2 // Register Declarations for Microchip 16F685 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define CCPR1L_ADDR 0x0015
46 #define CCPR1H_ADDR 0x0016
47 #define CCP1CON_ADDR 0x0017
48 #define PWM1CON_ADDR 0x001C
49 #define ECCPAS_ADDR 0x001D
50 #define ADRESH_ADDR 0x001E
51 #define ADCON0_ADDR 0x001F
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PIE2_ADDR 0x008D
58 #define PCON_ADDR 0x008E
59 #define OSCCON_ADDR 0x008F
60 #define OSCTUNE_ADDR 0x0090
61 #define PR2_ADDR 0x0092
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define WDTCON_ADDR 0x0097
67 #define ADRESL_ADDR 0x009E
68 #define ADCON1_ADDR 0x009F
69 #define EEDATA_ADDR 0x010C
70 #define EEADR_ADDR 0x010D
71 #define EEDATH_ADDR 0x010E
72 #define EEADRH_ADDR 0x010F
73 #define WPUB_ADDR 0x0115
74 #define IOCB_ADDR 0x0116
75 #define VRCON_ADDR 0x0118
76 #define CM1CON0_ADDR 0x0119
77 #define CM2CON0_ADDR 0x011A
78 #define CM2CON1_ADDR 0x011B
79 #define ANSEL_ADDR 0x011E
80 #define ANSELH_ADDR 0x011F
81 #define EECON1_ADDR 0x018C
82 #define EECON2_ADDR 0x018D
83 #define PSTRCON_ADDR 0x019D
84 #define SRCON_ADDR 0x019E
87 // Memory organization.
93 // P16F685.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
96 // This header file defines configurations, registers, and other useful bits of
97 // information for the PIC16F685 microcontroller. These names are taken to match
98 // the data sheets as closely as possible.
100 // Note that the processor must be selected before this file is
101 // included. The processor may be selected the following ways:
103 // 1. Command line switch:
104 // C:\ MPASM MYFILE.ASM /PIC16F685
105 // 2. LIST directive in the source file
107 // 3. Processor Type entry in the MPASM full-screen interface
109 //==========================================================================
113 //==========================================================================
114 //1.00 10/12/04 Original
115 //==========================================================================
119 //==========================================================================
122 // MESSG "Processor-header file mismatch. Verify selected processor."
125 //==========================================================================
127 // Register Definitions
129 //==========================================================================
134 //----- Register Files------------------------------------------------------
136 extern __data __at (INDF_ADDR) volatile char INDF;
137 extern __sfr __at (TMR0_ADDR) TMR0;
138 extern __data __at (PCL_ADDR) volatile char PCL;
139 extern __sfr __at (STATUS_ADDR) STATUS;
140 extern __sfr __at (FSR_ADDR) FSR;
141 extern __sfr __at (PORTA_ADDR) PORTA;
142 extern __sfr __at (PORTB_ADDR) PORTB;
143 extern __sfr __at (PORTC_ADDR) PORTC;
145 extern __sfr __at (PCLATH_ADDR) PCLATH;
146 extern __sfr __at (INTCON_ADDR) INTCON;
147 extern __sfr __at (PIR1_ADDR) PIR1;
148 extern __sfr __at (PIR2_ADDR) PIR2;
149 extern __sfr __at (TMR1L_ADDR) TMR1L;
150 extern __sfr __at (TMR1H_ADDR) TMR1H;
151 extern __sfr __at (T1CON_ADDR) T1CON;
152 extern __sfr __at (TMR2_ADDR) TMR2;
153 extern __sfr __at (T2CON_ADDR) T2CON;
156 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
157 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
158 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
161 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
162 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
163 extern __sfr __at (ADRESH_ADDR) ADRESH;
164 extern __sfr __at (ADCON0_ADDR) ADCON0;
167 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
169 extern __sfr __at (TRISA_ADDR) TRISA;
170 extern __sfr __at (TRISB_ADDR) TRISB;
171 extern __sfr __at (TRISC_ADDR) TRISC;
173 extern __sfr __at (PIE1_ADDR) PIE1;
174 extern __sfr __at (PIE2_ADDR) PIE2;
175 extern __sfr __at (PCON_ADDR) PCON;
176 extern __sfr __at (OSCCON_ADDR) OSCCON;
177 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
179 extern __sfr __at (PR2_ADDR) PR2;
182 extern __sfr __at (WPU_ADDR) WPU;
183 extern __sfr __at (WPUA_ADDR) WPUA;
184 extern __sfr __at (IOC_ADDR) IOC;
185 extern __sfr __at (IOCA_ADDR) IOCA;
186 extern __sfr __at (WDTCON_ADDR) WDTCON;
190 extern __sfr __at (ADRESL_ADDR) ADRESL;
191 extern __sfr __at (ADCON1_ADDR) ADCON1;
195 extern __sfr __at (EEDATA_ADDR) EEDATA;
196 extern __sfr __at (EEADR_ADDR) EEADR;
197 extern __sfr __at (EEDATH_ADDR) EEDATH;
198 extern __sfr __at (EEADRH_ADDR) EEADRH;
201 extern __sfr __at (WPUB_ADDR) WPUB;
202 extern __sfr __at (IOCB_ADDR) IOCB;
204 extern __sfr __at (VRCON_ADDR) VRCON;
205 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
206 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
207 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
209 extern __sfr __at (ANSEL_ADDR) ANSEL;
210 extern __sfr __at (ANSELH_ADDR) ANSELH;
212 extern __sfr __at (EECON1_ADDR) EECON1;
213 extern __sfr __at (EECON2_ADDR) EECON2;
216 extern __sfr __at (PSTRCON_ADDR) PSTRCON;
217 extern __sfr __at (SRCON_ADDR) SRCON;
221 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
222 //----- STATUS Bits --------------------------------------------------------
225 //----- INTCON Bits --------------------------------------------------------
228 //----- PIR1 Bits ----------------------------------------------------------
233 //----- PIR2 Bits ----------------------------------------------------------
236 //----- T1CON Bits ---------------------------------------------------------
239 //----- T2CON Bits ---------------------------------------------------------
243 //----- CCP1CON Bits -------------------------------------------------------
246 //----- PWM1CON Bits -------------------------------------------------------
249 //----- ECCPAS Bits --------------------------------------------------------
252 //----- ADCON0 Bits --------------------------------------------------------
255 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
256 //----- OPTION Bits --------------------------------------------------------
259 //----- TRISA Bits --------------------------------------------------------
262 //----- TRISB Bits --------------------------------------------------------
265 //----- TRISC Bits --------------------------------------------------------
268 //----- PIE1 Bits ----------------------------------------------------------
273 //----- PIE2 Bits ----------------------------------------------------------
276 //----- PCON Bits ----------------------------------------------------------
279 //----- OSCCON Bits --------------------------------------------------------
282 //----- OSCTUNE Bits -------------------------------------------------------
285 //----- WPUA --------------------------------------------------------------
289 //----- IOC --------------------------------------------------------------
292 //----- IOCA --------------------------------------------------------------
295 //----- WDTCON Bits --------------------------------------------------------
298 //----- ADCON1 -------------------------------------------------------------
301 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
302 //----- WPUB Bits ----------------------------------------------------------
305 //----- IOCB --------------------------------------------------------------
308 //----- VRCON Bits ---------------------------------------------------------
311 //----- CM1CON0 Bits -------------------------------------------------------
315 //----- CM2CON0 Bits -------------------------------------------------------
319 //----- CM2CON1 Bits -------------------------------------------------------
322 //----- ANSEL --------------------------------------------------------------
325 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
326 //----- EECON1 -------------------------------------------------------------
329 //----- PSTRCON -------------------------------------------------------------
332 //----- SRCON ---------------------------------------------------------------
335 //==========================================================================
339 //==========================================================================
342 // __BADRAM H'08'-H'09', H'13'-H'14', H'18'-H'1B'
343 // __BADRAM H'88'-H'89', H'91', H'93'-H'94', H'98'-H'9D'
344 // __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D'
345 // __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF'
347 //==========================================================================
349 // Configuration Bits
351 //==========================================================================
353 #define _FCMEN_ON 0x3FFF
354 #define _FCMEN_OFF 0x37FF
355 #define _IESO_ON 0x3FFF
356 #define _IESO_OFF 0x3BFF
357 #define _BOD_ON 0x3FFF
358 #define _BOD_NSLEEP 0x3EFF
359 #define _BOD_SBODEN 0x3DFF
360 #define _BOD_OFF 0x3CFF
361 #define _CPD_ON 0x3F7F
362 #define _CPD_OFF 0x3FFF
363 #define _CP_ON 0x3FBF
364 #define _CP_OFF 0x3FFF
365 #define _MCLRE_ON 0x3FFF
366 #define _MCLRE_OFF 0x3FDF
367 #define _PWRTE_OFF 0x3FFF
368 #define _PWRTE_ON 0x3FEF
369 #define _WDT_ON 0x3FFF
370 #define _WDT_OFF 0x3FF7
371 #define _LP_OSC 0x3FF8
372 #define _XT_OSC 0x3FF9
373 #define _HS_OSC 0x3FFA
374 #define _EC_OSC 0x3FFB
375 #define _INTRC_OSC_NOCLKOUT 0x3FFC
376 #define _INTRC_OSC_CLKOUT 0x3FFD
377 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
378 #define _EXTRC_OSC_CLKOUT 0x3FFF
379 #define _INTOSCIO 0x3FFC
380 #define _INTOSC 0x3FFD
381 #define _EXTRCIO 0x3FFE
382 #define _EXTRC 0x3FFF
386 // ----- ADCON0 bits --------------------
389 unsigned char ADON:1;
391 unsigned char CHS0:1;
392 unsigned char CHS1:1;
393 unsigned char CHS2:1;
394 unsigned char CHS3:1;
395 unsigned char VCFG:1;
396 unsigned char ADFM:1;
400 unsigned char NOT_DONE:1;
410 unsigned char GO_DONE:1;
419 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
421 #define ADON ADCON0_bits.ADON
422 #define GO ADCON0_bits.GO
423 #define NOT_DONE ADCON0_bits.NOT_DONE
424 #define GO_DONE ADCON0_bits.GO_DONE
425 #define CHS0 ADCON0_bits.CHS0
426 #define CHS1 ADCON0_bits.CHS1
427 #define CHS2 ADCON0_bits.CHS2
428 #define CHS3 ADCON0_bits.CHS3
429 #define VCFG ADCON0_bits.VCFG
430 #define ADFM ADCON0_bits.ADFM
432 // ----- CCP1CON bits --------------------
435 unsigned char CCP1M0:1;
436 unsigned char CCP1M1:1;
437 unsigned char CCP1M2:1;
438 unsigned char CCP1M3:1;
439 unsigned char DC1B0:1;
440 unsigned char DC1B1:1;
441 unsigned char P1M0:1;
442 unsigned char P1M1:1;
445 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
447 #define CCP1M0 CCP1CON_bits.CCP1M0
448 #define CCP1M1 CCP1CON_bits.CCP1M1
449 #define CCP1M2 CCP1CON_bits.CCP1M2
450 #define CCP1M3 CCP1CON_bits.CCP1M3
451 #define DC1B0 CCP1CON_bits.DC1B0
452 #define DC1B1 CCP1CON_bits.DC1B1
453 #define P1M0 CCP1CON_bits.P1M0
454 #define P1M1 CCP1CON_bits.P1M1
456 // ----- CM1CON0 bits --------------------
459 unsigned char C1CH0:1;
460 unsigned char C1CH1:1;
463 unsigned char C1POL:1;
464 unsigned char C1OE:1;
465 unsigned char C1OUT:1;
466 unsigned char C1ON:1;
469 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
471 #define C1CH0 CM1CON0_bits.C1CH0
472 #define C1CH1 CM1CON0_bits.C1CH1
473 #define C1R CM1CON0_bits.C1R
474 #define C1POL CM1CON0_bits.C1POL
475 #define C1OE CM1CON0_bits.C1OE
476 #define C1OUT CM1CON0_bits.C1OUT
477 #define C1ON CM1CON0_bits.C1ON
479 // ----- CM2CON0 bits --------------------
482 unsigned char C2CH0:1;
483 unsigned char C2CH1:1;
486 unsigned char C2POL:1;
487 unsigned char C2OE:1;
488 unsigned char C2OUT:1;
489 unsigned char C2ON:1;
492 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
494 #define C2CH0 CM2CON0_bits.C2CH0
495 #define C2CH1 CM2CON0_bits.C2CH1
496 #define C2R CM2CON0_bits.C2R
497 #define C2POL CM2CON0_bits.C2POL
498 #define C2OE CM2CON0_bits.C2OE
499 #define C2OUT CM2CON0_bits.C2OUT
500 #define C2ON CM2CON0_bits.C2ON
502 // ----- CM2CON1 bits --------------------
505 unsigned char C2SYNC:1;
506 unsigned char T1GSS:1;
507 unsigned char ANS2:1;
508 unsigned char ANS3:1;
509 unsigned char ANS4:1;
510 unsigned char ANS5:1;
511 unsigned char MC2OUT:1;
512 unsigned char MC1OUT:1;
515 unsigned char ANS0:1;
516 unsigned char ANS1:1;
517 unsigned char WREN:1;
518 unsigned char WRERR:1;
519 unsigned char STRSYNC:1;
520 unsigned char C1SEN:1;
521 unsigned char ANS6:1;
522 unsigned char ANS7:1;
527 unsigned char STRC:1;
528 unsigned char STRD:1;
529 unsigned char C2REN:1;
532 unsigned char EEPGD:1;
535 unsigned char STRA:1;
536 unsigned char STRB:1;
537 unsigned char PULSR:1;
538 unsigned char PULSS:1;
545 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
547 #define C2SYNC CM2CON1_bits.C2SYNC
548 #define ANS0 CM2CON1_bits.ANS0
549 #define RD CM2CON1_bits.RD
550 #define STRA CM2CON1_bits.STRA
551 #define T1GSS CM2CON1_bits.T1GSS
552 #define ANS1 CM2CON1_bits.ANS1
553 #define WR CM2CON1_bits.WR
554 #define STRB CM2CON1_bits.STRB
555 #define ANS2 CM2CON1_bits.ANS2
556 #define WREN CM2CON1_bits.WREN
557 #define STRC CM2CON1_bits.STRC
558 #define PULSR CM2CON1_bits.PULSR
559 #define ANS3 CM2CON1_bits.ANS3
560 #define WRERR CM2CON1_bits.WRERR
561 #define STRD CM2CON1_bits.STRD
562 #define PULSS CM2CON1_bits.PULSS
563 #define ANS4 CM2CON1_bits.ANS4
564 #define STRSYNC CM2CON1_bits.STRSYNC
565 #define C2REN CM2CON1_bits.C2REN
566 #define ANS5 CM2CON1_bits.ANS5
567 #define C1SEN CM2CON1_bits.C1SEN
568 #define MC2OUT CM2CON1_bits.MC2OUT
569 #define ANS6 CM2CON1_bits.ANS6
570 #define SR0 CM2CON1_bits.SR0
571 #define MC1OUT CM2CON1_bits.MC1OUT
572 #define ANS7 CM2CON1_bits.ANS7
573 #define EEPGD CM2CON1_bits.EEPGD
574 #define SR1 CM2CON1_bits.SR1
576 // ----- ECCPAS bits --------------------
579 unsigned char PSSBD0:1;
580 unsigned char PSSBD1:1;
581 unsigned char PSSAC0:1;
582 unsigned char PSSAC1:1;
583 unsigned char ECCPAS0:1;
584 unsigned char ECCPAS1:1;
585 unsigned char ECCPAS2:1;
586 unsigned char ECCPASE:1;
589 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
591 #define PSSBD0 ECCPAS_bits.PSSBD0
592 #define PSSBD1 ECCPAS_bits.PSSBD1
593 #define PSSAC0 ECCPAS_bits.PSSAC0
594 #define PSSAC1 ECCPAS_bits.PSSAC1
595 #define ECCPAS0 ECCPAS_bits.ECCPAS0
596 #define ECCPAS1 ECCPAS_bits.ECCPAS1
597 #define ECCPAS2 ECCPAS_bits.ECCPAS2
598 #define ECCPASE ECCPAS_bits.ECCPASE
600 // ----- INTCON bits --------------------
603 unsigned char RABIF:1;
604 unsigned char INTF:1;
605 unsigned char T0IF:1;
606 unsigned char RABIE:1;
607 unsigned char INTE:1;
608 unsigned char T0IE:1;
609 unsigned char PEIE:1;
613 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
615 #define RABIF INTCON_bits.RABIF
616 #define INTF INTCON_bits.INTF
617 #define T0IF INTCON_bits.T0IF
618 #define RABIE INTCON_bits.RABIE
619 #define INTE INTCON_bits.INTE
620 #define T0IE INTCON_bits.T0IE
621 #define PEIE INTCON_bits.PEIE
622 #define GIE INTCON_bits.GIE
624 // ----- OPTION_REG bits --------------------
631 unsigned char T0SE:1;
632 unsigned char T0CS:1;
633 unsigned char INTEDG:1;
634 unsigned char NOT_RABPU:1;
636 } __OPTION_REG_bits_t;
637 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
639 #define PS0 OPTION_REG_bits.PS0
640 #define PS1 OPTION_REG_bits.PS1
641 #define PS2 OPTION_REG_bits.PS2
642 #define PSA OPTION_REG_bits.PSA
643 #define T0SE OPTION_REG_bits.T0SE
644 #define T0CS OPTION_REG_bits.T0CS
645 #define INTEDG OPTION_REG_bits.INTEDG
646 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
648 // ----- OSCCON bits --------------------
654 unsigned char OSTS:1;
655 unsigned char IRCF0:1;
656 unsigned char IRCF1:1;
657 unsigned char IRCF2:1;
661 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
663 #define SCS OSCCON_bits.SCS
664 #define LTS OSCCON_bits.LTS
665 #define HTS OSCCON_bits.HTS
666 #define OSTS OSCCON_bits.OSTS
667 #define IRCF0 OSCCON_bits.IRCF0
668 #define IRCF1 OSCCON_bits.IRCF1
669 #define IRCF2 OSCCON_bits.IRCF2
671 // ----- OSCTUNE bits --------------------
674 unsigned char TUN0:1;
675 unsigned char TUN1:1;
676 unsigned char TUN2:1;
677 unsigned char TUN3:1;
678 unsigned char TUN4:1;
679 unsigned char WPUA5:1;
684 unsigned char WPUA0:1;
685 unsigned char WPUA1:1;
686 unsigned char WPUA2:1;
687 unsigned char IOC3:1;
688 unsigned char WPUA4:1;
689 unsigned char IOC5:1;
694 unsigned char IOC0:1;
695 unsigned char IOC1:1;
696 unsigned char IOC2:1;
697 unsigned char IOCA3:1;
698 unsigned char IOC4:1;
699 unsigned char IOCA5:1;
704 unsigned char IOCA0:1;
705 unsigned char IOCA1:1;
706 unsigned char IOCA2:1;
708 unsigned char IOCA4:1;
714 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
716 #define TUN0 OSCTUNE_bits.TUN0
717 #define WPUA0 OSCTUNE_bits.WPUA0
718 #define IOC0 OSCTUNE_bits.IOC0
719 #define IOCA0 OSCTUNE_bits.IOCA0
720 #define TUN1 OSCTUNE_bits.TUN1
721 #define WPUA1 OSCTUNE_bits.WPUA1
722 #define IOC1 OSCTUNE_bits.IOC1
723 #define IOCA1 OSCTUNE_bits.IOCA1
724 #define TUN2 OSCTUNE_bits.TUN2
725 #define WPUA2 OSCTUNE_bits.WPUA2
726 #define IOC2 OSCTUNE_bits.IOC2
727 #define IOCA2 OSCTUNE_bits.IOCA2
728 #define TUN3 OSCTUNE_bits.TUN3
729 #define IOC3 OSCTUNE_bits.IOC3
730 #define IOCA3 OSCTUNE_bits.IOCA3
731 #define TUN4 OSCTUNE_bits.TUN4
732 #define WPUA4 OSCTUNE_bits.WPUA4
733 #define IOC4 OSCTUNE_bits.IOC4
734 #define IOCA4 OSCTUNE_bits.IOCA4
735 #define WPUA5 OSCTUNE_bits.WPUA5
736 #define IOC5 OSCTUNE_bits.IOC5
737 #define IOCA5 OSCTUNE_bits.IOCA5
739 // ----- PCON bits --------------------
742 unsigned char NOT_BOD:1;
743 unsigned char NOT_POR:1;
746 unsigned char SBODEN:1;
747 unsigned char ULPWUE:1;
752 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
754 #define NOT_BOD PCON_bits.NOT_BOD
755 #define NOT_POR PCON_bits.NOT_POR
756 #define SBODEN PCON_bits.SBODEN
757 #define ULPWUE PCON_bits.ULPWUE
759 // ----- PIE1 bits --------------------
762 unsigned char T1IE:1;
763 unsigned char T2IE:1;
764 unsigned char CCPIE:1;
768 unsigned char ADIE:1;
772 unsigned char TMR1IE:1;
773 unsigned char TMR2IE:1;
782 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
784 #define T1IE PIE1_bits.T1IE
785 #define TMR1IE PIE1_bits.TMR1IE
786 #define T2IE PIE1_bits.T2IE
787 #define TMR2IE PIE1_bits.TMR2IE
788 #define CCPIE PIE1_bits.CCPIE
789 #define ADIE PIE1_bits.ADIE
791 // ----- PIE2 bits --------------------
798 unsigned char EEIE:1;
799 unsigned char C1IE:1;
800 unsigned char C2IE:1;
801 unsigned char OSFIE:1;
804 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
806 #define EEIE PIE2_bits.EEIE
807 #define C1IE PIE2_bits.C1IE
808 #define C2IE PIE2_bits.C2IE
809 #define OSFIE PIE2_bits.OSFIE
811 // ----- PIR1 bits --------------------
814 unsigned char T1IF:1;
815 unsigned char T2IF:1;
816 unsigned char CCP1IF:1;
820 unsigned char ADIF:1;
824 unsigned char TMR1IF:1;
825 unsigned char TMR2IF:1;
834 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
836 #define T1IF PIR1_bits.T1IF
837 #define TMR1IF PIR1_bits.TMR1IF
838 #define T2IF PIR1_bits.T2IF
839 #define TMR2IF PIR1_bits.TMR2IF
840 #define CCP1IF PIR1_bits.CCP1IF
841 #define ADIF PIR1_bits.ADIF
843 // ----- PIR2 bits --------------------
850 unsigned char EEIF:1;
851 unsigned char C1IF:1;
852 unsigned char C2IF:1;
853 unsigned char OSFIF:1;
856 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
858 #define EEIF PIR2_bits.EEIF
859 #define C1IF PIR2_bits.C1IF
860 #define C2IF PIR2_bits.C2IF
861 #define OSFIF PIR2_bits.OSFIF
863 // ----- PWM1CON bits --------------------
866 unsigned char PDC0:1;
867 unsigned char PDC1:1;
868 unsigned char PDC2:1;
869 unsigned char PDC3:1;
870 unsigned char PDC4:1;
871 unsigned char PDC5:1;
872 unsigned char PDC6:1;
873 unsigned char PRSEN:1;
876 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
878 #define PDC0 PWM1CON_bits.PDC0
879 #define PDC1 PWM1CON_bits.PDC1
880 #define PDC2 PWM1CON_bits.PDC2
881 #define PDC3 PWM1CON_bits.PDC3
882 #define PDC4 PWM1CON_bits.PDC4
883 #define PDC5 PWM1CON_bits.PDC5
884 #define PDC6 PWM1CON_bits.PDC6
885 #define PRSEN PWM1CON_bits.PRSEN
887 // ----- STATUS bits --------------------
893 unsigned char NOT_PD:1;
894 unsigned char NOT_TO:1;
900 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
902 #define C STATUS_bits.C
903 #define DC STATUS_bits.DC
904 #define Z STATUS_bits.Z
905 #define NOT_PD STATUS_bits.NOT_PD
906 #define NOT_TO STATUS_bits.NOT_TO
907 #define RP0 STATUS_bits.RP0
908 #define RP1 STATUS_bits.RP1
909 #define IRP STATUS_bits.IRP
911 // ----- T1CON bits --------------------
914 unsigned char TMR1ON:1;
915 unsigned char TMR1CS:1;
916 unsigned char NOT_T1SYNC:1;
917 unsigned char T1OSCEN:1;
918 unsigned char T1CKPS0:1;
919 unsigned char T1CKPS1:1;
920 unsigned char TMR1GE:1;
921 unsigned char T1GINV:1;
924 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
926 #define TMR1ON T1CON_bits.TMR1ON
927 #define TMR1CS T1CON_bits.TMR1CS
928 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
929 #define T1OSCEN T1CON_bits.T1OSCEN
930 #define T1CKPS0 T1CON_bits.T1CKPS0
931 #define T1CKPS1 T1CON_bits.T1CKPS1
932 #define TMR1GE T1CON_bits.TMR1GE
933 #define T1GINV T1CON_bits.T1GINV
935 // ----- T2CON bits --------------------
938 unsigned char T2CKPS0:1;
939 unsigned char T2CKPS1:1;
940 unsigned char TMR2ON:1;
941 unsigned char TOUTPS0:1;
942 unsigned char TOUTPS1:1;
943 unsigned char TOUTPS2:1;
944 unsigned char TOUTPS3:1;
948 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
950 #define T2CKPS0 T2CON_bits.T2CKPS0
951 #define T2CKPS1 T2CON_bits.T2CKPS1
952 #define TMR2ON T2CON_bits.TMR2ON
953 #define TOUTPS0 T2CON_bits.TOUTPS0
954 #define TOUTPS1 T2CON_bits.TOUTPS1
955 #define TOUTPS2 T2CON_bits.TOUTPS2
956 #define TOUTPS3 T2CON_bits.TOUTPS3
958 // ----- TRISA bits --------------------
961 unsigned char TRISA0:1;
962 unsigned char TRISA1:1;
963 unsigned char TRISA2:1;
964 unsigned char TRISA3:1;
965 unsigned char TRISA4:1;
966 unsigned char TRISA5:1;
971 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
973 #define TRISA0 TRISA_bits.TRISA0
974 #define TRISA1 TRISA_bits.TRISA1
975 #define TRISA2 TRISA_bits.TRISA2
976 #define TRISA3 TRISA_bits.TRISA3
977 #define TRISA4 TRISA_bits.TRISA4
978 #define TRISA5 TRISA_bits.TRISA5
980 // ----- TRISB bits --------------------
987 unsigned char TRISB4:1;
988 unsigned char TRISB5:1;
989 unsigned char TRISB6:1;
990 unsigned char TRISB7:1;
993 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
995 #define TRISB4 TRISB_bits.TRISB4
996 #define TRISB5 TRISB_bits.TRISB5
997 #define TRISB6 TRISB_bits.TRISB6
998 #define TRISB7 TRISB_bits.TRISB7
1000 // ----- TRISC bits --------------------
1003 unsigned char TRISC0:1;
1004 unsigned char TRISC1:1;
1005 unsigned char TRISC2:1;
1006 unsigned char TRISC3:1;
1007 unsigned char TRISC4:1;
1008 unsigned char TRISC5:1;
1009 unsigned char TRISC6:1;
1010 unsigned char TRISC7:1;
1013 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1015 #define TRISC0 TRISC_bits.TRISC0
1016 #define TRISC1 TRISC_bits.TRISC1
1017 #define TRISC2 TRISC_bits.TRISC2
1018 #define TRISC3 TRISC_bits.TRISC3
1019 #define TRISC4 TRISC_bits.TRISC4
1020 #define TRISC5 TRISC_bits.TRISC5
1021 #define TRISC6 TRISC_bits.TRISC6
1022 #define TRISC7 TRISC_bits.TRISC7
1024 // ----- VRCON bits --------------------
1027 unsigned char VR0:1;
1028 unsigned char VR1:1;
1029 unsigned char VR2:1;
1030 unsigned char VR3:1;
1031 unsigned char VP6EN:1;
1032 unsigned char VRR:1;
1033 unsigned char C2VREN:1;
1034 unsigned char C1VREN:1;
1037 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1039 #define VR0 VRCON_bits.VR0
1040 #define VR1 VRCON_bits.VR1
1041 #define VR2 VRCON_bits.VR2
1042 #define VR3 VRCON_bits.VR3
1043 #define VP6EN VRCON_bits.VP6EN
1044 #define VRR VRCON_bits.VRR
1045 #define C2VREN VRCON_bits.C2VREN
1046 #define C1VREN VRCON_bits.C1VREN
1048 // ----- WDTCON bits --------------------
1051 unsigned char SWDTEN:1;
1052 unsigned char WDTPS0:1;
1053 unsigned char WDTPS1:1;
1054 unsigned char WDTPS2:1;
1055 unsigned char WDTPS3:1;
1056 unsigned char ADCS1:1;
1057 unsigned char ADCS2:1;
1065 unsigned char ADCS0:1;
1071 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1073 #define SWDTEN WDTCON_bits.SWDTEN
1074 #define WDTPS0 WDTCON_bits.WDTPS0
1075 #define WDTPS1 WDTCON_bits.WDTPS1
1076 #define WDTPS2 WDTCON_bits.WDTPS2
1077 #define WDTPS3 WDTCON_bits.WDTPS3
1078 #define ADCS0 WDTCON_bits.ADCS0
1079 #define ADCS1 WDTCON_bits.ADCS1
1080 #define ADCS2 WDTCON_bits.ADCS2
1082 // ----- WPUB bits --------------------
1089 unsigned char WPUB4:1;
1090 unsigned char WPUB5:1;
1091 unsigned char WPUB6:1;
1092 unsigned char WPUB7:1;
1099 unsigned char IOCB4:1;
1100 unsigned char IOCB5:1;
1101 unsigned char IOCB6:1;
1102 unsigned char IOCB7:1;
1105 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1107 #define WPUB4 WPUB_bits.WPUB4
1108 #define IOCB4 WPUB_bits.IOCB4
1109 #define WPUB5 WPUB_bits.WPUB5
1110 #define IOCB5 WPUB_bits.IOCB5
1111 #define WPUB6 WPUB_bits.WPUB6
1112 #define IOCB6 WPUB_bits.IOCB6
1113 #define WPUB7 WPUB_bits.WPUB7
1114 #define IOCB7 WPUB_bits.IOCB7