2 // Register Declarations for Microchip 16F685 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define CCPR1L_ADDR 0x0015
46 #define CCPR1H_ADDR 0x0016
47 #define CCP1CON_ADDR 0x0017
48 #define PWM1CON_ADDR 0x001C
49 #define ECCPAS_ADDR 0x001D
50 #define ADRESH_ADDR 0x001E
51 #define ADCON0_ADDR 0x001F
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PIE2_ADDR 0x008D
58 #define PCON_ADDR 0x008E
59 #define OSCCON_ADDR 0x008F
60 #define OSCTUNE_ADDR 0x0090
61 #define PR2_ADDR 0x0092
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define WDTCON_ADDR 0x0097
67 #define ADRESL_ADDR 0x009E
68 #define ADCON1_ADDR 0x009F
69 #define EEDATA_ADDR 0x010C
70 #define EEADR_ADDR 0x010D
71 #define EEDATH_ADDR 0x010E
72 #define EEADRH_ADDR 0x010F
73 #define WPUB_ADDR 0x0115
74 #define IOCB_ADDR 0x0116
75 #define VRCON_ADDR 0x0118
76 #define CM1CON0_ADDR 0x0119
77 #define CM2CON0_ADDR 0x011A
78 #define CM2CON1_ADDR 0x011B
79 #define ANSEL_ADDR 0x011E
80 #define ANSELH_ADDR 0x011F
81 #define EECON1_ADDR 0x018C
82 #define EECON2_ADDR 0x018D
83 #define PSTRCON_ADDR 0x019D
84 #define SRCON_ADDR 0x019E
87 // Memory organization.
90 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
91 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
92 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
93 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
94 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
95 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
96 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
97 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
98 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
99 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
100 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
101 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
102 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
103 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
104 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
105 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
106 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
107 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
108 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
109 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
110 #pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON
111 #pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS
112 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
113 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
114 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
115 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
116 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
117 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
118 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
119 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
120 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
121 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
122 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
123 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
124 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
125 #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
126 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
127 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
128 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
129 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
130 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
131 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
132 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
133 #pragma memmap EEDATH_ADDR EEDATH_ADDR SFR 0x000 // EEDATH
134 #pragma memmap EEADRH_ADDR EEADRH_ADDR SFR 0x000 // EEADRH
135 #pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB
136 #pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
137 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
138 #pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0
139 #pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0
140 #pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1
141 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
142 #pragma memmap ANSELH_ADDR ANSELH_ADDR SFR 0x000 // ANSELH
143 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
144 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
145 #pragma memmap PSTRCON_ADDR PSTRCON_ADDR SFR 0x000 // PSTRCON
146 #pragma memmap SRCON_ADDR SRCON_ADDR SFR 0x000 // SRCON
150 // P16F685.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
153 // This header file defines configurations, registers, and other useful bits of
154 // information for the PIC16F685 microcontroller. These names are taken to match
155 // the data sheets as closely as possible.
157 // Note that the processor must be selected before this file is
158 // included. The processor may be selected the following ways:
160 // 1. Command line switch:
161 // C:\ MPASM MYFILE.ASM /PIC16F685
162 // 2. LIST directive in the source file
164 // 3. Processor Type entry in the MPASM full-screen interface
166 //==========================================================================
170 //==========================================================================
171 //1.00 10/12/04 Original
172 //==========================================================================
176 //==========================================================================
179 // MESSG "Processor-header file mismatch. Verify selected processor."
182 //==========================================================================
184 // Register Definitions
186 //==========================================================================
191 //----- Register Files------------------------------------------------------
193 extern data __at (INDF_ADDR) volatile char INDF;
194 extern sfr __at (TMR0_ADDR) TMR0;
195 extern data __at (PCL_ADDR) volatile char PCL;
196 extern sfr __at (STATUS_ADDR) STATUS;
197 extern sfr __at (FSR_ADDR) FSR;
198 extern sfr __at (PORTA_ADDR) PORTA;
199 extern sfr __at (PORTB_ADDR) PORTB;
200 extern sfr __at (PORTC_ADDR) PORTC;
202 extern sfr __at (PCLATH_ADDR) PCLATH;
203 extern sfr __at (INTCON_ADDR) INTCON;
204 extern sfr __at (PIR1_ADDR) PIR1;
205 extern sfr __at (PIR2_ADDR) PIR2;
206 extern sfr __at (TMR1L_ADDR) TMR1L;
207 extern sfr __at (TMR1H_ADDR) TMR1H;
208 extern sfr __at (T1CON_ADDR) T1CON;
209 extern sfr __at (TMR2_ADDR) TMR2;
210 extern sfr __at (T2CON_ADDR) T2CON;
213 extern sfr __at (CCPR1L_ADDR) CCPR1L;
214 extern sfr __at (CCPR1H_ADDR) CCPR1H;
215 extern sfr __at (CCP1CON_ADDR) CCP1CON;
218 extern sfr __at (PWM1CON_ADDR) PWM1CON;
219 extern sfr __at (ECCPAS_ADDR) ECCPAS;
220 extern sfr __at (ADRESH_ADDR) ADRESH;
221 extern sfr __at (ADCON0_ADDR) ADCON0;
224 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
226 extern sfr __at (TRISA_ADDR) TRISA;
227 extern sfr __at (TRISB_ADDR) TRISB;
228 extern sfr __at (TRISC_ADDR) TRISC;
230 extern sfr __at (PIE1_ADDR) PIE1;
231 extern sfr __at (PIE2_ADDR) PIE2;
232 extern sfr __at (PCON_ADDR) PCON;
233 extern sfr __at (OSCCON_ADDR) OSCCON;
234 extern sfr __at (OSCTUNE_ADDR) OSCTUNE;
236 extern sfr __at (PR2_ADDR) PR2;
239 extern sfr __at (WPU_ADDR) WPU;
240 extern sfr __at (WPUA_ADDR) WPUA;
241 extern sfr __at (IOC_ADDR) IOC;
242 extern sfr __at (IOCA_ADDR) IOCA;
243 extern sfr __at (WDTCON_ADDR) WDTCON;
247 extern sfr __at (ADRESL_ADDR) ADRESL;
248 extern sfr __at (ADCON1_ADDR) ADCON1;
252 extern sfr __at (EEDATA_ADDR) EEDATA;
253 extern sfr __at (EEADR_ADDR) EEADR;
254 extern sfr __at (EEDATH_ADDR) EEDATH;
255 extern sfr __at (EEADRH_ADDR) EEADRH;
258 extern sfr __at (WPUB_ADDR) WPUB;
259 extern sfr __at (IOCB_ADDR) IOCB;
261 extern sfr __at (VRCON_ADDR) VRCON;
262 extern sfr __at (CM1CON0_ADDR) CM1CON0;
263 extern sfr __at (CM2CON0_ADDR) CM2CON0;
264 extern sfr __at (CM2CON1_ADDR) CM2CON1;
266 extern sfr __at (ANSEL_ADDR) ANSEL;
267 extern sfr __at (ANSELH_ADDR) ANSELH;
269 extern sfr __at (EECON1_ADDR) EECON1;
270 extern sfr __at (EECON2_ADDR) EECON2;
273 extern sfr __at (PSTRCON_ADDR) PSTRCON;
274 extern sfr __at (SRCON_ADDR) SRCON;
278 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
279 //----- STATUS Bits --------------------------------------------------------
282 //----- INTCON Bits --------------------------------------------------------
285 //----- PIR1 Bits ----------------------------------------------------------
290 //----- PIR2 Bits ----------------------------------------------------------
293 //----- T1CON Bits ---------------------------------------------------------
296 //----- T2CON Bits ---------------------------------------------------------
300 //----- CCP1CON Bits -------------------------------------------------------
303 //----- PWM1CON Bits -------------------------------------------------------
306 //----- ECCPAS Bits --------------------------------------------------------
309 //----- ADCON0 Bits --------------------------------------------------------
312 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
313 //----- OPTION Bits --------------------------------------------------------
316 //----- TRISA Bits --------------------------------------------------------
319 //----- TRISB Bits --------------------------------------------------------
322 //----- TRISC Bits --------------------------------------------------------
325 //----- PIE1 Bits ----------------------------------------------------------
330 //----- PIE2 Bits ----------------------------------------------------------
333 //----- PCON Bits ----------------------------------------------------------
336 //----- OSCCON Bits --------------------------------------------------------
339 //----- OSCTUNE Bits -------------------------------------------------------
342 //----- WPUA --------------------------------------------------------------
346 //----- IOC --------------------------------------------------------------
349 //----- IOCA --------------------------------------------------------------
352 //----- WDTCON Bits --------------------------------------------------------
355 //----- ADCON1 -------------------------------------------------------------
358 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
359 //----- WPUB Bits ----------------------------------------------------------
362 //----- IOCB --------------------------------------------------------------
365 //----- VRCON Bits ---------------------------------------------------------
368 //----- CM1CON0 Bits -------------------------------------------------------
372 //----- CM2CON0 Bits -------------------------------------------------------
376 //----- CM2CON1 Bits -------------------------------------------------------
379 //----- ANSEL --------------------------------------------------------------
382 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
383 //----- EECON1 -------------------------------------------------------------
386 //----- PSTRCON -------------------------------------------------------------
389 //----- SRCON ---------------------------------------------------------------
392 //==========================================================================
396 //==========================================================================
399 // __BADRAM H'08'-H'09', H'13'-H'14', H'18'-H'1B'
400 // __BADRAM H'88'-H'89', H'91', H'93'-H'94', H'98'-H'9D'
401 // __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D'
402 // __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF'
404 //==========================================================================
406 // Configuration Bits
408 //==========================================================================
410 #define _FCMEN_ON 0x3FFF
411 #define _FCMEN_OFF 0x37FF
412 #define _IESO_ON 0x3FFF
413 #define _IESO_OFF 0x3BFF
414 #define _BOD_ON 0x3FFF
415 #define _BOD_NSLEEP 0x3EFF
416 #define _BOD_SBODEN 0x3DFF
417 #define _BOD_OFF 0x3CFF
418 #define _CPD_ON 0x3F7F
419 #define _CPD_OFF 0x3FFF
420 #define _CP_ON 0x3FBF
421 #define _CP_OFF 0x3FFF
422 #define _MCLRE_ON 0x3FFF
423 #define _MCLRE_OFF 0x3FDF
424 #define _PWRTE_OFF 0x3FFF
425 #define _PWRTE_ON 0x3FEF
426 #define _WDT_ON 0x3FFF
427 #define _WDT_OFF 0x3FF7
428 #define _LP_OSC 0x3FF8
429 #define _XT_OSC 0x3FF9
430 #define _HS_OSC 0x3FFA
431 #define _EC_OSC 0x3FFB
432 #define _INTRC_OSC_NOCLKOUT 0x3FFC
433 #define _INTRC_OSC_CLKOUT 0x3FFD
434 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
435 #define _EXTRC_OSC_CLKOUT 0x3FFF
436 #define _INTOSCIO 0x3FFC
437 #define _INTOSC 0x3FFD
438 #define _EXTRCIO 0x3FFE
439 #define _EXTRC 0x3FFF
443 // ----- ADCON0 bits --------------------
446 unsigned char ADON:1;
448 unsigned char CHS0:1;
449 unsigned char CHS1:1;
450 unsigned char CHS2:1;
451 unsigned char CHS3:1;
452 unsigned char VCFG:1;
453 unsigned char ADFM:1;
457 unsigned char NOT_DONE:1;
467 unsigned char GO_DONE:1;
476 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
478 #define ADON ADCON0_bits.ADON
479 #define GO ADCON0_bits.GO
480 #define NOT_DONE ADCON0_bits.NOT_DONE
481 #define GO_DONE ADCON0_bits.GO_DONE
482 #define CHS0 ADCON0_bits.CHS0
483 #define CHS1 ADCON0_bits.CHS1
484 #define CHS2 ADCON0_bits.CHS2
485 #define CHS3 ADCON0_bits.CHS3
486 #define VCFG ADCON0_bits.VCFG
487 #define ADFM ADCON0_bits.ADFM
489 // ----- CCP1CON bits --------------------
492 unsigned char CCP1M0:1;
493 unsigned char CCP1M1:1;
494 unsigned char CCP1M2:1;
495 unsigned char CCP1M3:1;
496 unsigned char DC1B0:1;
497 unsigned char DC1B1:1;
498 unsigned char P1M0:1;
499 unsigned char P1M1:1;
502 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
504 #define CCP1M0 CCP1CON_bits.CCP1M0
505 #define CCP1M1 CCP1CON_bits.CCP1M1
506 #define CCP1M2 CCP1CON_bits.CCP1M2
507 #define CCP1M3 CCP1CON_bits.CCP1M3
508 #define DC1B0 CCP1CON_bits.DC1B0
509 #define DC1B1 CCP1CON_bits.DC1B1
510 #define P1M0 CCP1CON_bits.P1M0
511 #define P1M1 CCP1CON_bits.P1M1
513 // ----- CM1CON0 bits --------------------
516 unsigned char C1CH0:1;
517 unsigned char C1CH1:1;
520 unsigned char C1POL:1;
521 unsigned char C1OE:1;
522 unsigned char C1OUT:1;
523 unsigned char C1ON:1;
526 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
528 #define C1CH0 CM1CON0_bits.C1CH0
529 #define C1CH1 CM1CON0_bits.C1CH1
530 #define C1R CM1CON0_bits.C1R
531 #define C1POL CM1CON0_bits.C1POL
532 #define C1OE CM1CON0_bits.C1OE
533 #define C1OUT CM1CON0_bits.C1OUT
534 #define C1ON CM1CON0_bits.C1ON
536 // ----- CM2CON0 bits --------------------
539 unsigned char C2CH0:1;
540 unsigned char C2CH1:1;
543 unsigned char C2POL:1;
544 unsigned char C2OE:1;
545 unsigned char C2OUT:1;
546 unsigned char C2ON:1;
549 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
551 #define C2CH0 CM2CON0_bits.C2CH0
552 #define C2CH1 CM2CON0_bits.C2CH1
553 #define C2R CM2CON0_bits.C2R
554 #define C2POL CM2CON0_bits.C2POL
555 #define C2OE CM2CON0_bits.C2OE
556 #define C2OUT CM2CON0_bits.C2OUT
557 #define C2ON CM2CON0_bits.C2ON
559 // ----- CM2CON1 bits --------------------
562 unsigned char C2SYNC:1;
563 unsigned char T1GSS:1;
564 unsigned char ANS2:1;
565 unsigned char ANS3:1;
566 unsigned char ANS4:1;
567 unsigned char ANS5:1;
568 unsigned char MC2OUT:1;
569 unsigned char MC1OUT:1;
572 unsigned char ANS0:1;
573 unsigned char ANS1:1;
574 unsigned char WREN:1;
575 unsigned char WRERR:1;
576 unsigned char STRSYNC:1;
577 unsigned char C1SEN:1;
578 unsigned char ANS6:1;
579 unsigned char ANS7:1;
584 unsigned char STRC:1;
585 unsigned char STRD:1;
586 unsigned char C2REN:1;
589 unsigned char EEPGD:1;
592 unsigned char STRA:1;
593 unsigned char STRB:1;
594 unsigned char PULSR:1;
595 unsigned char PULSS:1;
602 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
604 #define C2SYNC CM2CON1_bits.C2SYNC
605 #define ANS0 CM2CON1_bits.ANS0
606 #define RD CM2CON1_bits.RD
607 #define STRA CM2CON1_bits.STRA
608 #define T1GSS CM2CON1_bits.T1GSS
609 #define ANS1 CM2CON1_bits.ANS1
610 #define WR CM2CON1_bits.WR
611 #define STRB CM2CON1_bits.STRB
612 #define ANS2 CM2CON1_bits.ANS2
613 #define WREN CM2CON1_bits.WREN
614 #define STRC CM2CON1_bits.STRC
615 #define PULSR CM2CON1_bits.PULSR
616 #define ANS3 CM2CON1_bits.ANS3
617 #define WRERR CM2CON1_bits.WRERR
618 #define STRD CM2CON1_bits.STRD
619 #define PULSS CM2CON1_bits.PULSS
620 #define ANS4 CM2CON1_bits.ANS4
621 #define STRSYNC CM2CON1_bits.STRSYNC
622 #define C2REN CM2CON1_bits.C2REN
623 #define ANS5 CM2CON1_bits.ANS5
624 #define C1SEN CM2CON1_bits.C1SEN
625 #define MC2OUT CM2CON1_bits.MC2OUT
626 #define ANS6 CM2CON1_bits.ANS6
627 #define SR0 CM2CON1_bits.SR0
628 #define MC1OUT CM2CON1_bits.MC1OUT
629 #define ANS7 CM2CON1_bits.ANS7
630 #define EEPGD CM2CON1_bits.EEPGD
631 #define SR1 CM2CON1_bits.SR1
633 // ----- ECCPAS bits --------------------
636 unsigned char PSSBD0:1;
637 unsigned char PSSBD1:1;
638 unsigned char PSSAC0:1;
639 unsigned char PSSAC1:1;
640 unsigned char ECCPAS0:1;
641 unsigned char ECCPAS1:1;
642 unsigned char ECCPAS2:1;
643 unsigned char ECCPASE:1;
646 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
648 #define PSSBD0 ECCPAS_bits.PSSBD0
649 #define PSSBD1 ECCPAS_bits.PSSBD1
650 #define PSSAC0 ECCPAS_bits.PSSAC0
651 #define PSSAC1 ECCPAS_bits.PSSAC1
652 #define ECCPAS0 ECCPAS_bits.ECCPAS0
653 #define ECCPAS1 ECCPAS_bits.ECCPAS1
654 #define ECCPAS2 ECCPAS_bits.ECCPAS2
655 #define ECCPASE ECCPAS_bits.ECCPASE
657 // ----- INTCON bits --------------------
660 unsigned char RABIF:1;
661 unsigned char INTF:1;
662 unsigned char T0IF:1;
663 unsigned char RABIE:1;
664 unsigned char INTE:1;
665 unsigned char T0IE:1;
666 unsigned char PEIE:1;
670 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
672 #define RABIF INTCON_bits.RABIF
673 #define INTF INTCON_bits.INTF
674 #define T0IF INTCON_bits.T0IF
675 #define RABIE INTCON_bits.RABIE
676 #define INTE INTCON_bits.INTE
677 #define T0IE INTCON_bits.T0IE
678 #define PEIE INTCON_bits.PEIE
679 #define GIE INTCON_bits.GIE
681 // ----- OPTION_REG bits --------------------
688 unsigned char T0SE:1;
689 unsigned char T0CS:1;
690 unsigned char INTEDG:1;
691 unsigned char NOT_RABPU:1;
693 } __OPTION_REG_bits_t;
694 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
696 #define PS0 OPTION_REG_bits.PS0
697 #define PS1 OPTION_REG_bits.PS1
698 #define PS2 OPTION_REG_bits.PS2
699 #define PSA OPTION_REG_bits.PSA
700 #define T0SE OPTION_REG_bits.T0SE
701 #define T0CS OPTION_REG_bits.T0CS
702 #define INTEDG OPTION_REG_bits.INTEDG
703 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
705 // ----- OSCCON bits --------------------
711 unsigned char OSTS:1;
712 unsigned char IRCF0:1;
713 unsigned char IRCF1:1;
714 unsigned char IRCF2:1;
718 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
720 #define SCS OSCCON_bits.SCS
721 #define LTS OSCCON_bits.LTS
722 #define HTS OSCCON_bits.HTS
723 #define OSTS OSCCON_bits.OSTS
724 #define IRCF0 OSCCON_bits.IRCF0
725 #define IRCF1 OSCCON_bits.IRCF1
726 #define IRCF2 OSCCON_bits.IRCF2
728 // ----- OSCTUNE bits --------------------
731 unsigned char TUN0:1;
732 unsigned char TUN1:1;
733 unsigned char TUN2:1;
734 unsigned char TUN3:1;
735 unsigned char TUN4:1;
736 unsigned char WPUA5:1;
741 unsigned char WPUA0:1;
742 unsigned char WPUA1:1;
743 unsigned char WPUA2:1;
744 unsigned char IOC3:1;
745 unsigned char WPUA4:1;
746 unsigned char IOC5:1;
751 unsigned char IOC0:1;
752 unsigned char IOC1:1;
753 unsigned char IOC2:1;
754 unsigned char IOCA3:1;
755 unsigned char IOC4:1;
756 unsigned char IOCA5:1;
761 unsigned char IOCA0:1;
762 unsigned char IOCA1:1;
763 unsigned char IOCA2:1;
765 unsigned char IOCA4:1;
771 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
773 #define TUN0 OSCTUNE_bits.TUN0
774 #define WPUA0 OSCTUNE_bits.WPUA0
775 #define IOC0 OSCTUNE_bits.IOC0
776 #define IOCA0 OSCTUNE_bits.IOCA0
777 #define TUN1 OSCTUNE_bits.TUN1
778 #define WPUA1 OSCTUNE_bits.WPUA1
779 #define IOC1 OSCTUNE_bits.IOC1
780 #define IOCA1 OSCTUNE_bits.IOCA1
781 #define TUN2 OSCTUNE_bits.TUN2
782 #define WPUA2 OSCTUNE_bits.WPUA2
783 #define IOC2 OSCTUNE_bits.IOC2
784 #define IOCA2 OSCTUNE_bits.IOCA2
785 #define TUN3 OSCTUNE_bits.TUN3
786 #define IOC3 OSCTUNE_bits.IOC3
787 #define IOCA3 OSCTUNE_bits.IOCA3
788 #define TUN4 OSCTUNE_bits.TUN4
789 #define WPUA4 OSCTUNE_bits.WPUA4
790 #define IOC4 OSCTUNE_bits.IOC4
791 #define IOCA4 OSCTUNE_bits.IOCA4
792 #define WPUA5 OSCTUNE_bits.WPUA5
793 #define IOC5 OSCTUNE_bits.IOC5
794 #define IOCA5 OSCTUNE_bits.IOCA5
796 // ----- PCON bits --------------------
799 unsigned char NOT_BOD:1;
800 unsigned char NOT_POR:1;
803 unsigned char SBODEN:1;
804 unsigned char ULPWUE:1;
809 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
811 #define NOT_BOD PCON_bits.NOT_BOD
812 #define NOT_POR PCON_bits.NOT_POR
813 #define SBODEN PCON_bits.SBODEN
814 #define ULPWUE PCON_bits.ULPWUE
816 // ----- PIE1 bits --------------------
819 unsigned char T1IE:1;
820 unsigned char T2IE:1;
821 unsigned char CCPIE:1;
825 unsigned char ADIE:1;
829 unsigned char TMR1IE:1;
830 unsigned char TMR2IE:1;
839 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
841 #define T1IE PIE1_bits.T1IE
842 #define TMR1IE PIE1_bits.TMR1IE
843 #define T2IE PIE1_bits.T2IE
844 #define TMR2IE PIE1_bits.TMR2IE
845 #define CCPIE PIE1_bits.CCPIE
846 #define ADIE PIE1_bits.ADIE
848 // ----- PIE2 bits --------------------
855 unsigned char EEIE:1;
856 unsigned char C1IE:1;
857 unsigned char C2IE:1;
858 unsigned char OSFIE:1;
861 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
863 #define EEIE PIE2_bits.EEIE
864 #define C1IE PIE2_bits.C1IE
865 #define C2IE PIE2_bits.C2IE
866 #define OSFIE PIE2_bits.OSFIE
868 // ----- PIR1 bits --------------------
871 unsigned char T1IF:1;
872 unsigned char T2IF:1;
873 unsigned char CCP1IF:1;
877 unsigned char ADIF:1;
881 unsigned char TMR1IF:1;
882 unsigned char TMR2IF:1;
891 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
893 #define T1IF PIR1_bits.T1IF
894 #define TMR1IF PIR1_bits.TMR1IF
895 #define T2IF PIR1_bits.T2IF
896 #define TMR2IF PIR1_bits.TMR2IF
897 #define CCP1IF PIR1_bits.CCP1IF
898 #define ADIF PIR1_bits.ADIF
900 // ----- PIR2 bits --------------------
907 unsigned char EEIF:1;
908 unsigned char C1IF:1;
909 unsigned char C2IF:1;
910 unsigned char OSFIF:1;
913 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
915 #define EEIF PIR2_bits.EEIF
916 #define C1IF PIR2_bits.C1IF
917 #define C2IF PIR2_bits.C2IF
918 #define OSFIF PIR2_bits.OSFIF
920 // ----- PWM1CON bits --------------------
923 unsigned char PDC0:1;
924 unsigned char PDC1:1;
925 unsigned char PDC2:1;
926 unsigned char PDC3:1;
927 unsigned char PDC4:1;
928 unsigned char PDC5:1;
929 unsigned char PDC6:1;
930 unsigned char PRSEN:1;
933 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
935 #define PDC0 PWM1CON_bits.PDC0
936 #define PDC1 PWM1CON_bits.PDC1
937 #define PDC2 PWM1CON_bits.PDC2
938 #define PDC3 PWM1CON_bits.PDC3
939 #define PDC4 PWM1CON_bits.PDC4
940 #define PDC5 PWM1CON_bits.PDC5
941 #define PDC6 PWM1CON_bits.PDC6
942 #define PRSEN PWM1CON_bits.PRSEN
944 // ----- STATUS bits --------------------
950 unsigned char NOT_PD:1;
951 unsigned char NOT_TO:1;
957 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
959 #define C STATUS_bits.C
960 #define DC STATUS_bits.DC
961 #define Z STATUS_bits.Z
962 #define NOT_PD STATUS_bits.NOT_PD
963 #define NOT_TO STATUS_bits.NOT_TO
964 #define RP0 STATUS_bits.RP0
965 #define RP1 STATUS_bits.RP1
966 #define IRP STATUS_bits.IRP
968 // ----- T1CON bits --------------------
971 unsigned char TMR1ON:1;
972 unsigned char TMR1CS:1;
973 unsigned char NOT_T1SYNC:1;
974 unsigned char T1OSCEN:1;
975 unsigned char T1CKPS0:1;
976 unsigned char T1CKPS1:1;
977 unsigned char TMR1GE:1;
978 unsigned char T1GINV:1;
981 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
983 #define TMR1ON T1CON_bits.TMR1ON
984 #define TMR1CS T1CON_bits.TMR1CS
985 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
986 #define T1OSCEN T1CON_bits.T1OSCEN
987 #define T1CKPS0 T1CON_bits.T1CKPS0
988 #define T1CKPS1 T1CON_bits.T1CKPS1
989 #define TMR1GE T1CON_bits.TMR1GE
990 #define T1GINV T1CON_bits.T1GINV
992 // ----- T2CON bits --------------------
995 unsigned char T2CKPS0:1;
996 unsigned char T2CKPS1:1;
997 unsigned char TMR2ON:1;
998 unsigned char TOUTPS0:1;
999 unsigned char TOUTPS1:1;
1000 unsigned char TOUTPS2:1;
1001 unsigned char TOUTPS3:1;
1005 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1007 #define T2CKPS0 T2CON_bits.T2CKPS0
1008 #define T2CKPS1 T2CON_bits.T2CKPS1
1009 #define TMR2ON T2CON_bits.TMR2ON
1010 #define TOUTPS0 T2CON_bits.TOUTPS0
1011 #define TOUTPS1 T2CON_bits.TOUTPS1
1012 #define TOUTPS2 T2CON_bits.TOUTPS2
1013 #define TOUTPS3 T2CON_bits.TOUTPS3
1015 // ----- TRISA bits --------------------
1018 unsigned char TRISA0:1;
1019 unsigned char TRISA1:1;
1020 unsigned char TRISA2:1;
1021 unsigned char TRISA3:1;
1022 unsigned char TRISA4:1;
1023 unsigned char TRISA5:1;
1028 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1030 #define TRISA0 TRISA_bits.TRISA0
1031 #define TRISA1 TRISA_bits.TRISA1
1032 #define TRISA2 TRISA_bits.TRISA2
1033 #define TRISA3 TRISA_bits.TRISA3
1034 #define TRISA4 TRISA_bits.TRISA4
1035 #define TRISA5 TRISA_bits.TRISA5
1037 // ----- TRISB bits --------------------
1044 unsigned char TRISB4:1;
1045 unsigned char TRISB5:1;
1046 unsigned char TRISB6:1;
1047 unsigned char TRISB7:1;
1050 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1052 #define TRISB4 TRISB_bits.TRISB4
1053 #define TRISB5 TRISB_bits.TRISB5
1054 #define TRISB6 TRISB_bits.TRISB6
1055 #define TRISB7 TRISB_bits.TRISB7
1057 // ----- TRISC bits --------------------
1060 unsigned char TRISC0:1;
1061 unsigned char TRISC1:1;
1062 unsigned char TRISC2:1;
1063 unsigned char TRISC3:1;
1064 unsigned char TRISC4:1;
1065 unsigned char TRISC5:1;
1066 unsigned char TRISC6:1;
1067 unsigned char TRISC7:1;
1070 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1072 #define TRISC0 TRISC_bits.TRISC0
1073 #define TRISC1 TRISC_bits.TRISC1
1074 #define TRISC2 TRISC_bits.TRISC2
1075 #define TRISC3 TRISC_bits.TRISC3
1076 #define TRISC4 TRISC_bits.TRISC4
1077 #define TRISC5 TRISC_bits.TRISC5
1078 #define TRISC6 TRISC_bits.TRISC6
1079 #define TRISC7 TRISC_bits.TRISC7
1081 // ----- VRCON bits --------------------
1084 unsigned char VR0:1;
1085 unsigned char VR1:1;
1086 unsigned char VR2:1;
1087 unsigned char VR3:1;
1088 unsigned char VP6EN:1;
1089 unsigned char VRR:1;
1090 unsigned char C2VREN:1;
1091 unsigned char C1VREN:1;
1094 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1096 #define VR0 VRCON_bits.VR0
1097 #define VR1 VRCON_bits.VR1
1098 #define VR2 VRCON_bits.VR2
1099 #define VR3 VRCON_bits.VR3
1100 #define VP6EN VRCON_bits.VP6EN
1101 #define VRR VRCON_bits.VRR
1102 #define C2VREN VRCON_bits.C2VREN
1103 #define C1VREN VRCON_bits.C1VREN
1105 // ----- WDTCON bits --------------------
1108 unsigned char SWDTEN:1;
1109 unsigned char WDTPS0:1;
1110 unsigned char WDTPS1:1;
1111 unsigned char WDTPS2:1;
1112 unsigned char WDTPS3:1;
1113 unsigned char ADCS1:1;
1114 unsigned char ADCS2:1;
1122 unsigned char ADCS0:1;
1128 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1130 #define SWDTEN WDTCON_bits.SWDTEN
1131 #define WDTPS0 WDTCON_bits.WDTPS0
1132 #define WDTPS1 WDTCON_bits.WDTPS1
1133 #define WDTPS2 WDTCON_bits.WDTPS2
1134 #define WDTPS3 WDTCON_bits.WDTPS3
1135 #define ADCS0 WDTCON_bits.ADCS0
1136 #define ADCS1 WDTCON_bits.ADCS1
1137 #define ADCS2 WDTCON_bits.ADCS2
1139 // ----- WPUB bits --------------------
1146 unsigned char WPUB4:1;
1147 unsigned char WPUB5:1;
1148 unsigned char WPUB6:1;
1149 unsigned char WPUB7:1;
1156 unsigned char IOCB4:1;
1157 unsigned char IOCB5:1;
1158 unsigned char IOCB6:1;
1159 unsigned char IOCB7:1;
1162 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1164 #define WPUB4 WPUB_bits.WPUB4
1165 #define IOCB4 WPUB_bits.IOCB4
1166 #define WPUB5 WPUB_bits.WPUB5
1167 #define IOCB5 WPUB_bits.IOCB5
1168 #define WPUB6 WPUB_bits.WPUB6
1169 #define IOCB6 WPUB_bits.IOCB6
1170 #define WPUB7 WPUB_bits.WPUB7
1171 #define IOCB7 WPUB_bits.IOCB7