2 // Register Declarations for Microchip 16F685 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define CCPR1L_ADDR 0x0015
46 #define CCPR1H_ADDR 0x0016
47 #define CCP1CON_ADDR 0x0017
48 #define PWM1CON_ADDR 0x001C
49 #define ECCPAS_ADDR 0x001D
50 #define ADRESH_ADDR 0x001E
51 #define ADCON0_ADDR 0x001F
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PIE2_ADDR 0x008D
58 #define PCON_ADDR 0x008E
59 #define OSCCON_ADDR 0x008F
60 #define OSCTUNE_ADDR 0x0090
61 #define PR2_ADDR 0x0092
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define WDTCON_ADDR 0x0097
67 #define ADRESL_ADDR 0x009E
68 #define ADCON1_ADDR 0x009F
69 #define EEDAT_ADDR 0x010C
70 #define EEDATA_ADDR 0x010C
71 #define EEADR_ADDR 0x010D
72 #define EEDATH_ADDR 0x010E
73 #define EEADRH_ADDR 0x010F
74 #define WPUB_ADDR 0x0115
75 #define IOCB_ADDR 0x0116
76 #define VRCON_ADDR 0x0118
77 #define CM1CON0_ADDR 0x0119
78 #define CM2CON0_ADDR 0x011A
79 #define CM2CON1_ADDR 0x011B
80 #define ANSEL_ADDR 0x011E
81 #define ANSELH_ADDR 0x011F
82 #define EECON1_ADDR 0x018C
83 #define EECON2_ADDR 0x018D
84 #define PSTRCON_ADDR 0x019D
85 #define SRCON_ADDR 0x019E
88 // Memory organization.
94 // P16F685.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
97 // This header file defines configurations, registers, and other useful bits of
98 // information for the PIC16F685 microcontroller. These names are taken to match
99 // the data sheets as closely as possible.
101 // Note that the processor must be selected before this file is
102 // included. The processor may be selected the following ways:
104 // 1. Command line switch:
105 // C:\ MPASM MYFILE.ASM /PIC16F685
106 // 2. LIST directive in the source file
108 // 3. Processor Type entry in the MPASM full-screen interface
110 //==========================================================================
114 //==========================================================================
115 //1.00 10/12/04 Original
116 //2.00 04/21/05 Modified file to match released datasheet
117 //==========================================================================
121 //==========================================================================
124 // MESSG "Processor-header file mismatch. Verify selected processor."
127 //==========================================================================
129 // Register Definitions
131 //==========================================================================
136 //----- Register Files------------------------------------------------------
138 extern __sfr __at (INDF_ADDR) INDF;
139 extern __sfr __at (TMR0_ADDR) TMR0;
140 extern __sfr __at (PCL_ADDR) PCL;
141 extern __sfr __at (STATUS_ADDR) STATUS;
142 extern __sfr __at (FSR_ADDR) FSR;
143 extern __sfr __at (PORTA_ADDR) PORTA;
144 extern __sfr __at (PORTB_ADDR) PORTB;
145 extern __sfr __at (PORTC_ADDR) PORTC;
147 extern __sfr __at (PCLATH_ADDR) PCLATH;
148 extern __sfr __at (INTCON_ADDR) INTCON;
149 extern __sfr __at (PIR1_ADDR) PIR1;
150 extern __sfr __at (PIR2_ADDR) PIR2;
151 extern __sfr __at (TMR1L_ADDR) TMR1L;
152 extern __sfr __at (TMR1H_ADDR) TMR1H;
153 extern __sfr __at (T1CON_ADDR) T1CON;
154 extern __sfr __at (TMR2_ADDR) TMR2;
155 extern __sfr __at (T2CON_ADDR) T2CON;
158 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
159 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
160 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
163 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
164 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
165 extern __sfr __at (ADRESH_ADDR) ADRESH;
166 extern __sfr __at (ADCON0_ADDR) ADCON0;
169 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
171 extern __sfr __at (TRISA_ADDR) TRISA;
172 extern __sfr __at (TRISB_ADDR) TRISB;
173 extern __sfr __at (TRISC_ADDR) TRISC;
175 extern __sfr __at (PIE1_ADDR) PIE1;
176 extern __sfr __at (PIE2_ADDR) PIE2;
177 extern __sfr __at (PCON_ADDR) PCON;
178 extern __sfr __at (OSCCON_ADDR) OSCCON;
179 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
181 extern __sfr __at (PR2_ADDR) PR2;
184 extern __sfr __at (WPU_ADDR) WPU;
185 extern __sfr __at (WPUA_ADDR) WPUA;
186 extern __sfr __at (IOC_ADDR) IOC;
187 extern __sfr __at (IOCA_ADDR) IOCA;
188 extern __sfr __at (WDTCON_ADDR) WDTCON;
192 extern __sfr __at (ADRESL_ADDR) ADRESL;
193 extern __sfr __at (ADCON1_ADDR) ADCON1;
196 extern __sfr __at (EEDAT_ADDR) EEDAT;
197 extern __sfr __at (EEDATA_ADDR) EEDATA;
198 extern __sfr __at (EEADR_ADDR) EEADR;
199 extern __sfr __at (EEDATH_ADDR) EEDATH;
200 extern __sfr __at (EEADRH_ADDR) EEADRH;
203 extern __sfr __at (WPUB_ADDR) WPUB;
204 extern __sfr __at (IOCB_ADDR) IOCB;
206 extern __sfr __at (VRCON_ADDR) VRCON;
207 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
208 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
209 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
211 extern __sfr __at (ANSEL_ADDR) ANSEL;
212 extern __sfr __at (ANSELH_ADDR) ANSELH;
214 extern __sfr __at (EECON1_ADDR) EECON1;
215 extern __sfr __at (EECON2_ADDR) EECON2;
218 extern __sfr __at (PSTRCON_ADDR) PSTRCON;
219 extern __sfr __at (SRCON_ADDR) SRCON;
223 //----- BANK 0 REGISTER DEFINITIONS ----------------------------------------
224 //----- STATUS Bits --------------------------------------------------------
227 //----- INTCON Bits --------------------------------------------------------
230 //----- PIR1 Bits ----------------------------------------------------------
235 //----- PIR2 Bits ----------------------------------------------------------
238 //----- T1CON Bits ---------------------------------------------------------
241 //----- T2CON Bits ---------------------------------------------------------
245 //----- CCP1CON Bits -------------------------------------------------------
248 //----- PWM1CON Bits -------------------------------------------------------
251 //----- ECCPAS Bits --------------------------------------------------------
254 //----- ADCON0 Bits --------------------------------------------------------
257 //----- BANK 1 REGISTER DEFINITIONS ----------------------------------------
258 //----- OPTION Bits --------------------------------------------------------
261 //----- TRISA Bits --------------------------------------------------------
264 //----- TRISB Bits --------------------------------------------------------
267 //----- TRISC Bits --------------------------------------------------------
270 //----- PIE1 Bits ----------------------------------------------------------
275 //----- PIE2 Bits ----------------------------------------------------------
278 //----- PCON Bits ----------------------------------------------------------
281 //----- OSCCON Bits --------------------------------------------------------
284 //----- OSCTUNE Bits -------------------------------------------------------
287 //----- WPUA --------------------------------------------------------------
291 //----- IOC --------------------------------------------------------------
294 //----- IOCA --------------------------------------------------------------
297 //----- WDTCON Bits --------------------------------------------------------
300 //----- ADCON1 -------------------------------------------------------------
303 //----- BANK 2 REGISTER DEFINITIONS ----------------------------------------
304 //----- WPUB Bits ----------------------------------------------------------
307 //----- IOCB --------------------------------------------------------------
310 //----- VRCON Bits ---------------------------------------------------------
313 //----- CM1CON0 Bits -------------------------------------------------------
317 //----- CM2CON0 Bits -------------------------------------------------------
321 //----- CM2CON1 Bits -------------------------------------------------------
324 //----- ANSELH --------------------------------------------------------------
327 //----- ANSEL --------------------------------------------------------------
330 //----- BANK 3 REGISTER DEFINITIONS ----------------------------------------
331 //----- EECON1 -------------------------------------------------------------
334 //----- PSTRCON -------------------------------------------------------------
337 //----- SRCON ---------------------------------------------------------------
340 //==========================================================================
344 //==========================================================================
347 // __BADRAM H'08'-H'09', H'13'-H'14', H'18'-H'1B'
348 // __BADRAM H'88'-H'89', H'91', H'93'-H'94', H'98'-H'9D'
349 // __BADRAM H'108'-H'109', H'110'-H'114', H'117', H'11C'-H'11D'
350 // __BADRAM H'188'-H'189', H'18E'-H'19C', H'19F'-H'1EF'
352 //==========================================================================
354 // Configuration Bits
356 //==========================================================================
358 #define _FCMEN_ON 0x3FFF
359 #define _FCMEN_OFF 0x37FF
360 #define _IESO_ON 0x3FFF
361 #define _IESO_OFF 0x3BFF
362 #define _BOR_ON 0x3FFF
363 #define _BOR_NSLEEP 0x3EFF
364 #define _BOR_SBODEN 0x3DFF
365 #define _BOR_OFF 0x3CFF
366 #define _CPD_ON 0x3F7F
367 #define _CPD_OFF 0x3FFF
368 #define _CP_ON 0x3FBF
369 #define _CP_OFF 0x3FFF
370 #define _MCLRE_ON 0x3FFF
371 #define _MCLRE_OFF 0x3FDF
372 #define _PWRTE_OFF 0x3FFF
373 #define _PWRTE_ON 0x3FEF
374 #define _WDT_ON 0x3FFF
375 #define _WDT_OFF 0x3FF7
376 #define _LP_OSC 0x3FF8
377 #define _XT_OSC 0x3FF9
378 #define _HS_OSC 0x3FFA
379 #define _EC_OSC 0x3FFB
380 #define _INTRC_OSC_NOCLKOUT 0x3FFC
381 #define _INTRC_OSC_CLKOUT 0x3FFD
382 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
383 #define _EXTRC_OSC_CLKOUT 0x3FFF
384 #define _INTOSCIO 0x3FFC
385 #define _INTOSC 0x3FFD
386 #define _EXTRCIO 0x3FFE
387 #define _EXTRC 0x3FFF
391 // ----- ADCON0 bits --------------------
394 unsigned char ADON:1;
396 unsigned char CHS0:1;
397 unsigned char CHS1:1;
398 unsigned char CHS2:1;
399 unsigned char CHS3:1;
400 unsigned char VCFG:1;
401 unsigned char ADFM:1;
405 unsigned char NOT_DONE:1;
415 unsigned char GO_DONE:1;
424 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
426 #ifndef NO_BIT_DEFINES
427 #define ADON ADCON0_bits.ADON
428 #define GO ADCON0_bits.GO
429 #define NOT_DONE ADCON0_bits.NOT_DONE
430 #define GO_DONE ADCON0_bits.GO_DONE
431 #define CHS0 ADCON0_bits.CHS0
432 #define CHS1 ADCON0_bits.CHS1
433 #define CHS2 ADCON0_bits.CHS2
434 #define CHS3 ADCON0_bits.CHS3
435 #define VCFG ADCON0_bits.VCFG
436 #define ADFM ADCON0_bits.ADFM
437 #endif /* NO_BIT_DEFINES */
439 // ----- ADCON1 bits --------------------
446 unsigned char ADCS0:1;
447 unsigned char ADCS1:1;
448 unsigned char ADCS2:1;
452 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
454 #ifndef NO_BIT_DEFINES
455 #define ADCS0 ADCON1_bits.ADCS0
456 #define ADCS1 ADCON1_bits.ADCS1
457 #define ADCS2 ADCON1_bits.ADCS2
458 #endif /* NO_BIT_DEFINES */
460 // ----- ANSEL bits --------------------
463 unsigned char ANS0:1;
464 unsigned char ANS1:1;
465 unsigned char ANS2:1;
466 unsigned char ANS3:1;
467 unsigned char ANS4:1;
468 unsigned char ANS5:1;
469 unsigned char ANS6:1;
470 unsigned char ANS7:1;
473 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
475 #ifndef NO_BIT_DEFINES
476 #define ANS0 ANSEL_bits.ANS0
477 #define ANS1 ANSEL_bits.ANS1
478 #define ANS2 ANSEL_bits.ANS2
479 #define ANS3 ANSEL_bits.ANS3
480 #define ANS4 ANSEL_bits.ANS4
481 #define ANS5 ANSEL_bits.ANS5
482 #define ANS6 ANSEL_bits.ANS6
483 #define ANS7 ANSEL_bits.ANS7
484 #endif /* NO_BIT_DEFINES */
486 // ----- ANSELH bits --------------------
489 unsigned char ANS8:1;
490 unsigned char ANS9:1;
491 unsigned char ANS10:1;
492 unsigned char ANS11:1;
499 extern volatile __ANSELH_bits_t __at(ANSELH_ADDR) ANSELH_bits;
501 #ifndef NO_BIT_DEFINES
502 #define ANS8 ANSELH_bits.ANS8
503 #define ANS9 ANSELH_bits.ANS9
504 #define ANS10 ANSELH_bits.ANS10
505 #define ANS11 ANSELH_bits.ANS11
506 #endif /* NO_BIT_DEFINES */
508 // ----- CCP1CON bits --------------------
511 unsigned char CCP1M0:1;
512 unsigned char CCP1M1:1;
513 unsigned char CCP1M2:1;
514 unsigned char CCP1M3:1;
515 unsigned char DC1B0:1;
516 unsigned char DC1B1:1;
517 unsigned char P1M0:1;
518 unsigned char P1M1:1;
521 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
523 #ifndef NO_BIT_DEFINES
524 #define CCP1M0 CCP1CON_bits.CCP1M0
525 #define CCP1M1 CCP1CON_bits.CCP1M1
526 #define CCP1M2 CCP1CON_bits.CCP1M2
527 #define CCP1M3 CCP1CON_bits.CCP1M3
528 #define DC1B0 CCP1CON_bits.DC1B0
529 #define DC1B1 CCP1CON_bits.DC1B1
530 #define P1M0 CCP1CON_bits.P1M0
531 #define P1M1 CCP1CON_bits.P1M1
532 #endif /* NO_BIT_DEFINES */
534 // ----- CM1CON0 bits --------------------
537 unsigned char C1CH0:1;
538 unsigned char C1CH1:1;
541 unsigned char C1POL:1;
542 unsigned char C1OE:1;
543 unsigned char C1OUT:1;
544 unsigned char C1ON:1;
547 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
549 #ifndef NO_BIT_DEFINES
550 #define C1CH0 CM1CON0_bits.C1CH0
551 #define C1CH1 CM1CON0_bits.C1CH1
552 #define C1R CM1CON0_bits.C1R
553 #define C1POL CM1CON0_bits.C1POL
554 #define C1OE CM1CON0_bits.C1OE
555 #define C1OUT CM1CON0_bits.C1OUT
556 #define C1ON CM1CON0_bits.C1ON
557 #endif /* NO_BIT_DEFINES */
559 // ----- CM2CON0 bits --------------------
562 unsigned char C2CH0:1;
563 unsigned char C2CH1:1;
566 unsigned char C2POL:1;
567 unsigned char C2OE:1;
568 unsigned char C2OUT:1;
569 unsigned char C2ON:1;
572 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
574 #ifndef NO_BIT_DEFINES
575 #define C2CH0 CM2CON0_bits.C2CH0
576 #define C2CH1 CM2CON0_bits.C2CH1
577 #define C2R CM2CON0_bits.C2R
578 #define C2POL CM2CON0_bits.C2POL
579 #define C2OE CM2CON0_bits.C2OE
580 #define C2OUT CM2CON0_bits.C2OUT
581 #define C2ON CM2CON0_bits.C2ON
582 #endif /* NO_BIT_DEFINES */
584 // ----- CM2CON1 bits --------------------
587 unsigned char C2SYNC:1;
588 unsigned char T1GSS:1;
593 unsigned char MC2OUT:1;
594 unsigned char MC1OUT:1;
597 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
599 #ifndef NO_BIT_DEFINES
600 #define C2SYNC CM2CON1_bits.C2SYNC
601 #define T1GSS CM2CON1_bits.T1GSS
602 #define MC2OUT CM2CON1_bits.MC2OUT
603 #define MC1OUT CM2CON1_bits.MC1OUT
604 #endif /* NO_BIT_DEFINES */
606 // ----- ECCPAS bits --------------------
609 unsigned char PSSBD0:1;
610 unsigned char PSSBD1:1;
611 unsigned char PSSAC0:1;
612 unsigned char PSSAC1:1;
613 unsigned char ECCPAS0:1;
614 unsigned char ECCPAS1:1;
615 unsigned char ECCPAS2:1;
616 unsigned char ECCPASE:1;
619 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
621 #ifndef NO_BIT_DEFINES
622 #define PSSBD0 ECCPAS_bits.PSSBD0
623 #define PSSBD1 ECCPAS_bits.PSSBD1
624 #define PSSAC0 ECCPAS_bits.PSSAC0
625 #define PSSAC1 ECCPAS_bits.PSSAC1
626 #define ECCPAS0 ECCPAS_bits.ECCPAS0
627 #define ECCPAS1 ECCPAS_bits.ECCPAS1
628 #define ECCPAS2 ECCPAS_bits.ECCPAS2
629 #define ECCPASE ECCPAS_bits.ECCPASE
630 #endif /* NO_BIT_DEFINES */
632 // ----- EECON1 bits --------------------
637 unsigned char WREN:1;
638 unsigned char WRERR:1;
642 unsigned char EEPGD:1;
645 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
647 #ifndef NO_BIT_DEFINES
648 #define RD EECON1_bits.RD
649 #define WR EECON1_bits.WR
650 #define WREN EECON1_bits.WREN
651 #define WRERR EECON1_bits.WRERR
652 #define EEPGD EECON1_bits.EEPGD
653 #endif /* NO_BIT_DEFINES */
655 // ----- INTCON bits --------------------
658 unsigned char RABIF:1;
659 unsigned char INTF:1;
660 unsigned char T0IF:1;
661 unsigned char RABIE:1;
662 unsigned char INTE:1;
663 unsigned char T0IE:1;
664 unsigned char PEIE:1;
668 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
670 #ifndef NO_BIT_DEFINES
671 #define RABIF INTCON_bits.RABIF
672 #define INTF INTCON_bits.INTF
673 #define T0IF INTCON_bits.T0IF
674 #define RABIE INTCON_bits.RABIE
675 #define INTE INTCON_bits.INTE
676 #define T0IE INTCON_bits.T0IE
677 #define PEIE INTCON_bits.PEIE
678 #define GIE INTCON_bits.GIE
679 #endif /* NO_BIT_DEFINES */
681 // ----- IOC bits --------------------
684 unsigned char IOC0:1;
685 unsigned char IOC1:1;
686 unsigned char IOC2:1;
687 unsigned char IOC3:1;
688 unsigned char IOC4:1;
689 unsigned char IOC5:1;
694 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
696 #ifndef NO_BIT_DEFINES
697 #define IOC0 IOC_bits.IOC0
698 #define IOC1 IOC_bits.IOC1
699 #define IOC2 IOC_bits.IOC2
700 #define IOC3 IOC_bits.IOC3
701 #define IOC4 IOC_bits.IOC4
702 #define IOC5 IOC_bits.IOC5
703 #endif /* NO_BIT_DEFINES */
705 // ----- IOCA bits --------------------
708 unsigned char IOCA0:1;
709 unsigned char IOCA1:1;
710 unsigned char IOCA2:1;
711 unsigned char IOCA3:1;
712 unsigned char IOCA4:1;
713 unsigned char IOCA5:1;
718 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
720 #ifndef NO_BIT_DEFINES
721 #define IOCA0 IOCA_bits.IOCA0
722 #define IOCA1 IOCA_bits.IOCA1
723 #define IOCA2 IOCA_bits.IOCA2
724 #define IOCA3 IOCA_bits.IOCA3
725 #define IOCA4 IOCA_bits.IOCA4
726 #define IOCA5 IOCA_bits.IOCA5
727 #endif /* NO_BIT_DEFINES */
729 // ----- IOCB bits --------------------
736 unsigned char IOCB4:1;
737 unsigned char IOCB5:1;
738 unsigned char IOCB6:1;
739 unsigned char IOCB7:1;
742 extern volatile __IOCB_bits_t __at(IOCB_ADDR) IOCB_bits;
744 #ifndef NO_BIT_DEFINES
745 #define IOCB4 IOCB_bits.IOCB4
746 #define IOCB5 IOCB_bits.IOCB5
747 #define IOCB6 IOCB_bits.IOCB6
748 #define IOCB7 IOCB_bits.IOCB7
749 #endif /* NO_BIT_DEFINES */
751 // ----- OPTION_REG bits --------------------
758 unsigned char T0SE:1;
759 unsigned char T0CS:1;
760 unsigned char INTEDG:1;
761 unsigned char NOT_RABPU:1;
763 } __OPTION_REG_bits_t;
764 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
766 #ifndef NO_BIT_DEFINES
767 #define PS0 OPTION_REG_bits.PS0
768 #define PS1 OPTION_REG_bits.PS1
769 #define PS2 OPTION_REG_bits.PS2
770 #define PSA OPTION_REG_bits.PSA
771 #define T0SE OPTION_REG_bits.T0SE
772 #define T0CS OPTION_REG_bits.T0CS
773 #define INTEDG OPTION_REG_bits.INTEDG
774 #define NOT_RABPU OPTION_REG_bits.NOT_RABPU
775 #endif /* NO_BIT_DEFINES */
777 // ----- OSCCON bits --------------------
783 unsigned char OSTS:1;
784 unsigned char IRCF0:1;
785 unsigned char IRCF1:1;
786 unsigned char IRCF2:1;
790 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
792 #ifndef NO_BIT_DEFINES
793 #define SCS OSCCON_bits.SCS
794 #define LTS OSCCON_bits.LTS
795 #define HTS OSCCON_bits.HTS
796 #define OSTS OSCCON_bits.OSTS
797 #define IRCF0 OSCCON_bits.IRCF0
798 #define IRCF1 OSCCON_bits.IRCF1
799 #define IRCF2 OSCCON_bits.IRCF2
800 #endif /* NO_BIT_DEFINES */
802 // ----- OSCTUNE bits --------------------
805 unsigned char TUN0:1;
806 unsigned char TUN1:1;
807 unsigned char TUN2:1;
808 unsigned char TUN3:1;
809 unsigned char TUN4:1;
815 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
817 #ifndef NO_BIT_DEFINES
818 #define TUN0 OSCTUNE_bits.TUN0
819 #define TUN1 OSCTUNE_bits.TUN1
820 #define TUN2 OSCTUNE_bits.TUN2
821 #define TUN3 OSCTUNE_bits.TUN3
822 #define TUN4 OSCTUNE_bits.TUN4
823 #endif /* NO_BIT_DEFINES */
825 // ----- PCON bits --------------------
828 unsigned char NOT_BOD:1;
829 unsigned char NOT_POR:1;
832 unsigned char SBOREN:1;
833 unsigned char ULPWUE:1;
838 unsigned char NOT_BOR:1;
848 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
850 #ifndef NO_BIT_DEFINES
851 #define NOT_BOD PCON_bits.NOT_BOD
852 #define NOT_BOR PCON_bits.NOT_BOR
853 #define NOT_POR PCON_bits.NOT_POR
854 #define SBOREN PCON_bits.SBOREN
855 #define ULPWUE PCON_bits.ULPWUE
856 #endif /* NO_BIT_DEFINES */
858 // ----- PIE1 bits --------------------
861 unsigned char T1IE:1;
862 unsigned char T2IE:1;
863 unsigned char CCP1IE:1;
867 unsigned char ADIE:1;
871 unsigned char TMR1IE:1;
872 unsigned char TMR2IE:1;
881 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
883 #ifndef NO_BIT_DEFINES
884 #define T1IE PIE1_bits.T1IE
885 #define TMR1IE PIE1_bits.TMR1IE
886 #define T2IE PIE1_bits.T2IE
887 #define TMR2IE PIE1_bits.TMR2IE
888 #define CCP1IE PIE1_bits.CCP1IE
889 #define ADIE PIE1_bits.ADIE
890 #endif /* NO_BIT_DEFINES */
892 // ----- PIE2 bits --------------------
899 unsigned char EEIE:1;
900 unsigned char C1IE:1;
901 unsigned char C2IE:1;
902 unsigned char OSFIE:1;
905 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
907 #ifndef NO_BIT_DEFINES
908 #define EEIE PIE2_bits.EEIE
909 #define C1IE PIE2_bits.C1IE
910 #define C2IE PIE2_bits.C2IE
911 #define OSFIE PIE2_bits.OSFIE
912 #endif /* NO_BIT_DEFINES */
914 // ----- PIR1 bits --------------------
917 unsigned char T1IF:1;
918 unsigned char T2IF:1;
919 unsigned char CCP1IF:1;
923 unsigned char ADIF:1;
927 unsigned char TMR1IF:1;
928 unsigned char TMR2IF:1;
937 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
939 #ifndef NO_BIT_DEFINES
940 #define T1IF PIR1_bits.T1IF
941 #define TMR1IF PIR1_bits.TMR1IF
942 #define T2IF PIR1_bits.T2IF
943 #define TMR2IF PIR1_bits.TMR2IF
944 #define CCP1IF PIR1_bits.CCP1IF
945 #define ADIF PIR1_bits.ADIF
946 #endif /* NO_BIT_DEFINES */
948 // ----- PIR2 bits --------------------
955 unsigned char EEIF:1;
956 unsigned char C1IF:1;
957 unsigned char C2IF:1;
958 unsigned char OSFIF:1;
961 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
963 #ifndef NO_BIT_DEFINES
964 #define EEIF PIR2_bits.EEIF
965 #define C1IF PIR2_bits.C1IF
966 #define C2IF PIR2_bits.C2IF
967 #define OSFIF PIR2_bits.OSFIF
968 #endif /* NO_BIT_DEFINES */
970 // ----- PORTA bits --------------------
983 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
985 #ifndef NO_BIT_DEFINES
986 #define RA0 PORTA_bits.RA0
987 #define RA1 PORTA_bits.RA1
988 #define RA2 PORTA_bits.RA2
989 #define RA3 PORTA_bits.RA3
990 #define RA4 PORTA_bits.RA4
991 #define RA5 PORTA_bits.RA5
992 #endif /* NO_BIT_DEFINES */
994 // ----- PORTB bits --------------------
1000 unsigned char RB3:1;
1001 unsigned char RB4:1;
1002 unsigned char RB5:1;
1003 unsigned char RB6:1;
1004 unsigned char RB7:1;
1007 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
1009 #ifndef NO_BIT_DEFINES
1010 #define RB0 PORTB_bits.RB0
1011 #define RB1 PORTB_bits.RB1
1012 #define RB2 PORTB_bits.RB2
1013 #define RB3 PORTB_bits.RB3
1014 #define RB4 PORTB_bits.RB4
1015 #define RB5 PORTB_bits.RB5
1016 #define RB6 PORTB_bits.RB6
1017 #define RB7 PORTB_bits.RB7
1018 #endif /* NO_BIT_DEFINES */
1020 // ----- PORTC bits --------------------
1023 unsigned char RC0:1;
1024 unsigned char RC1:1;
1025 unsigned char RC2:1;
1026 unsigned char RC3:1;
1027 unsigned char RC4:1;
1028 unsigned char RC5:1;
1029 unsigned char RC6:1;
1030 unsigned char RC7:1;
1033 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
1035 #ifndef NO_BIT_DEFINES
1036 #define RC0 PORTC_bits.RC0
1037 #define RC1 PORTC_bits.RC1
1038 #define RC2 PORTC_bits.RC2
1039 #define RC3 PORTC_bits.RC3
1040 #define RC4 PORTC_bits.RC4
1041 #define RC5 PORTC_bits.RC5
1042 #define RC6 PORTC_bits.RC6
1043 #define RC7 PORTC_bits.RC7
1044 #endif /* NO_BIT_DEFINES */
1046 // ----- PSTRCON bits --------------------
1049 unsigned char STRA:1;
1050 unsigned char STRB:1;
1051 unsigned char STRC:1;
1052 unsigned char STRD:1;
1053 unsigned char STRSYNC:1;
1059 extern volatile __PSTRCON_bits_t __at(PSTRCON_ADDR) PSTRCON_bits;
1061 #ifndef NO_BIT_DEFINES
1062 #define STRA PSTRCON_bits.STRA
1063 #define STRB PSTRCON_bits.STRB
1064 #define STRC PSTRCON_bits.STRC
1065 #define STRD PSTRCON_bits.STRD
1066 #define STRSYNC PSTRCON_bits.STRSYNC
1067 #endif /* NO_BIT_DEFINES */
1069 // ----- PWM1CON bits --------------------
1072 unsigned char PDC0:1;
1073 unsigned char PDC1:1;
1074 unsigned char PDC2:1;
1075 unsigned char PDC3:1;
1076 unsigned char PDC4:1;
1077 unsigned char PDC5:1;
1078 unsigned char PDC6:1;
1079 unsigned char PRSEN:1;
1082 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
1084 #ifndef NO_BIT_DEFINES
1085 #define PDC0 PWM1CON_bits.PDC0
1086 #define PDC1 PWM1CON_bits.PDC1
1087 #define PDC2 PWM1CON_bits.PDC2
1088 #define PDC3 PWM1CON_bits.PDC3
1089 #define PDC4 PWM1CON_bits.PDC4
1090 #define PDC5 PWM1CON_bits.PDC5
1091 #define PDC6 PWM1CON_bits.PDC6
1092 #define PRSEN PWM1CON_bits.PRSEN
1093 #endif /* NO_BIT_DEFINES */
1095 // ----- SRCON bits --------------------
1100 unsigned char PULSR:1;
1101 unsigned char PULSS:1;
1102 unsigned char C2REN:1;
1103 unsigned char C1SEN:1;
1104 unsigned char SR0:1;
1105 unsigned char SR1:1;
1108 extern volatile __SRCON_bits_t __at(SRCON_ADDR) SRCON_bits;
1110 #ifndef NO_BIT_DEFINES
1111 #define PULSR SRCON_bits.PULSR
1112 #define PULSS SRCON_bits.PULSS
1113 #define C2REN SRCON_bits.C2REN
1114 #define C1SEN SRCON_bits.C1SEN
1115 #define SR0 SRCON_bits.SR0
1116 #define SR1 SRCON_bits.SR1
1117 #endif /* NO_BIT_DEFINES */
1119 // ----- STATUS bits --------------------
1125 unsigned char NOT_PD:1;
1126 unsigned char NOT_TO:1;
1127 unsigned char RP0:1;
1128 unsigned char RP1:1;
1129 unsigned char IRP:1;
1132 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
1134 #ifndef NO_BIT_DEFINES
1135 #define C STATUS_bits.C
1136 #define DC STATUS_bits.DC
1137 #define Z STATUS_bits.Z
1138 #define NOT_PD STATUS_bits.NOT_PD
1139 #define NOT_TO STATUS_bits.NOT_TO
1140 #define RP0 STATUS_bits.RP0
1141 #define RP1 STATUS_bits.RP1
1142 #define IRP STATUS_bits.IRP
1143 #endif /* NO_BIT_DEFINES */
1145 // ----- T1CON bits --------------------
1148 unsigned char TMR1ON:1;
1149 unsigned char TMR1CS:1;
1150 unsigned char NOT_T1SYNC:1;
1151 unsigned char T1OSCEN:1;
1152 unsigned char T1CKPS0:1;
1153 unsigned char T1CKPS1:1;
1154 unsigned char TMR1GE:1;
1155 unsigned char T1GINV:1;
1158 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
1160 #ifndef NO_BIT_DEFINES
1161 #define TMR1ON T1CON_bits.TMR1ON
1162 #define TMR1CS T1CON_bits.TMR1CS
1163 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
1164 #define T1OSCEN T1CON_bits.T1OSCEN
1165 #define T1CKPS0 T1CON_bits.T1CKPS0
1166 #define T1CKPS1 T1CON_bits.T1CKPS1
1167 #define TMR1GE T1CON_bits.TMR1GE
1168 #define T1GINV T1CON_bits.T1GINV
1169 #endif /* NO_BIT_DEFINES */
1171 // ----- T2CON bits --------------------
1174 unsigned char T2CKPS0:1;
1175 unsigned char T2CKPS1:1;
1176 unsigned char TMR2ON:1;
1177 unsigned char TOUTPS0:1;
1178 unsigned char TOUTPS1:1;
1179 unsigned char TOUTPS2:1;
1180 unsigned char TOUTPS3:1;
1184 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
1186 #ifndef NO_BIT_DEFINES
1187 #define T2CKPS0 T2CON_bits.T2CKPS0
1188 #define T2CKPS1 T2CON_bits.T2CKPS1
1189 #define TMR2ON T2CON_bits.TMR2ON
1190 #define TOUTPS0 T2CON_bits.TOUTPS0
1191 #define TOUTPS1 T2CON_bits.TOUTPS1
1192 #define TOUTPS2 T2CON_bits.TOUTPS2
1193 #define TOUTPS3 T2CON_bits.TOUTPS3
1194 #endif /* NO_BIT_DEFINES */
1196 // ----- TRISA bits --------------------
1199 unsigned char TRISA0:1;
1200 unsigned char TRISA1:1;
1201 unsigned char TRISA2:1;
1202 unsigned char TRISA3:1;
1203 unsigned char TRISA4:1;
1204 unsigned char TRISA5:1;
1209 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
1211 #ifndef NO_BIT_DEFINES
1212 #define TRISA0 TRISA_bits.TRISA0
1213 #define TRISA1 TRISA_bits.TRISA1
1214 #define TRISA2 TRISA_bits.TRISA2
1215 #define TRISA3 TRISA_bits.TRISA3
1216 #define TRISA4 TRISA_bits.TRISA4
1217 #define TRISA5 TRISA_bits.TRISA5
1218 #endif /* NO_BIT_DEFINES */
1220 // ----- TRISB bits --------------------
1227 unsigned char TRISB4:1;
1228 unsigned char TRISB5:1;
1229 unsigned char TRISB6:1;
1230 unsigned char TRISB7:1;
1233 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
1235 #ifndef NO_BIT_DEFINES
1236 #define TRISB4 TRISB_bits.TRISB4
1237 #define TRISB5 TRISB_bits.TRISB5
1238 #define TRISB6 TRISB_bits.TRISB6
1239 #define TRISB7 TRISB_bits.TRISB7
1240 #endif /* NO_BIT_DEFINES */
1242 // ----- TRISC bits --------------------
1245 unsigned char TRISC0:1;
1246 unsigned char TRISC1:1;
1247 unsigned char TRISC2:1;
1248 unsigned char TRISC3:1;
1249 unsigned char TRISC4:1;
1250 unsigned char TRISC5:1;
1251 unsigned char TRISC6:1;
1252 unsigned char TRISC7:1;
1255 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
1257 #ifndef NO_BIT_DEFINES
1258 #define TRISC0 TRISC_bits.TRISC0
1259 #define TRISC1 TRISC_bits.TRISC1
1260 #define TRISC2 TRISC_bits.TRISC2
1261 #define TRISC3 TRISC_bits.TRISC3
1262 #define TRISC4 TRISC_bits.TRISC4
1263 #define TRISC5 TRISC_bits.TRISC5
1264 #define TRISC6 TRISC_bits.TRISC6
1265 #define TRISC7 TRISC_bits.TRISC7
1266 #endif /* NO_BIT_DEFINES */
1268 // ----- VRCON bits --------------------
1271 unsigned char VR0:1;
1272 unsigned char VR1:1;
1273 unsigned char VR2:1;
1274 unsigned char VR3:1;
1275 unsigned char VP6EN:1;
1276 unsigned char VRR:1;
1277 unsigned char C2VREN:1;
1278 unsigned char C1VREN:1;
1281 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
1283 #ifndef NO_BIT_DEFINES
1284 #define VR0 VRCON_bits.VR0
1285 #define VR1 VRCON_bits.VR1
1286 #define VR2 VRCON_bits.VR2
1287 #define VR3 VRCON_bits.VR3
1288 #define VP6EN VRCON_bits.VP6EN
1289 #define VRR VRCON_bits.VRR
1290 #define C2VREN VRCON_bits.C2VREN
1291 #define C1VREN VRCON_bits.C1VREN
1292 #endif /* NO_BIT_DEFINES */
1294 // ----- WDTCON bits --------------------
1297 unsigned char SWDTEN:1;
1298 unsigned char WDTPS0:1;
1299 unsigned char WDTPS1:1;
1300 unsigned char WDTPS2:1;
1301 unsigned char WDTPS3:1;
1307 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
1309 #ifndef NO_BIT_DEFINES
1310 #define SWDTEN WDTCON_bits.SWDTEN
1311 #define WDTPS0 WDTCON_bits.WDTPS0
1312 #define WDTPS1 WDTCON_bits.WDTPS1
1313 #define WDTPS2 WDTCON_bits.WDTPS2
1314 #define WDTPS3 WDTCON_bits.WDTPS3
1315 #endif /* NO_BIT_DEFINES */
1317 // ----- WPUA bits --------------------
1320 unsigned char WPUA0:1;
1321 unsigned char WPUA1:1;
1322 unsigned char WPUA2:1;
1324 unsigned char WPUA4:1;
1325 unsigned char WPUA5:1;
1330 extern volatile __WPUA_bits_t __at(WPUA_ADDR) WPUA_bits;
1332 #ifndef NO_BIT_DEFINES
1333 #define WPUA0 WPUA_bits.WPUA0
1334 #define WPUA1 WPUA_bits.WPUA1
1335 #define WPUA2 WPUA_bits.WPUA2
1336 #define WPUA4 WPUA_bits.WPUA4
1337 #define WPUA5 WPUA_bits.WPUA5
1338 #endif /* NO_BIT_DEFINES */
1340 // ----- WPUB bits --------------------
1347 unsigned char WPUB4:1;
1348 unsigned char WPUB5:1;
1349 unsigned char WPUB6:1;
1350 unsigned char WPUB7:1;
1353 extern volatile __WPUB_bits_t __at(WPUB_ADDR) WPUB_bits;
1355 #ifndef NO_BIT_DEFINES
1356 #define WPUB4 WPUB_bits.WPUB4
1357 #define WPUB5 WPUB_bits.WPUB5
1358 #define WPUB6 WPUB_bits.WPUB6
1359 #define WPUB7 WPUB_bits.WPUB7
1360 #endif /* NO_BIT_DEFINES */