2 // Register Declarations for Microchip 16F684 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define TMR2_ADDR 0x0011
42 #define T2CON_ADDR 0x0012
43 #define CCPR1L_ADDR 0x0013
44 #define CCPR1H_ADDR 0x0014
45 #define CCP1CON_ADDR 0x0015
46 #define PWM1CON_ADDR 0x0016
47 #define ECCPAS_ADDR 0x0017
48 #define WDTCON_ADDR 0x0018
49 #define CMCON0_ADDR 0x0019
50 #define CMCON1_ADDR 0x001A
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PCON_ADDR 0x008E
58 #define OSCCON_ADDR 0x008F
59 #define OSCTUNE_ADDR 0x0090
60 #define ANSEL_ADDR 0x0091
61 #define PR2_ADDR 0x0092
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define VRCON_ADDR 0x0099
67 #define EEDAT_ADDR 0x009A
68 #define EEDATA_ADDR 0x009A
69 #define EEADR_ADDR 0x009B
70 #define EECON1_ADDR 0x009C
71 #define EECON2_ADDR 0x009D
72 #define ADRESL_ADDR 0x009E
73 #define ADCON1_ADDR 0x009F
76 // Memory organization.
79 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
80 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
81 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
82 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
83 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
84 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
85 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
86 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
87 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
88 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
89 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
90 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
91 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
92 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
93 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
94 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
95 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
96 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
97 #pragma memmap PWM1CON_ADDR PWM1CON_ADDR SFR 0x000 // PWM1CON
98 #pragma memmap ECCPAS_ADDR ECCPAS_ADDR SFR 0x000 // ECCPAS
99 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
100 #pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
101 #pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
102 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
103 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
104 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
105 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
106 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
107 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
108 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
109 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
110 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
111 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
112 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
113 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
114 #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
115 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
116 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
117 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
118 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
119 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
120 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
121 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
122 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
123 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
124 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
128 // P16F684.INC Standard Header File, Version 1.03 Microchip Technology, Inc.
131 // This header file defines configurations, registers, and other useful bits of
132 // information for the PIC16F684 microcontroller. These names are taken to match
133 // the data sheets as closely as possible.
135 // Note that the processor must be selected before this file is
136 // included. The processor may be selected the following ways:
138 // 1. Command line switch:
139 // C:\ MPASM MYFILE.ASM /PIC16F684
140 // 2. LIST directive in the source file
142 // 3. Processor Type entry in the MPASM full-screen interface
144 //==========================================================================
148 //==========================================================================
149 //1.00 03/20/03 Original
150 //1.01 08/04/03 Updated CMCON1 address
151 //1.02 08/05/03 Updated names to match datasheet
152 //1.03 08/11/03 Updated ULPWUE bit name to match datasheet
153 //==========================================================================
157 //==========================================================================
160 // MESSG "Processor-header file mismatch. Verify selected processor."
163 //==========================================================================
165 // Register Definitions
167 //==========================================================================
172 //----- Register Files------------------------------------------------------
174 extern data __at (INDF_ADDR) volatile char INDF;
175 extern sfr __at (TMR0_ADDR) TMR0;
176 extern data __at (PCL_ADDR) volatile char PCL;
177 extern sfr __at (STATUS_ADDR) STATUS;
178 extern sfr __at (FSR_ADDR) FSR;
179 extern sfr __at (PORTA_ADDR) PORTA;
181 extern sfr __at (PORTC_ADDR) PORTC;
183 extern sfr __at (PCLATH_ADDR) PCLATH;
184 extern sfr __at (INTCON_ADDR) INTCON;
185 extern sfr __at (PIR1_ADDR) PIR1;
187 extern sfr __at (TMR1L_ADDR) TMR1L;
188 extern sfr __at (TMR1H_ADDR) TMR1H;
189 extern sfr __at (T1CON_ADDR) T1CON;
190 extern sfr __at (TMR2_ADDR) TMR2;
191 extern sfr __at (T2CON_ADDR) T2CON;
192 extern sfr __at (CCPR1L_ADDR) CCPR1L;
193 extern sfr __at (CCPR1H_ADDR) CCPR1H;
194 extern sfr __at (CCP1CON_ADDR) CCP1CON;
195 extern sfr __at (PWM1CON_ADDR) PWM1CON;
196 extern sfr __at (ECCPAS_ADDR) ECCPAS;
197 extern sfr __at (WDTCON_ADDR) WDTCON;
198 extern sfr __at (CMCON0_ADDR) CMCON0;
199 extern sfr __at (CMCON1_ADDR) CMCON1;
201 extern sfr __at (ADRESH_ADDR) ADRESH;
202 extern sfr __at (ADCON0_ADDR) ADCON0;
205 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
207 extern sfr __at (TRISA_ADDR) TRISA;
208 extern sfr __at (TRISC_ADDR) TRISC;
210 extern sfr __at (PIE1_ADDR) PIE1;
212 extern sfr __at (PCON_ADDR) PCON;
213 extern sfr __at (OSCCON_ADDR) OSCCON;
214 extern sfr __at (OSCTUNE_ADDR) OSCTUNE;
215 extern sfr __at (ANSEL_ADDR) ANSEL;
216 extern sfr __at (PR2_ADDR) PR2;
218 extern sfr __at (WPU_ADDR) WPU;
219 extern sfr __at (WPUA_ADDR) WPUA;
220 extern sfr __at (IOC_ADDR) IOC;
221 extern sfr __at (IOCA_ADDR) IOCA;
223 extern sfr __at (VRCON_ADDR) VRCON;
224 extern sfr __at (EEDAT_ADDR) EEDAT;
225 extern sfr __at (EEDATA_ADDR) EEDATA;
226 extern sfr __at (EEADR_ADDR) EEADR;
227 extern sfr __at (EECON1_ADDR) EECON1;
228 extern sfr __at (EECON2_ADDR) EECON2;
229 extern sfr __at (ADRESL_ADDR) ADRESL;
230 extern sfr __at (ADCON1_ADDR) ADCON1;
233 //----- STATUS Bits --------------------------------------------------------
236 //----- INTCON Bits --------------------------------------------------------
239 //----- PIR1 Bits ----------------------------------------------------------
242 //----- T1CON Bits ---------------------------------------------------------
245 //----- T2CON Bits ---------------------------------------------------------
248 //----- CCP1CON Bits -------------------------------------------------------
251 //----- PWM1CON Bits -------------------------------------------------------
254 //----- ECCPAS Bits --------------------------------------------------------
257 //----- WDTCON Bits --------------------------------------------------------
260 //----- CMCON0 Bits -------------------------------------------------------
263 //----- CMCON1 Bits -------------------------------------------------------
266 //----- ADCON0 Bits --------------------------------------------------------
269 //----- OPTION Bits --------------------------------------------------------
272 //----- PIE1 Bits ----------------------------------------------------------
275 //----- PCON Bits ----------------------------------------------------------
278 //----- OSCCON Bits --------------------------------------------------------
281 //----- OSCTUNE Bits -------------------------------------------------------
284 //----- ANSEL --------------------------------------------------------------
287 //----- IOC --------------------------------------------------------------
290 //----- IOCA --------------------------------------------------------------
293 //----- VRCON Bits ---------------------------------------------------------
296 //----- EECON1 -------------------------------------------------------------
299 //----- ADCON1 -------------------------------------------------------------
302 //==========================================================================
306 //==========================================================================
309 // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
310 // __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF'
312 //==========================================================================
314 // Configuration Bits
316 //==========================================================================
318 #define _FCMEN_ON 0x3FFF
319 #define _FCMEN_OFF 0x37FF
320 #define _IESO_ON 0x3FFF
321 #define _IESO_OFF 0x3BFF
322 #define _BOD_ON 0x3FFF
323 #define _BOD_NSLEEP 0x3EFF
324 #define _BOD_SBODEN 0x3DFF
325 #define _BOD_OFF 0x3CFF
326 #define _CPD_ON 0x3F7F
327 #define _CPD_OFF 0x3FFF
328 #define _CP_ON 0x3FBF
329 #define _CP_OFF 0x3FFF
330 #define _MCLRE_ON 0x3FFF
331 #define _MCLRE_OFF 0x3FDF
332 #define _PWRTE_OFF 0x3FFF
333 #define _PWRTE_ON 0x3FEF
334 #define _WDT_ON 0x3FFF
335 #define _WDT_OFF 0x3FF7
336 #define _LP_OSC 0x3FF8
337 #define _XT_OSC 0x3FF9
338 #define _HS_OSC 0x3FFA
339 #define _EC_OSC 0x3FFB
340 #define _INTRC_OSC_NOCLKOUT 0x3FFC
341 #define _INTRC_OSC_CLKOUT 0x3FFD
342 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
343 #define _EXTRC_OSC_CLKOUT 0x3FFF
344 #define _INTOSCIO 0x3FFC
345 #define _INTOSC 0x3FFD
346 #define _EXTRCIO 0x3FFE
347 #define _EXTRC 0x3FFF
351 // ----- ADCON0 bits --------------------
354 unsigned char ADON:1;
356 unsigned char CHS0:1;
357 unsigned char CHS1:1;
358 unsigned char CHS2:1;
360 unsigned char VCFG:1;
361 unsigned char ADFM:1;
365 unsigned char NOT_DONE:1;
375 unsigned char GO_DONE:1;
384 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
386 #define ADON ADCON0_bits.ADON
387 #define GO ADCON0_bits.GO
388 #define NOT_DONE ADCON0_bits.NOT_DONE
389 #define GO_DONE ADCON0_bits.GO_DONE
390 #define CHS0 ADCON0_bits.CHS0
391 #define CHS1 ADCON0_bits.CHS1
392 #define CHS2 ADCON0_bits.CHS2
393 #define VCFG ADCON0_bits.VCFG
394 #define ADFM ADCON0_bits.ADFM
396 // ----- CCP1CON bits --------------------
399 unsigned char CCP1M0:1;
400 unsigned char CCP1M1:1;
401 unsigned char CCP1M2:1;
402 unsigned char CCP1M3:1;
403 unsigned char DC1B0:1;
404 unsigned char DC1B1:1;
405 unsigned char P1M0:1;
406 unsigned char P1M1:1;
409 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
411 #define CCP1M0 CCP1CON_bits.CCP1M0
412 #define CCP1M1 CCP1CON_bits.CCP1M1
413 #define CCP1M2 CCP1CON_bits.CCP1M2
414 #define CCP1M3 CCP1CON_bits.CCP1M3
415 #define DC1B0 CCP1CON_bits.DC1B0
416 #define DC1B1 CCP1CON_bits.DC1B1
417 #define P1M0 CCP1CON_bits.P1M0
418 #define P1M1 CCP1CON_bits.P1M1
420 // ----- CMCON0 bits --------------------
427 unsigned char C1INV:1;
428 unsigned char C2INV:1;
429 unsigned char C1OUT:1;
430 unsigned char C2OUT:1;
433 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
435 #define CM0 CMCON0_bits.CM0
436 #define CM1 CMCON0_bits.CM1
437 #define CM2 CMCON0_bits.CM2
438 #define CIS CMCON0_bits.CIS
439 #define C1INV CMCON0_bits.C1INV
440 #define C2INV CMCON0_bits.C2INV
441 #define C1OUT CMCON0_bits.C1OUT
442 #define C2OUT CMCON0_bits.C2OUT
444 // ----- CMCON1 bits --------------------
447 unsigned char C2SYNC:1;
448 unsigned char T1GSS:1;
457 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
459 #define C2SYNC CMCON1_bits.C2SYNC
460 #define T1GSS CMCON1_bits.T1GSS
462 // ----- ECCPAS bits --------------------
465 unsigned char PSSBD0:1;
466 unsigned char PSSBD1:1;
467 unsigned char PSSAC0:1;
468 unsigned char PSSAC1:1;
469 unsigned char ECCPAS0:1;
470 unsigned char ECCPAS1:1;
471 unsigned char ECCPAS2:1;
472 unsigned char ECCPASE:1;
475 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
477 #define PSSBD0 ECCPAS_bits.PSSBD0
478 #define PSSBD1 ECCPAS_bits.PSSBD1
479 #define PSSAC0 ECCPAS_bits.PSSAC0
480 #define PSSAC1 ECCPAS_bits.PSSAC1
481 #define ECCPAS0 ECCPAS_bits.ECCPAS0
482 #define ECCPAS1 ECCPAS_bits.ECCPAS1
483 #define ECCPAS2 ECCPAS_bits.ECCPAS2
484 #define ECCPASE ECCPAS_bits.ECCPASE
486 // ----- INTCON bits --------------------
489 unsigned char RAIF:1;
490 unsigned char INTF:1;
491 unsigned char T0IF:1;
492 unsigned char RAIE:1;
493 unsigned char INTE:1;
494 unsigned char T0IE:1;
495 unsigned char PEIE:1;
499 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
501 #define RAIF INTCON_bits.RAIF
502 #define INTF INTCON_bits.INTF
503 #define T0IF INTCON_bits.T0IF
504 #define RAIE INTCON_bits.RAIE
505 #define INTE INTCON_bits.INTE
506 #define T0IE INTCON_bits.T0IE
507 #define PEIE INTCON_bits.PEIE
508 #define GIE INTCON_bits.GIE
510 // ----- OPTION_REG bits --------------------
517 unsigned char T0SE:1;
518 unsigned char T0CS:1;
519 unsigned char INTEDG:1;
520 unsigned char NOT_RAPU:1;
522 } __OPTION_REG_bits_t;
523 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
525 #define PS0 OPTION_REG_bits.PS0
526 #define PS1 OPTION_REG_bits.PS1
527 #define PS2 OPTION_REG_bits.PS2
528 #define PSA OPTION_REG_bits.PSA
529 #define T0SE OPTION_REG_bits.T0SE
530 #define T0CS OPTION_REG_bits.T0CS
531 #define INTEDG OPTION_REG_bits.INTEDG
532 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
534 // ----- OSCCON bits --------------------
540 unsigned char OSTS:1;
541 unsigned char IRCF0:1;
542 unsigned char IRCF1:1;
543 unsigned char IRCF2:1;
547 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
549 #define SCS OSCCON_bits.SCS
550 #define LTS OSCCON_bits.LTS
551 #define HTS OSCCON_bits.HTS
552 #define OSTS OSCCON_bits.OSTS
553 #define IRCF0 OSCCON_bits.IRCF0
554 #define IRCF1 OSCCON_bits.IRCF1
555 #define IRCF2 OSCCON_bits.IRCF2
557 // ----- OSCTUNE bits --------------------
560 unsigned char TUN0:1;
561 unsigned char TUN1:1;
562 unsigned char TUN2:1;
563 unsigned char TUN3:1;
564 unsigned char TUN4:1;
565 unsigned char ANS5:1;
566 unsigned char ANS6:1;
567 unsigned char ANS7:1;
570 unsigned char ANS0:1;
571 unsigned char ANS1:1;
572 unsigned char ANS2:1;
573 unsigned char ANS3:1;
574 unsigned char ANS4:1;
575 unsigned char IOC5:1;
580 unsigned char IOC0:1;
581 unsigned char IOC1:1;
582 unsigned char IOC2:1;
583 unsigned char IOC3:1;
584 unsigned char IOC4:1;
585 unsigned char IOCA5:1;
590 unsigned char IOCA0:1;
591 unsigned char IOCA1:1;
592 unsigned char IOCA2:1;
593 unsigned char IOCA3:1;
594 unsigned char IOCA4:1;
600 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
602 #define TUN0 OSCTUNE_bits.TUN0
603 #define ANS0 OSCTUNE_bits.ANS0
604 #define IOC0 OSCTUNE_bits.IOC0
605 #define IOCA0 OSCTUNE_bits.IOCA0
606 #define TUN1 OSCTUNE_bits.TUN1
607 #define ANS1 OSCTUNE_bits.ANS1
608 #define IOC1 OSCTUNE_bits.IOC1
609 #define IOCA1 OSCTUNE_bits.IOCA1
610 #define TUN2 OSCTUNE_bits.TUN2
611 #define ANS2 OSCTUNE_bits.ANS2
612 #define IOC2 OSCTUNE_bits.IOC2
613 #define IOCA2 OSCTUNE_bits.IOCA2
614 #define TUN3 OSCTUNE_bits.TUN3
615 #define ANS3 OSCTUNE_bits.ANS3
616 #define IOC3 OSCTUNE_bits.IOC3
617 #define IOCA3 OSCTUNE_bits.IOCA3
618 #define TUN4 OSCTUNE_bits.TUN4
619 #define ANS4 OSCTUNE_bits.ANS4
620 #define IOC4 OSCTUNE_bits.IOC4
621 #define IOCA4 OSCTUNE_bits.IOCA4
622 #define ANS5 OSCTUNE_bits.ANS5
623 #define IOC5 OSCTUNE_bits.IOC5
624 #define IOCA5 OSCTUNE_bits.IOCA5
625 #define ANS6 OSCTUNE_bits.ANS6
626 #define ANS7 OSCTUNE_bits.ANS7
628 // ----- PCON bits --------------------
631 unsigned char NOT_BOD:1;
632 unsigned char NOT_POR:1;
635 unsigned char SBODEN:1;
636 unsigned char ULPWUE:1;
641 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
643 #define NOT_BOD PCON_bits.NOT_BOD
644 #define NOT_POR PCON_bits.NOT_POR
645 #define SBODEN PCON_bits.SBODEN
646 #define ULPWUE PCON_bits.ULPWUE
648 // ----- PIE1 bits --------------------
651 unsigned char T1IE:1;
652 unsigned char T2IE:1;
653 unsigned char OSFIE:1;
654 unsigned char C1IE:1;
655 unsigned char C2IE:1;
656 unsigned char CCP1IE:1;
657 unsigned char ADIE:1;
658 unsigned char EEIE:1;
661 unsigned char TMR1IE:1;
662 unsigned char TMR2IE:1;
671 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
673 #define T1IE PIE1_bits.T1IE
674 #define TMR1IE PIE1_bits.TMR1IE
675 #define T2IE PIE1_bits.T2IE
676 #define TMR2IE PIE1_bits.TMR2IE
677 #define OSFIE PIE1_bits.OSFIE
678 #define C1IE PIE1_bits.C1IE
679 #define C2IE PIE1_bits.C2IE
680 #define CCP1IE PIE1_bits.CCP1IE
681 #define ADIE PIE1_bits.ADIE
682 #define EEIE PIE1_bits.EEIE
684 // ----- PIR1 bits --------------------
687 unsigned char T1IF:1;
688 unsigned char T2IF:1;
689 unsigned char OSFIF:1;
690 unsigned char C1IF:1;
691 unsigned char C2IF:1;
692 unsigned char CCP1IF:1;
693 unsigned char ADIF:1;
694 unsigned char EEIF:1;
697 unsigned char TMR1IF:1;
698 unsigned char TMR2IF:1;
707 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
709 #define T1IF PIR1_bits.T1IF
710 #define TMR1IF PIR1_bits.TMR1IF
711 #define T2IF PIR1_bits.T2IF
712 #define TMR2IF PIR1_bits.TMR2IF
713 #define OSFIF PIR1_bits.OSFIF
714 #define C1IF PIR1_bits.C1IF
715 #define C2IF PIR1_bits.C2IF
716 #define CCP1IF PIR1_bits.CCP1IF
717 #define ADIF PIR1_bits.ADIF
718 #define EEIF PIR1_bits.EEIF
720 // ----- PWM1CON bits --------------------
723 unsigned char PDC0:1;
724 unsigned char PDC1:1;
725 unsigned char PDC2:1;
726 unsigned char PDC3:1;
727 unsigned char PDC4:1;
728 unsigned char PDC5:1;
729 unsigned char PDC6:1;
730 unsigned char PRSEN:1;
733 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
735 #define PDC0 PWM1CON_bits.PDC0
736 #define PDC1 PWM1CON_bits.PDC1
737 #define PDC2 PWM1CON_bits.PDC2
738 #define PDC3 PWM1CON_bits.PDC3
739 #define PDC4 PWM1CON_bits.PDC4
740 #define PDC5 PWM1CON_bits.PDC5
741 #define PDC6 PWM1CON_bits.PDC6
742 #define PRSEN PWM1CON_bits.PRSEN
744 // ----- STATUS bits --------------------
750 unsigned char NOT_PD:1;
751 unsigned char NOT_TO:1;
757 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
759 #define C STATUS_bits.C
760 #define DC STATUS_bits.DC
761 #define Z STATUS_bits.Z
762 #define NOT_PD STATUS_bits.NOT_PD
763 #define NOT_TO STATUS_bits.NOT_TO
764 #define RP0 STATUS_bits.RP0
765 #define RP1 STATUS_bits.RP1
766 #define IRP STATUS_bits.IRP
768 // ----- T1CON bits --------------------
771 unsigned char TMR1ON:1;
772 unsigned char TMR1CS:1;
773 unsigned char NOT_T1SYNC:1;
774 unsigned char T1OSCEN:1;
775 unsigned char T1CKPS0:1;
776 unsigned char T1CKPS1:1;
777 unsigned char TMR1GE:1;
778 unsigned char T1GINV:1;
781 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
783 #define TMR1ON T1CON_bits.TMR1ON
784 #define TMR1CS T1CON_bits.TMR1CS
785 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
786 #define T1OSCEN T1CON_bits.T1OSCEN
787 #define T1CKPS0 T1CON_bits.T1CKPS0
788 #define T1CKPS1 T1CON_bits.T1CKPS1
789 #define TMR1GE T1CON_bits.TMR1GE
790 #define T1GINV T1CON_bits.T1GINV
792 // ----- T2CON bits --------------------
795 unsigned char T2CKPS0:1;
796 unsigned char T2CKPS1:1;
797 unsigned char TMR2ON:1;
798 unsigned char TOUTPS0:1;
799 unsigned char TOUTPS1:1;
800 unsigned char TOUTPS2:1;
801 unsigned char TOUTPS3:1;
805 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
807 #define T2CKPS0 T2CON_bits.T2CKPS0
808 #define T2CKPS1 T2CON_bits.T2CKPS1
809 #define TMR2ON T2CON_bits.TMR2ON
810 #define TOUTPS0 T2CON_bits.TOUTPS0
811 #define TOUTPS1 T2CON_bits.TOUTPS1
812 #define TOUTPS2 T2CON_bits.TOUTPS2
813 #define TOUTPS3 T2CON_bits.TOUTPS3
815 // ----- VRCON bits --------------------
822 unsigned char ADCS0:1;
824 unsigned char ADCS2:1;
825 unsigned char VREN:1;
830 unsigned char WREN:1;
831 unsigned char WRERR:1;
833 unsigned char ADCS1:1;
838 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
840 #define VR0 VRCON_bits.VR0
841 #define RD VRCON_bits.RD
842 #define VR1 VRCON_bits.VR1
843 #define WR VRCON_bits.WR
844 #define VR2 VRCON_bits.VR2
845 #define WREN VRCON_bits.WREN
846 #define VR3 VRCON_bits.VR3
847 #define WRERR VRCON_bits.WRERR
848 #define ADCS0 VRCON_bits.ADCS0
849 #define VRR VRCON_bits.VRR
850 #define ADCS1 VRCON_bits.ADCS1
851 #define ADCS2 VRCON_bits.ADCS2
852 #define VREN VRCON_bits.VREN
854 // ----- WDTCON bits --------------------
857 unsigned char SWDTEN:1;
858 unsigned char WDTPS0:1;
859 unsigned char WDTPS1:1;
860 unsigned char WDTPS2:1;
861 unsigned char WDTPS3:1;
867 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
869 #define SWDTEN WDTCON_bits.SWDTEN
870 #define WDTPS0 WDTCON_bits.WDTPS0
871 #define WDTPS1 WDTCON_bits.WDTPS1
872 #define WDTPS2 WDTCON_bits.WDTPS2
873 #define WDTPS3 WDTCON_bits.WDTPS3