2 // Register Declarations for Microchip 16F684 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define TMR2_ADDR 0x0011
42 #define T2CON_ADDR 0x0012
43 #define CCPR1L_ADDR 0x0013
44 #define CCPR1H_ADDR 0x0014
45 #define CCP1CON_ADDR 0x0015
46 #define PWM1CON_ADDR 0x0016
47 #define ECCPAS_ADDR 0x0017
48 #define WDTCON_ADDR 0x0018
49 #define CMCON0_ADDR 0x0019
50 #define CMCON1_ADDR 0x001A
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PCON_ADDR 0x008E
58 #define OSCCON_ADDR 0x008F
59 #define OSCTUNE_ADDR 0x0090
60 #define ANSEL_ADDR 0x0091
61 #define PR2_ADDR 0x0092
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define VRCON_ADDR 0x0099
67 #define EEDAT_ADDR 0x009A
68 #define EEDATA_ADDR 0x009A
69 #define EEADR_ADDR 0x009B
70 #define EECON1_ADDR 0x009C
71 #define EECON2_ADDR 0x009D
72 #define ADRESL_ADDR 0x009E
73 #define ADCON1_ADDR 0x009F
76 // Memory organization.
82 // P16F684.INC Standard Header File, Version 1.03 Microchip Technology, Inc.
85 // This header file defines configurations, registers, and other useful bits of
86 // information for the PIC16F684 microcontroller. These names are taken to match
87 // the data sheets as closely as possible.
89 // Note that the processor must be selected before this file is
90 // included. The processor may be selected the following ways:
92 // 1. Command line switch:
93 // C:\ MPASM MYFILE.ASM /PIC16F684
94 // 2. LIST directive in the source file
96 // 3. Processor Type entry in the MPASM full-screen interface
98 //==========================================================================
102 //==========================================================================
103 //1.00 03/20/03 Original
104 //1.01 08/04/03 Updated CMCON1 address
105 //1.02 08/05/03 Updated names to match datasheet
106 //1.03 08/11/03 Updated ULPWUE bit name to match datasheet
107 //==========================================================================
111 //==========================================================================
114 // MESSG "Processor-header file mismatch. Verify selected processor."
117 //==========================================================================
119 // Register Definitions
121 //==========================================================================
126 //----- Register Files------------------------------------------------------
128 extern __sfr __at (INDF_ADDR) INDF;
129 extern __sfr __at (TMR0_ADDR) TMR0;
130 extern __sfr __at (PCL_ADDR) PCL;
131 extern __sfr __at (STATUS_ADDR) STATUS;
132 extern __sfr __at (FSR_ADDR) FSR;
133 extern __sfr __at (PORTA_ADDR) PORTA;
135 extern __sfr __at (PORTC_ADDR) PORTC;
137 extern __sfr __at (PCLATH_ADDR) PCLATH;
138 extern __sfr __at (INTCON_ADDR) INTCON;
139 extern __sfr __at (PIR1_ADDR) PIR1;
141 extern __sfr __at (TMR1L_ADDR) TMR1L;
142 extern __sfr __at (TMR1H_ADDR) TMR1H;
143 extern __sfr __at (T1CON_ADDR) T1CON;
144 extern __sfr __at (TMR2_ADDR) TMR2;
145 extern __sfr __at (T2CON_ADDR) T2CON;
146 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
147 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
148 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
149 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
150 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
151 extern __sfr __at (WDTCON_ADDR) WDTCON;
152 extern __sfr __at (CMCON0_ADDR) CMCON0;
153 extern __sfr __at (CMCON1_ADDR) CMCON1;
155 extern __sfr __at (ADRESH_ADDR) ADRESH;
156 extern __sfr __at (ADCON0_ADDR) ADCON0;
159 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
161 extern __sfr __at (TRISA_ADDR) TRISA;
162 extern __sfr __at (TRISC_ADDR) TRISC;
164 extern __sfr __at (PIE1_ADDR) PIE1;
166 extern __sfr __at (PCON_ADDR) PCON;
167 extern __sfr __at (OSCCON_ADDR) OSCCON;
168 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
169 extern __sfr __at (ANSEL_ADDR) ANSEL;
170 extern __sfr __at (PR2_ADDR) PR2;
172 extern __sfr __at (WPU_ADDR) WPU;
173 extern __sfr __at (WPUA_ADDR) WPUA;
174 extern __sfr __at (IOC_ADDR) IOC;
175 extern __sfr __at (IOCA_ADDR) IOCA;
177 extern __sfr __at (VRCON_ADDR) VRCON;
178 extern __sfr __at (EEDAT_ADDR) EEDAT;
179 extern __sfr __at (EEDATA_ADDR) EEDATA;
180 extern __sfr __at (EEADR_ADDR) EEADR;
181 extern __sfr __at (EECON1_ADDR) EECON1;
182 extern __sfr __at (EECON2_ADDR) EECON2;
183 extern __sfr __at (ADRESL_ADDR) ADRESL;
184 extern __sfr __at (ADCON1_ADDR) ADCON1;
187 //----- STATUS Bits --------------------------------------------------------
190 //----- INTCON Bits --------------------------------------------------------
193 //----- PIR1 Bits ----------------------------------------------------------
196 //----- T1CON Bits ---------------------------------------------------------
199 //----- T2CON Bits ---------------------------------------------------------
202 //----- CCP1CON Bits -------------------------------------------------------
205 //----- PWM1CON Bits -------------------------------------------------------
208 //----- ECCPAS Bits --------------------------------------------------------
211 //----- WDTCON Bits --------------------------------------------------------
214 //----- COMCON0 Bits -------------------------------------------------------
217 //----- COMCON1 Bits -------------------------------------------------------
220 //----- ADCON0 Bits --------------------------------------------------------
223 //----- OPTION Bits --------------------------------------------------------
226 //----- PIE1 Bits ----------------------------------------------------------
229 //----- PCON Bits ----------------------------------------------------------
232 //----- OSCCON Bits --------------------------------------------------------
235 //----- OSCTUNE Bits -------------------------------------------------------
238 //----- ANSEL --------------------------------------------------------------
241 //----- IOC --------------------------------------------------------------
244 //----- IOCA --------------------------------------------------------------
247 //----- VRCON Bits ---------------------------------------------------------
250 //----- EECON1 -------------------------------------------------------------
253 //----- ADCON1 -------------------------------------------------------------
256 //==========================================================================
260 //==========================================================================
263 // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
264 // __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF'
266 //==========================================================================
268 // Configuration Bits
270 //==========================================================================
272 #define _FCMEN_ON 0x3FFF
273 #define _FCMEN_OFF 0x37FF
274 #define _IESO_ON 0x3FFF
275 #define _IESO_OFF 0x3BFF
276 #define _BOD_ON 0x3FFF
277 #define _BOD_NSLEEP 0x3EFF
278 #define _BOD_SBODEN 0x3DFF
279 #define _BOD_OFF 0x3CFF
280 #define _CPD_ON 0x3F7F
281 #define _CPD_OFF 0x3FFF
282 #define _CP_ON 0x3FBF
283 #define _CP_OFF 0x3FFF
284 #define _MCLRE_ON 0x3FFF
285 #define _MCLRE_OFF 0x3FDF
286 #define _PWRTE_OFF 0x3FFF
287 #define _PWRTE_ON 0x3FEF
288 #define _WDT_ON 0x3FFF
289 #define _WDT_OFF 0x3FF7
290 #define _LP_OSC 0x3FF8
291 #define _XT_OSC 0x3FF9
292 #define _HS_OSC 0x3FFA
293 #define _EC_OSC 0x3FFB
294 #define _INTRC_OSC_NOCLKOUT 0x3FFC
295 #define _INTRC_OSC_CLKOUT 0x3FFD
296 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
297 #define _EXTRC_OSC_CLKOUT 0x3FFF
298 #define _INTOSCIO 0x3FFC
299 #define _INTOSC 0x3FFD
300 #define _EXTRCIO 0x3FFE
301 #define _EXTRC 0x3FFF
305 // ----- ADCON0 bits --------------------
308 unsigned char ADON:1;
310 unsigned char CHS0:1;
311 unsigned char CHS1:1;
312 unsigned char CHS2:1;
314 unsigned char VCFG:1;
315 unsigned char ADFM:1;
319 unsigned char NOT_DONE:1;
329 unsigned char GO_DONE:1;
338 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
340 #define ADON ADCON0_bits.ADON
341 #define GO ADCON0_bits.GO
342 #define NOT_DONE ADCON0_bits.NOT_DONE
343 #define GO_DONE ADCON0_bits.GO_DONE
344 #define CHS0 ADCON0_bits.CHS0
345 #define CHS1 ADCON0_bits.CHS1
346 #define CHS2 ADCON0_bits.CHS2
347 #define VCFG ADCON0_bits.VCFG
348 #define ADFM ADCON0_bits.ADFM
350 // ----- ADCON1 bits --------------------
357 unsigned char ADCS0:1;
358 unsigned char ADCS1:1;
359 unsigned char ADCS2:1;
363 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
365 #define ADCS0 ADCON1_bits.ADCS0
366 #define ADCS1 ADCON1_bits.ADCS1
367 #define ADCS2 ADCON1_bits.ADCS2
369 // ----- ANSEL bits --------------------
372 unsigned char ANS0:1;
373 unsigned char ANS1:1;
374 unsigned char ANS2:1;
375 unsigned char ANS3:1;
376 unsigned char ANS4:1;
377 unsigned char ANS5:1;
378 unsigned char ANS6:1;
379 unsigned char ANS7:1;
382 extern volatile __ANSEL_bits_t __at(ANSEL_ADDR) ANSEL_bits;
384 #define ANS0 ANSEL_bits.ANS0
385 #define ANS1 ANSEL_bits.ANS1
386 #define ANS2 ANSEL_bits.ANS2
387 #define ANS3 ANSEL_bits.ANS3
388 #define ANS4 ANSEL_bits.ANS4
389 #define ANS5 ANSEL_bits.ANS5
390 #define ANS6 ANSEL_bits.ANS6
391 #define ANS7 ANSEL_bits.ANS7
393 // ----- CCP1CON bits --------------------
396 unsigned char CCP1M0:1;
397 unsigned char CCP1M1:1;
398 unsigned char CCP1M2:1;
399 unsigned char CCP1M3:1;
400 unsigned char DC1B0:1;
401 unsigned char DC1B1:1;
402 unsigned char P1M0:1;
403 unsigned char P1M1:1;
406 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
408 #define CCP1M0 CCP1CON_bits.CCP1M0
409 #define CCP1M1 CCP1CON_bits.CCP1M1
410 #define CCP1M2 CCP1CON_bits.CCP1M2
411 #define CCP1M3 CCP1CON_bits.CCP1M3
412 #define DC1B0 CCP1CON_bits.DC1B0
413 #define DC1B1 CCP1CON_bits.DC1B1
414 #define P1M0 CCP1CON_bits.P1M0
415 #define P1M1 CCP1CON_bits.P1M1
417 // ----- CMCON0 bits --------------------
424 unsigned char C1INV:1;
425 unsigned char C2INV:1;
426 unsigned char C1OUT:1;
427 unsigned char C2OUT:1;
430 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
432 #define CM0 CMCON0_bits.CM0
433 #define CM1 CMCON0_bits.CM1
434 #define CM2 CMCON0_bits.CM2
435 #define CIS CMCON0_bits.CIS
436 #define C1INV CMCON0_bits.C1INV
437 #define C2INV CMCON0_bits.C2INV
438 #define C1OUT CMCON0_bits.C1OUT
439 #define C2OUT CMCON0_bits.C2OUT
441 // ----- CMCON1 bits --------------------
444 unsigned char C2SYNC:1;
445 unsigned char T1GSS:1;
454 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
456 #define C2SYNC CMCON1_bits.C2SYNC
457 #define T1GSS CMCON1_bits.T1GSS
459 // ----- ECCPAS bits --------------------
462 unsigned char PSSBD0:1;
463 unsigned char PSSBD1:1;
464 unsigned char PSSAC0:1;
465 unsigned char PSSAC1:1;
466 unsigned char ECCPAS0:1;
467 unsigned char ECCPAS1:1;
468 unsigned char ECCPAS2:1;
469 unsigned char ECCPASE:1;
472 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
474 #define PSSBD0 ECCPAS_bits.PSSBD0
475 #define PSSBD1 ECCPAS_bits.PSSBD1
476 #define PSSAC0 ECCPAS_bits.PSSAC0
477 #define PSSAC1 ECCPAS_bits.PSSAC1
478 #define ECCPAS0 ECCPAS_bits.ECCPAS0
479 #define ECCPAS1 ECCPAS_bits.ECCPAS1
480 #define ECCPAS2 ECCPAS_bits.ECCPAS2
481 #define ECCPASE ECCPAS_bits.ECCPASE
483 // ----- EECON1 bits --------------------
488 unsigned char WREN:1;
489 unsigned char WRERR:1;
496 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
498 #define RD EECON1_bits.RD
499 #define WR EECON1_bits.WR
500 #define WREN EECON1_bits.WREN
501 #define WRERR EECON1_bits.WRERR
503 // ----- INTCON bits --------------------
506 unsigned char RAIF:1;
507 unsigned char INTF:1;
508 unsigned char T0IF:1;
509 unsigned char RAIE:1;
510 unsigned char INTE:1;
511 unsigned char T0IE:1;
512 unsigned char PEIE:1;
516 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
518 #define RAIF INTCON_bits.RAIF
519 #define INTF INTCON_bits.INTF
520 #define T0IF INTCON_bits.T0IF
521 #define RAIE INTCON_bits.RAIE
522 #define INTE INTCON_bits.INTE
523 #define T0IE INTCON_bits.T0IE
524 #define PEIE INTCON_bits.PEIE
525 #define GIE INTCON_bits.GIE
527 // ----- IOC bits --------------------
530 unsigned char IOC0:1;
531 unsigned char IOC1:1;
532 unsigned char IOC2:1;
533 unsigned char IOC3:1;
534 unsigned char IOC4:1;
535 unsigned char IOC5:1;
540 extern volatile __IOC_bits_t __at(IOC_ADDR) IOC_bits;
542 #define IOC0 IOC_bits.IOC0
543 #define IOC1 IOC_bits.IOC1
544 #define IOC2 IOC_bits.IOC2
545 #define IOC3 IOC_bits.IOC3
546 #define IOC4 IOC_bits.IOC4
547 #define IOC5 IOC_bits.IOC5
549 // ----- IOCA bits --------------------
552 unsigned char IOCA0:1;
553 unsigned char IOCA1:1;
554 unsigned char IOCA2:1;
555 unsigned char IOCA3:1;
556 unsigned char IOCA4:1;
557 unsigned char IOCA5:1;
562 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
564 #define IOCA0 IOCA_bits.IOCA0
565 #define IOCA1 IOCA_bits.IOCA1
566 #define IOCA2 IOCA_bits.IOCA2
567 #define IOCA3 IOCA_bits.IOCA3
568 #define IOCA4 IOCA_bits.IOCA4
569 #define IOCA5 IOCA_bits.IOCA5
571 // ----- OPTION_REG bits --------------------
578 unsigned char T0SE:1;
579 unsigned char T0CS:1;
580 unsigned char INTEDG:1;
581 unsigned char NOT_RAPU:1;
583 } __OPTION_REG_bits_t;
584 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
586 #define PS0 OPTION_REG_bits.PS0
587 #define PS1 OPTION_REG_bits.PS1
588 #define PS2 OPTION_REG_bits.PS2
589 #define PSA OPTION_REG_bits.PSA
590 #define T0SE OPTION_REG_bits.T0SE
591 #define T0CS OPTION_REG_bits.T0CS
592 #define INTEDG OPTION_REG_bits.INTEDG
593 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
595 // ----- OSCCON bits --------------------
601 unsigned char OSTS:1;
602 unsigned char IRCF0:1;
603 unsigned char IRCF1:1;
604 unsigned char IRCF2:1;
608 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
610 #define SCS OSCCON_bits.SCS
611 #define LTS OSCCON_bits.LTS
612 #define HTS OSCCON_bits.HTS
613 #define OSTS OSCCON_bits.OSTS
614 #define IRCF0 OSCCON_bits.IRCF0
615 #define IRCF1 OSCCON_bits.IRCF1
616 #define IRCF2 OSCCON_bits.IRCF2
618 // ----- OSCTUNE bits --------------------
621 unsigned char TUN0:1;
622 unsigned char TUN1:1;
623 unsigned char TUN2:1;
624 unsigned char TUN3:1;
625 unsigned char TUN4:1;
631 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
633 #define TUN0 OSCTUNE_bits.TUN0
634 #define TUN1 OSCTUNE_bits.TUN1
635 #define TUN2 OSCTUNE_bits.TUN2
636 #define TUN3 OSCTUNE_bits.TUN3
637 #define TUN4 OSCTUNE_bits.TUN4
639 // ----- PCON bits --------------------
642 unsigned char NOT_BOD:1;
643 unsigned char NOT_POR:1;
646 unsigned char SBODEN:1;
647 unsigned char ULPWUE:1;
652 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
654 #define NOT_BOD PCON_bits.NOT_BOD
655 #define NOT_POR PCON_bits.NOT_POR
656 #define SBODEN PCON_bits.SBODEN
657 #define ULPWUE PCON_bits.ULPWUE
659 // ----- PIE1 bits --------------------
662 unsigned char T1IE:1;
663 unsigned char T2IE:1;
664 unsigned char OSFIE:1;
665 unsigned char C1IE:1;
666 unsigned char C2IE:1;
667 unsigned char CCP1IE:1;
668 unsigned char ADIE:1;
669 unsigned char EEIE:1;
672 unsigned char TMR1IE:1;
673 unsigned char TMR2IE:1;
682 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
684 #define T1IE PIE1_bits.T1IE
685 #define TMR1IE PIE1_bits.TMR1IE
686 #define T2IE PIE1_bits.T2IE
687 #define TMR2IE PIE1_bits.TMR2IE
688 #define OSFIE PIE1_bits.OSFIE
689 #define C1IE PIE1_bits.C1IE
690 #define C2IE PIE1_bits.C2IE
691 #define CCP1IE PIE1_bits.CCP1IE
692 #define ADIE PIE1_bits.ADIE
693 #define EEIE PIE1_bits.EEIE
695 // ----- PIR1 bits --------------------
698 unsigned char T1IF:1;
699 unsigned char T2IF:1;
700 unsigned char OSFIF:1;
701 unsigned char C1IF:1;
702 unsigned char C2IF:1;
703 unsigned char CCP1IF:1;
704 unsigned char ADIF:1;
705 unsigned char EEIF:1;
708 unsigned char TMR1IF:1;
709 unsigned char TMR2IF:1;
718 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
720 #define T1IF PIR1_bits.T1IF
721 #define TMR1IF PIR1_bits.TMR1IF
722 #define T2IF PIR1_bits.T2IF
723 #define TMR2IF PIR1_bits.TMR2IF
724 #define OSFIF PIR1_bits.OSFIF
725 #define C1IF PIR1_bits.C1IF
726 #define C2IF PIR1_bits.C2IF
727 #define CCP1IF PIR1_bits.CCP1IF
728 #define ADIF PIR1_bits.ADIF
729 #define EEIF PIR1_bits.EEIF
731 // ----- PORTA bits --------------------
744 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
746 #define RA0 PORTA_bits.RA0
747 #define RA1 PORTA_bits.RA1
748 #define RA2 PORTA_bits.RA2
749 #define RA3 PORTA_bits.RA3
750 #define RA4 PORTA_bits.RA4
751 #define RA5 PORTA_bits.RA5
753 // ----- PORTC bits --------------------
766 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
768 #define RC0 PORTC_bits.RC0
769 #define RC1 PORTC_bits.RC1
770 #define RC2 PORTC_bits.RC2
771 #define RC3 PORTC_bits.RC3
772 #define RC4 PORTC_bits.RC4
773 #define RC5 PORTC_bits.RC5
774 #define RC6 PORTC_bits.RC6
775 #define RC7 PORTC_bits.RC7
777 // ----- PWM1CON bits --------------------
780 unsigned char PDC0:1;
781 unsigned char PDC1:1;
782 unsigned char PDC2:1;
783 unsigned char PDC3:1;
784 unsigned char PDC4:1;
785 unsigned char PDC5:1;
786 unsigned char PDC6:1;
787 unsigned char PRSEN:1;
790 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
792 #define PDC0 PWM1CON_bits.PDC0
793 #define PDC1 PWM1CON_bits.PDC1
794 #define PDC2 PWM1CON_bits.PDC2
795 #define PDC3 PWM1CON_bits.PDC3
796 #define PDC4 PWM1CON_bits.PDC4
797 #define PDC5 PWM1CON_bits.PDC5
798 #define PDC6 PWM1CON_bits.PDC6
799 #define PRSEN PWM1CON_bits.PRSEN
801 // ----- STATUS bits --------------------
807 unsigned char NOT_PD:1;
808 unsigned char NOT_TO:1;
814 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
816 #define C STATUS_bits.C
817 #define DC STATUS_bits.DC
818 #define Z STATUS_bits.Z
819 #define NOT_PD STATUS_bits.NOT_PD
820 #define NOT_TO STATUS_bits.NOT_TO
821 #define RP0 STATUS_bits.RP0
822 #define RP1 STATUS_bits.RP1
823 #define IRP STATUS_bits.IRP
825 // ----- T1CON bits --------------------
828 unsigned char TMR1ON:1;
829 unsigned char TMR1CS:1;
830 unsigned char NOT_T1SYNC:1;
831 unsigned char T1OSCEN:1;
832 unsigned char T1CKPS0:1;
833 unsigned char T1CKPS1:1;
834 unsigned char TMR1GE:1;
835 unsigned char T1GINV:1;
838 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
840 #define TMR1ON T1CON_bits.TMR1ON
841 #define TMR1CS T1CON_bits.TMR1CS
842 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
843 #define T1OSCEN T1CON_bits.T1OSCEN
844 #define T1CKPS0 T1CON_bits.T1CKPS0
845 #define T1CKPS1 T1CON_bits.T1CKPS1
846 #define TMR1GE T1CON_bits.TMR1GE
847 #define T1GINV T1CON_bits.T1GINV
849 // ----- T2CON bits --------------------
852 unsigned char T2CKPS0:1;
853 unsigned char T2CKPS1:1;
854 unsigned char TMR2ON:1;
855 unsigned char TOUTPS0:1;
856 unsigned char TOUTPS1:1;
857 unsigned char TOUTPS2:1;
858 unsigned char TOUTPS3:1;
862 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
864 #define T2CKPS0 T2CON_bits.T2CKPS0
865 #define T2CKPS1 T2CON_bits.T2CKPS1
866 #define TMR2ON T2CON_bits.TMR2ON
867 #define TOUTPS0 T2CON_bits.TOUTPS0
868 #define TOUTPS1 T2CON_bits.TOUTPS1
869 #define TOUTPS2 T2CON_bits.TOUTPS2
870 #define TOUTPS3 T2CON_bits.TOUTPS3
872 // ----- TRISA bits --------------------
875 unsigned char TRISA0:1;
876 unsigned char TRISA1:1;
877 unsigned char TRISA2:1;
878 unsigned char TRISA3:1;
879 unsigned char TRISA4:1;
880 unsigned char TRISA5:1;
885 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
887 #define TRISA0 TRISA_bits.TRISA0
888 #define TRISA1 TRISA_bits.TRISA1
889 #define TRISA2 TRISA_bits.TRISA2
890 #define TRISA3 TRISA_bits.TRISA3
891 #define TRISA4 TRISA_bits.TRISA4
892 #define TRISA5 TRISA_bits.TRISA5
894 // ----- TRISC bits --------------------
897 unsigned char TRISC0:1;
898 unsigned char TRISC1:1;
899 unsigned char TRISC2:1;
900 unsigned char TRISC3:1;
901 unsigned char TRISC4:1;
902 unsigned char TRISC5:1;
903 unsigned char TRISC6:1;
904 unsigned char TRISC7:1;
907 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
909 #define TRISC0 TRISC_bits.TRISC0
910 #define TRISC1 TRISC_bits.TRISC1
911 #define TRISC2 TRISC_bits.TRISC2
912 #define TRISC3 TRISC_bits.TRISC3
913 #define TRISC4 TRISC_bits.TRISC4
914 #define TRISC5 TRISC_bits.TRISC5
915 #define TRISC6 TRISC_bits.TRISC6
916 #define TRISC7 TRISC_bits.TRISC7
918 // ----- VRCON bits --------------------
928 unsigned char VREN:1;
931 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
933 #define VR0 VRCON_bits.VR0
934 #define VR1 VRCON_bits.VR1
935 #define VR2 VRCON_bits.VR2
936 #define VR3 VRCON_bits.VR3
937 #define VRR VRCON_bits.VRR
938 #define VREN VRCON_bits.VREN
940 // ----- WDTCON bits --------------------
943 unsigned char SWDTEN:1;
944 unsigned char WDTPS0:1;
945 unsigned char WDTPS1:1;
946 unsigned char WDTPS2:1;
947 unsigned char WDTPS3:1;
953 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
955 #define SWDTEN WDTCON_bits.SWDTEN
956 #define WDTPS0 WDTCON_bits.WDTPS0
957 #define WDTPS1 WDTCON_bits.WDTPS1
958 #define WDTPS2 WDTCON_bits.WDTPS2
959 #define WDTPS3 WDTCON_bits.WDTPS3