2 // Register Declarations for Microchip 16F684 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define TMR2_ADDR 0x0011
42 #define T2CON_ADDR 0x0012
43 #define CCPR1L_ADDR 0x0013
44 #define CCPR1H_ADDR 0x0014
45 #define CCP1CON_ADDR 0x0015
46 #define PWM1CON_ADDR 0x0016
47 #define ECCPAS_ADDR 0x0017
48 #define WDTCON_ADDR 0x0018
49 #define CMCON0_ADDR 0x0019
50 #define CMCON1_ADDR 0x001A
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PCON_ADDR 0x008E
58 #define OSCCON_ADDR 0x008F
59 #define OSCTUNE_ADDR 0x0090
60 #define ANSEL_ADDR 0x0091
61 #define PR2_ADDR 0x0092
62 #define WPU_ADDR 0x0095
63 #define WPUA_ADDR 0x0095
64 #define IOC_ADDR 0x0096
65 #define IOCA_ADDR 0x0096
66 #define VRCON_ADDR 0x0099
67 #define EEDAT_ADDR 0x009A
68 #define EEDATA_ADDR 0x009A
69 #define EEADR_ADDR 0x009B
70 #define EECON1_ADDR 0x009C
71 #define EECON2_ADDR 0x009D
72 #define ADRESL_ADDR 0x009E
73 #define ADCON1_ADDR 0x009F
76 // Memory organization.
82 // P16F684.INC Standard Header File, Version 1.03 Microchip Technology, Inc.
85 // This header file defines configurations, registers, and other useful bits of
86 // information for the PIC16F684 microcontroller. These names are taken to match
87 // the data sheets as closely as possible.
89 // Note that the processor must be selected before this file is
90 // included. The processor may be selected the following ways:
92 // 1. Command line switch:
93 // C:\ MPASM MYFILE.ASM /PIC16F684
94 // 2. LIST directive in the source file
96 // 3. Processor Type entry in the MPASM full-screen interface
98 //==========================================================================
102 //==========================================================================
103 //1.00 03/20/03 Original
104 //1.01 08/04/03 Updated CMCON1 address
105 //1.02 08/05/03 Updated names to match datasheet
106 //1.03 08/11/03 Updated ULPWUE bit name to match datasheet
107 //==========================================================================
111 //==========================================================================
114 // MESSG "Processor-header file mismatch. Verify selected processor."
117 //==========================================================================
119 // Register Definitions
121 //==========================================================================
126 //----- Register Files------------------------------------------------------
128 extern __data __at (INDF_ADDR) volatile char INDF;
129 extern __sfr __at (TMR0_ADDR) TMR0;
130 extern __data __at (PCL_ADDR) volatile char PCL;
131 extern __sfr __at (STATUS_ADDR) STATUS;
132 extern __sfr __at (FSR_ADDR) FSR;
133 extern __sfr __at (PORTA_ADDR) PORTA;
135 extern __sfr __at (PORTC_ADDR) PORTC;
137 extern __sfr __at (PCLATH_ADDR) PCLATH;
138 extern __sfr __at (INTCON_ADDR) INTCON;
139 extern __sfr __at (PIR1_ADDR) PIR1;
141 extern __sfr __at (TMR1L_ADDR) TMR1L;
142 extern __sfr __at (TMR1H_ADDR) TMR1H;
143 extern __sfr __at (T1CON_ADDR) T1CON;
144 extern __sfr __at (TMR2_ADDR) TMR2;
145 extern __sfr __at (T2CON_ADDR) T2CON;
146 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
147 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
148 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
149 extern __sfr __at (PWM1CON_ADDR) PWM1CON;
150 extern __sfr __at (ECCPAS_ADDR) ECCPAS;
151 extern __sfr __at (WDTCON_ADDR) WDTCON;
152 extern __sfr __at (CMCON0_ADDR) CMCON0;
153 extern __sfr __at (CMCON1_ADDR) CMCON1;
155 extern __sfr __at (ADRESH_ADDR) ADRESH;
156 extern __sfr __at (ADCON0_ADDR) ADCON0;
159 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
161 extern __sfr __at (TRISA_ADDR) TRISA;
162 extern __sfr __at (TRISC_ADDR) TRISC;
164 extern __sfr __at (PIE1_ADDR) PIE1;
166 extern __sfr __at (PCON_ADDR) PCON;
167 extern __sfr __at (OSCCON_ADDR) OSCCON;
168 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
169 extern __sfr __at (ANSEL_ADDR) ANSEL;
170 extern __sfr __at (PR2_ADDR) PR2;
172 extern __sfr __at (WPU_ADDR) WPU;
173 extern __sfr __at (WPUA_ADDR) WPUA;
174 extern __sfr __at (IOC_ADDR) IOC;
175 extern __sfr __at (IOCA_ADDR) IOCA;
177 extern __sfr __at (VRCON_ADDR) VRCON;
178 extern __sfr __at (EEDAT_ADDR) EEDAT;
179 extern __sfr __at (EEDATA_ADDR) EEDATA;
180 extern __sfr __at (EEADR_ADDR) EEADR;
181 extern __sfr __at (EECON1_ADDR) EECON1;
182 extern __sfr __at (EECON2_ADDR) EECON2;
183 extern __sfr __at (ADRESL_ADDR) ADRESL;
184 extern __sfr __at (ADCON1_ADDR) ADCON1;
187 //----- STATUS Bits --------------------------------------------------------
190 //----- INTCON Bits --------------------------------------------------------
193 //----- PIR1 Bits ----------------------------------------------------------
196 //----- T1CON Bits ---------------------------------------------------------
199 //----- T2CON Bits ---------------------------------------------------------
202 //----- CCP1CON Bits -------------------------------------------------------
205 //----- PWM1CON Bits -------------------------------------------------------
208 //----- ECCPAS Bits --------------------------------------------------------
211 //----- WDTCON Bits --------------------------------------------------------
214 //----- CMCON0 Bits -------------------------------------------------------
217 //----- CMCON1 Bits -------------------------------------------------------
220 //----- ADCON0 Bits --------------------------------------------------------
223 //----- OPTION Bits --------------------------------------------------------
226 //----- PIE1 Bits ----------------------------------------------------------
229 //----- PCON Bits ----------------------------------------------------------
232 //----- OSCCON Bits --------------------------------------------------------
235 //----- OSCTUNE Bits -------------------------------------------------------
238 //----- ANSEL --------------------------------------------------------------
241 //----- IOC --------------------------------------------------------------
244 //----- IOCA --------------------------------------------------------------
247 //----- VRCON Bits ---------------------------------------------------------
250 //----- EECON1 -------------------------------------------------------------
253 //----- ADCON1 -------------------------------------------------------------
256 //==========================================================================
260 //==========================================================================
263 // __BADRAM H'06', H'08'-H'09', H'0D', H'1B'-H'1D'
264 // __BADRAM H'86', H'88'-H'89', H'8D', H'93'-H'94', H'97'-H'98', H'C0'-H'EF'
266 //==========================================================================
268 // Configuration Bits
270 //==========================================================================
272 #define _FCMEN_ON 0x3FFF
273 #define _FCMEN_OFF 0x37FF
274 #define _IESO_ON 0x3FFF
275 #define _IESO_OFF 0x3BFF
276 #define _BOD_ON 0x3FFF
277 #define _BOD_NSLEEP 0x3EFF
278 #define _BOD_SBODEN 0x3DFF
279 #define _BOD_OFF 0x3CFF
280 #define _CPD_ON 0x3F7F
281 #define _CPD_OFF 0x3FFF
282 #define _CP_ON 0x3FBF
283 #define _CP_OFF 0x3FFF
284 #define _MCLRE_ON 0x3FFF
285 #define _MCLRE_OFF 0x3FDF
286 #define _PWRTE_OFF 0x3FFF
287 #define _PWRTE_ON 0x3FEF
288 #define _WDT_ON 0x3FFF
289 #define _WDT_OFF 0x3FF7
290 #define _LP_OSC 0x3FF8
291 #define _XT_OSC 0x3FF9
292 #define _HS_OSC 0x3FFA
293 #define _EC_OSC 0x3FFB
294 #define _INTRC_OSC_NOCLKOUT 0x3FFC
295 #define _INTRC_OSC_CLKOUT 0x3FFD
296 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
297 #define _EXTRC_OSC_CLKOUT 0x3FFF
298 #define _INTOSCIO 0x3FFC
299 #define _INTOSC 0x3FFD
300 #define _EXTRCIO 0x3FFE
301 #define _EXTRC 0x3FFF
305 // ----- ADCON0 bits --------------------
308 unsigned char ADON:1;
310 unsigned char CHS0:1;
311 unsigned char CHS1:1;
312 unsigned char CHS2:1;
314 unsigned char VCFG:1;
315 unsigned char ADFM:1;
319 unsigned char NOT_DONE:1;
329 unsigned char GO_DONE:1;
338 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
340 #define ADON ADCON0_bits.ADON
341 #define GO ADCON0_bits.GO
342 #define NOT_DONE ADCON0_bits.NOT_DONE
343 #define GO_DONE ADCON0_bits.GO_DONE
344 #define CHS0 ADCON0_bits.CHS0
345 #define CHS1 ADCON0_bits.CHS1
346 #define CHS2 ADCON0_bits.CHS2
347 #define VCFG ADCON0_bits.VCFG
348 #define ADFM ADCON0_bits.ADFM
350 // ----- CCP1CON bits --------------------
353 unsigned char CCP1M0:1;
354 unsigned char CCP1M1:1;
355 unsigned char CCP1M2:1;
356 unsigned char CCP1M3:1;
357 unsigned char DC1B0:1;
358 unsigned char DC1B1:1;
359 unsigned char P1M0:1;
360 unsigned char P1M1:1;
363 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
365 #define CCP1M0 CCP1CON_bits.CCP1M0
366 #define CCP1M1 CCP1CON_bits.CCP1M1
367 #define CCP1M2 CCP1CON_bits.CCP1M2
368 #define CCP1M3 CCP1CON_bits.CCP1M3
369 #define DC1B0 CCP1CON_bits.DC1B0
370 #define DC1B1 CCP1CON_bits.DC1B1
371 #define P1M0 CCP1CON_bits.P1M0
372 #define P1M1 CCP1CON_bits.P1M1
374 // ----- CMCON0 bits --------------------
381 unsigned char C1INV:1;
382 unsigned char C2INV:1;
383 unsigned char C1OUT:1;
384 unsigned char C2OUT:1;
387 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
389 #define CM0 CMCON0_bits.CM0
390 #define CM1 CMCON0_bits.CM1
391 #define CM2 CMCON0_bits.CM2
392 #define CIS CMCON0_bits.CIS
393 #define C1INV CMCON0_bits.C1INV
394 #define C2INV CMCON0_bits.C2INV
395 #define C1OUT CMCON0_bits.C1OUT
396 #define C2OUT CMCON0_bits.C2OUT
398 // ----- CMCON1 bits --------------------
401 unsigned char C2SYNC:1;
402 unsigned char T1GSS:1;
411 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
413 #define C2SYNC CMCON1_bits.C2SYNC
414 #define T1GSS CMCON1_bits.T1GSS
416 // ----- ECCPAS bits --------------------
419 unsigned char PSSBD0:1;
420 unsigned char PSSBD1:1;
421 unsigned char PSSAC0:1;
422 unsigned char PSSAC1:1;
423 unsigned char ECCPAS0:1;
424 unsigned char ECCPAS1:1;
425 unsigned char ECCPAS2:1;
426 unsigned char ECCPASE:1;
429 extern volatile __ECCPAS_bits_t __at(ECCPAS_ADDR) ECCPAS_bits;
431 #define PSSBD0 ECCPAS_bits.PSSBD0
432 #define PSSBD1 ECCPAS_bits.PSSBD1
433 #define PSSAC0 ECCPAS_bits.PSSAC0
434 #define PSSAC1 ECCPAS_bits.PSSAC1
435 #define ECCPAS0 ECCPAS_bits.ECCPAS0
436 #define ECCPAS1 ECCPAS_bits.ECCPAS1
437 #define ECCPAS2 ECCPAS_bits.ECCPAS2
438 #define ECCPASE ECCPAS_bits.ECCPASE
440 // ----- INTCON bits --------------------
443 unsigned char RAIF:1;
444 unsigned char INTF:1;
445 unsigned char T0IF:1;
446 unsigned char RAIE:1;
447 unsigned char INTE:1;
448 unsigned char T0IE:1;
449 unsigned char PEIE:1;
453 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
455 #define RAIF INTCON_bits.RAIF
456 #define INTF INTCON_bits.INTF
457 #define T0IF INTCON_bits.T0IF
458 #define RAIE INTCON_bits.RAIE
459 #define INTE INTCON_bits.INTE
460 #define T0IE INTCON_bits.T0IE
461 #define PEIE INTCON_bits.PEIE
462 #define GIE INTCON_bits.GIE
464 // ----- OPTION_REG bits --------------------
471 unsigned char T0SE:1;
472 unsigned char T0CS:1;
473 unsigned char INTEDG:1;
474 unsigned char NOT_RAPU:1;
476 } __OPTION_REG_bits_t;
477 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
479 #define PS0 OPTION_REG_bits.PS0
480 #define PS1 OPTION_REG_bits.PS1
481 #define PS2 OPTION_REG_bits.PS2
482 #define PSA OPTION_REG_bits.PSA
483 #define T0SE OPTION_REG_bits.T0SE
484 #define T0CS OPTION_REG_bits.T0CS
485 #define INTEDG OPTION_REG_bits.INTEDG
486 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
488 // ----- OSCCON bits --------------------
494 unsigned char OSTS:1;
495 unsigned char IRCF0:1;
496 unsigned char IRCF1:1;
497 unsigned char IRCF2:1;
501 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
503 #define SCS OSCCON_bits.SCS
504 #define LTS OSCCON_bits.LTS
505 #define HTS OSCCON_bits.HTS
506 #define OSTS OSCCON_bits.OSTS
507 #define IRCF0 OSCCON_bits.IRCF0
508 #define IRCF1 OSCCON_bits.IRCF1
509 #define IRCF2 OSCCON_bits.IRCF2
511 // ----- OSCTUNE bits --------------------
514 unsigned char TUN0:1;
515 unsigned char TUN1:1;
516 unsigned char TUN2:1;
517 unsigned char TUN3:1;
518 unsigned char TUN4:1;
519 unsigned char ANS5:1;
520 unsigned char ANS6:1;
521 unsigned char ANS7:1;
524 unsigned char ANS0:1;
525 unsigned char ANS1:1;
526 unsigned char ANS2:1;
527 unsigned char ANS3:1;
528 unsigned char ANS4:1;
529 unsigned char IOC5:1;
534 unsigned char IOC0:1;
535 unsigned char IOC1:1;
536 unsigned char IOC2:1;
537 unsigned char IOC3:1;
538 unsigned char IOC4:1;
539 unsigned char IOCA5:1;
544 unsigned char IOCA0:1;
545 unsigned char IOCA1:1;
546 unsigned char IOCA2:1;
547 unsigned char IOCA3:1;
548 unsigned char IOCA4:1;
554 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
556 #define TUN0 OSCTUNE_bits.TUN0
557 #define ANS0 OSCTUNE_bits.ANS0
558 #define IOC0 OSCTUNE_bits.IOC0
559 #define IOCA0 OSCTUNE_bits.IOCA0
560 #define TUN1 OSCTUNE_bits.TUN1
561 #define ANS1 OSCTUNE_bits.ANS1
562 #define IOC1 OSCTUNE_bits.IOC1
563 #define IOCA1 OSCTUNE_bits.IOCA1
564 #define TUN2 OSCTUNE_bits.TUN2
565 #define ANS2 OSCTUNE_bits.ANS2
566 #define IOC2 OSCTUNE_bits.IOC2
567 #define IOCA2 OSCTUNE_bits.IOCA2
568 #define TUN3 OSCTUNE_bits.TUN3
569 #define ANS3 OSCTUNE_bits.ANS3
570 #define IOC3 OSCTUNE_bits.IOC3
571 #define IOCA3 OSCTUNE_bits.IOCA3
572 #define TUN4 OSCTUNE_bits.TUN4
573 #define ANS4 OSCTUNE_bits.ANS4
574 #define IOC4 OSCTUNE_bits.IOC4
575 #define IOCA4 OSCTUNE_bits.IOCA4
576 #define ANS5 OSCTUNE_bits.ANS5
577 #define IOC5 OSCTUNE_bits.IOC5
578 #define IOCA5 OSCTUNE_bits.IOCA5
579 #define ANS6 OSCTUNE_bits.ANS6
580 #define ANS7 OSCTUNE_bits.ANS7
582 // ----- PCON bits --------------------
585 unsigned char NOT_BOD:1;
586 unsigned char NOT_POR:1;
589 unsigned char SBODEN:1;
590 unsigned char ULPWUE:1;
595 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
597 #define NOT_BOD PCON_bits.NOT_BOD
598 #define NOT_POR PCON_bits.NOT_POR
599 #define SBODEN PCON_bits.SBODEN
600 #define ULPWUE PCON_bits.ULPWUE
602 // ----- PIE1 bits --------------------
605 unsigned char T1IE:1;
606 unsigned char T2IE:1;
607 unsigned char OSFIE:1;
608 unsigned char C1IE:1;
609 unsigned char C2IE:1;
610 unsigned char CCP1IE:1;
611 unsigned char ADIE:1;
612 unsigned char EEIE:1;
615 unsigned char TMR1IE:1;
616 unsigned char TMR2IE:1;
625 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
627 #define T1IE PIE1_bits.T1IE
628 #define TMR1IE PIE1_bits.TMR1IE
629 #define T2IE PIE1_bits.T2IE
630 #define TMR2IE PIE1_bits.TMR2IE
631 #define OSFIE PIE1_bits.OSFIE
632 #define C1IE PIE1_bits.C1IE
633 #define C2IE PIE1_bits.C2IE
634 #define CCP1IE PIE1_bits.CCP1IE
635 #define ADIE PIE1_bits.ADIE
636 #define EEIE PIE1_bits.EEIE
638 // ----- PIR1 bits --------------------
641 unsigned char T1IF:1;
642 unsigned char T2IF:1;
643 unsigned char OSFIF:1;
644 unsigned char C1IF:1;
645 unsigned char C2IF:1;
646 unsigned char CCP1IF:1;
647 unsigned char ADIF:1;
648 unsigned char EEIF:1;
651 unsigned char TMR1IF:1;
652 unsigned char TMR2IF:1;
661 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
663 #define T1IF PIR1_bits.T1IF
664 #define TMR1IF PIR1_bits.TMR1IF
665 #define T2IF PIR1_bits.T2IF
666 #define TMR2IF PIR1_bits.TMR2IF
667 #define OSFIF PIR1_bits.OSFIF
668 #define C1IF PIR1_bits.C1IF
669 #define C2IF PIR1_bits.C2IF
670 #define CCP1IF PIR1_bits.CCP1IF
671 #define ADIF PIR1_bits.ADIF
672 #define EEIF PIR1_bits.EEIF
674 // ----- PWM1CON bits --------------------
677 unsigned char PDC0:1;
678 unsigned char PDC1:1;
679 unsigned char PDC2:1;
680 unsigned char PDC3:1;
681 unsigned char PDC4:1;
682 unsigned char PDC5:1;
683 unsigned char PDC6:1;
684 unsigned char PRSEN:1;
687 extern volatile __PWM1CON_bits_t __at(PWM1CON_ADDR) PWM1CON_bits;
689 #define PDC0 PWM1CON_bits.PDC0
690 #define PDC1 PWM1CON_bits.PDC1
691 #define PDC2 PWM1CON_bits.PDC2
692 #define PDC3 PWM1CON_bits.PDC3
693 #define PDC4 PWM1CON_bits.PDC4
694 #define PDC5 PWM1CON_bits.PDC5
695 #define PDC6 PWM1CON_bits.PDC6
696 #define PRSEN PWM1CON_bits.PRSEN
698 // ----- STATUS bits --------------------
704 unsigned char NOT_PD:1;
705 unsigned char NOT_TO:1;
711 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
713 #define C STATUS_bits.C
714 #define DC STATUS_bits.DC
715 #define Z STATUS_bits.Z
716 #define NOT_PD STATUS_bits.NOT_PD
717 #define NOT_TO STATUS_bits.NOT_TO
718 #define RP0 STATUS_bits.RP0
719 #define RP1 STATUS_bits.RP1
720 #define IRP STATUS_bits.IRP
722 // ----- T1CON bits --------------------
725 unsigned char TMR1ON:1;
726 unsigned char TMR1CS:1;
727 unsigned char NOT_T1SYNC:1;
728 unsigned char T1OSCEN:1;
729 unsigned char T1CKPS0:1;
730 unsigned char T1CKPS1:1;
731 unsigned char TMR1GE:1;
732 unsigned char T1GINV:1;
735 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
737 #define TMR1ON T1CON_bits.TMR1ON
738 #define TMR1CS T1CON_bits.TMR1CS
739 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
740 #define T1OSCEN T1CON_bits.T1OSCEN
741 #define T1CKPS0 T1CON_bits.T1CKPS0
742 #define T1CKPS1 T1CON_bits.T1CKPS1
743 #define TMR1GE T1CON_bits.TMR1GE
744 #define T1GINV T1CON_bits.T1GINV
746 // ----- T2CON bits --------------------
749 unsigned char T2CKPS0:1;
750 unsigned char T2CKPS1:1;
751 unsigned char TMR2ON:1;
752 unsigned char TOUTPS0:1;
753 unsigned char TOUTPS1:1;
754 unsigned char TOUTPS2:1;
755 unsigned char TOUTPS3:1;
759 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
761 #define T2CKPS0 T2CON_bits.T2CKPS0
762 #define T2CKPS1 T2CON_bits.T2CKPS1
763 #define TMR2ON T2CON_bits.TMR2ON
764 #define TOUTPS0 T2CON_bits.TOUTPS0
765 #define TOUTPS1 T2CON_bits.TOUTPS1
766 #define TOUTPS2 T2CON_bits.TOUTPS2
767 #define TOUTPS3 T2CON_bits.TOUTPS3
769 // ----- VRCON bits --------------------
776 unsigned char ADCS0:1;
778 unsigned char ADCS2:1;
779 unsigned char VREN:1;
784 unsigned char WREN:1;
785 unsigned char WRERR:1;
787 unsigned char ADCS1:1;
792 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
794 #define VR0 VRCON_bits.VR0
795 #define RD VRCON_bits.RD
796 #define VR1 VRCON_bits.VR1
797 #define WR VRCON_bits.WR
798 #define VR2 VRCON_bits.VR2
799 #define WREN VRCON_bits.WREN
800 #define VR3 VRCON_bits.VR3
801 #define WRERR VRCON_bits.WRERR
802 #define ADCS0 VRCON_bits.ADCS0
803 #define VRR VRCON_bits.VRR
804 #define ADCS1 VRCON_bits.ADCS1
805 #define ADCS2 VRCON_bits.ADCS2
806 #define VREN VRCON_bits.VREN
808 // ----- WDTCON bits --------------------
811 unsigned char SWDTEN:1;
812 unsigned char WDTPS0:1;
813 unsigned char WDTPS1:1;
814 unsigned char WDTPS2:1;
815 unsigned char WDTPS3:1;
821 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
823 #define SWDTEN WDTCON_bits.SWDTEN
824 #define WDTPS0 WDTCON_bits.WDTPS0
825 #define WDTPS1 WDTCON_bits.WDTPS1
826 #define WDTPS2 WDTCON_bits.WDTPS2
827 #define WDTPS3 WDTCON_bits.WDTPS3