2 // Register Declarations for Microchip 16F676 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define CMCON_ADDR 0x0019
42 #define ADRESH_ADDR 0x001E
43 #define ADCON0_ADDR 0x001F
44 #define OPTION_REG_ADDR 0x0081
45 #define TRISA_ADDR 0x0085
46 #define TRISC_ADDR 0x0087
47 #define PIE1_ADDR 0x008C
48 #define PCON_ADDR 0x008E
49 #define OSCCAL_ADDR 0x0090
50 #define ANSEL_ADDR 0x0091
51 #define WPU_ADDR 0x0095
52 #define WPUA_ADDR 0x0095
53 #define IOC_ADDR 0x0096
54 #define IOCA_ADDR 0x0096
55 #define VRCON_ADDR 0x0099
56 #define EEDATA_ADDR 0x009A
57 #define EEDAT_ADDR 0x009A
58 #define EEADR_ADDR 0x009B
59 #define EECON1_ADDR 0x009C
60 #define EECON2_ADDR 0x009D
61 #define ADRESL_ADDR 0x009E
62 #define ADCON1_ADDR 0x009F
65 // Memory organization.
71 // P16F676.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
74 // This header file defines configurations, registers, and other useful bits of
75 // information for the PIC16F676 microcontroller. These names are taken to match
76 // the data sheets as closely as possible.
78 // Note that the processor must be selected before this file is
79 // included. The processor may be selected the following ways:
81 // 1. Command line switch:
82 // C:\ MPASM MYFILE.ASM /PIC16F676
83 // 2. LIST directive in the source file
85 // 3. Processor Type entry in the MPASM full-screen interface
87 //==========================================================================
91 //==========================================================================
92 //1.00 05/13/02 Original
94 //==========================================================================
98 //==========================================================================
101 // MESSG "Processor-header file mismatch. Verify selected processor."
104 //==========================================================================
106 // Register Definitions
108 //==========================================================================
113 //----- Register Files------------------------------------------------------
115 extern __data __at (INDF_ADDR) volatile char INDF;
116 extern __sfr __at (TMR0_ADDR) TMR0;
117 extern __data __at (PCL_ADDR) volatile char PCL;
118 extern __sfr __at (STATUS_ADDR) STATUS;
119 extern __sfr __at (FSR_ADDR) FSR;
120 extern __sfr __at (PORTA_ADDR) PORTA;
122 extern __sfr __at (PORTC_ADDR) PORTC;
124 extern __sfr __at (PCLATH_ADDR) PCLATH;
125 extern __sfr __at (INTCON_ADDR) INTCON;
126 extern __sfr __at (PIR1_ADDR) PIR1;
128 extern __sfr __at (TMR1L_ADDR) TMR1L;
129 extern __sfr __at (TMR1H_ADDR) TMR1H;
130 extern __sfr __at (T1CON_ADDR) T1CON;
132 extern __sfr __at (CMCON_ADDR) CMCON;
134 extern __sfr __at (ADRESH_ADDR) ADRESH;
135 extern __sfr __at (ADCON0_ADDR) ADCON0;
138 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
140 extern __sfr __at (TRISA_ADDR) TRISA;
141 extern __sfr __at (TRISC_ADDR) TRISC;
143 extern __sfr __at (PIE1_ADDR) PIE1;
145 extern __sfr __at (PCON_ADDR) PCON;
147 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
148 extern __sfr __at (ANSEL_ADDR) ANSEL;
150 extern __sfr __at (WPU_ADDR) WPU;
151 extern __sfr __at (WPUA_ADDR) WPUA;
152 extern __sfr __at (IOC_ADDR) IOC;
153 extern __sfr __at (IOCA_ADDR) IOCA;
155 extern __sfr __at (VRCON_ADDR) VRCON;
156 extern __sfr __at (EEDATA_ADDR) EEDATA;
157 extern __sfr __at (EEDAT_ADDR) EEDAT;
158 extern __sfr __at (EEADR_ADDR) EEADR;
159 extern __sfr __at (EECON1_ADDR) EECON1;
160 extern __sfr __at (EECON2_ADDR) EECON2;
161 extern __sfr __at (ADRESL_ADDR) ADRESL;
162 extern __sfr __at (ADCON1_ADDR) ADCON1;
165 //----- STATUS Bits --------------------------------------------------------
168 //----- INTCON Bits --------------------------------------------------------
171 //----- PIR1 Bits ----------------------------------------------------------
174 //----- T1CON Bits ---------------------------------------------------------
177 //----- CMCON Bits --------------------------------------------------------
180 //----- ADCON0 Bits --------------------------------------------------------
183 //----- OPTION Bits --------------------------------------------------------
186 //----- PIE1 Bits ----------------------------------------------------------
189 //----- PCON Bits ----------------------------------------------------------
192 //----- OSCCAL Bits --------------------------------------------------------
195 //----- ANSEL --------------------------------------------------------------
198 //----- VRCON Bits ---------------------------------------------------------
201 //----- EECON1 -------------------------------------------------------------
204 //----- ADCON1 -------------------------------------------------------------
207 //==========================================================================
211 //==========================================================================
214 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F'
215 // __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'92'-H'94', H'97'-H'98', H'E0'-H'FF'
217 //==========================================================================
219 // Configuration Bits
221 //==========================================================================
224 #define _CPD_OFF 0x3FFF
226 #define _CP_OFF 0x3FFF
227 #define _BODEN 0x3FFF
228 #define _BODEN_OFF 0x3FBF
229 #define _MCLRE_ON 0x3FFF
230 #define _MCLRE_OFF 0x3FDF
231 #define _PWRTE_OFF 0x3FFF
232 #define _PWRTE_ON 0x3FEF
233 #define _WDT_ON 0x3FFF
234 #define _WDT_OFF 0x3FF7
235 #define _LP_OSC 0x3FF8
236 #define _XT_OSC 0x3FF9
237 #define _HS_OSC 0x3FFA
238 #define _EC_OSC 0x3FFB
239 #define _INTRC_OSC_NOCLKOUT 0x3FFC
240 #define _INTRC_OSC_CLKOUT 0x3FFD
241 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
242 #define _EXTRC_OSC_CLKOUT 0x3FFF
246 // ----- ADCON0 bits --------------------
249 unsigned char ADON:1;
251 unsigned char CHS0:1;
252 unsigned char CHS1:1;
253 unsigned char CHS2:1;
255 unsigned char VCFG:1;
256 unsigned char ADFM:1;
260 unsigned char NOT_DONE:1;
270 unsigned char GO_DONE:1;
279 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
281 #define ADON ADCON0_bits.ADON
282 #define GO ADCON0_bits.GO
283 #define NOT_DONE ADCON0_bits.NOT_DONE
284 #define GO_DONE ADCON0_bits.GO_DONE
285 #define CHS0 ADCON0_bits.CHS0
286 #define CHS1 ADCON0_bits.CHS1
287 #define CHS2 ADCON0_bits.CHS2
288 #define VCFG ADCON0_bits.VCFG
289 #define ADFM ADCON0_bits.ADFM
291 // ----- CMCON bits --------------------
298 unsigned char CINV:1;
300 unsigned char COUT:1;
304 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
306 #define CM0 CMCON_bits.CM0
307 #define CM1 CMCON_bits.CM1
308 #define CM2 CMCON_bits.CM2
309 #define CIS CMCON_bits.CIS
310 #define CINV CMCON_bits.CINV
311 #define COUT CMCON_bits.COUT
313 // ----- INTCON bits --------------------
316 unsigned char RAIF:1;
317 unsigned char INTF:1;
318 unsigned char T0IF:1;
319 unsigned char RAIE:1;
320 unsigned char INTE:1;
321 unsigned char T0IE:1;
322 unsigned char PEIE:1;
326 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
328 #define RAIF INTCON_bits.RAIF
329 #define INTF INTCON_bits.INTF
330 #define T0IF INTCON_bits.T0IF
331 #define RAIE INTCON_bits.RAIE
332 #define INTE INTCON_bits.INTE
333 #define T0IE INTCON_bits.T0IE
334 #define PEIE INTCON_bits.PEIE
335 #define GIE INTCON_bits.GIE
337 // ----- OPTION_REG bits --------------------
344 unsigned char T0SE:1;
345 unsigned char T0CS:1;
346 unsigned char INTEDG:1;
347 unsigned char NOT_GPPU:1;
357 unsigned char NOT_RAPU:1;
359 } __OPTION_REG_bits_t;
360 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
362 #define PS0 OPTION_REG_bits.PS0
363 #define PS1 OPTION_REG_bits.PS1
364 #define PS2 OPTION_REG_bits.PS2
365 #define PSA OPTION_REG_bits.PSA
366 #define T0SE OPTION_REG_bits.T0SE
367 #define T0CS OPTION_REG_bits.T0CS
368 #define INTEDG OPTION_REG_bits.INTEDG
369 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
370 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
372 // ----- OSCCAL bits --------------------
375 unsigned char ANS0:1;
376 unsigned char ANS1:1;
377 unsigned char CAL0:1;
378 unsigned char CAL1:1;
379 unsigned char CAL2:1;
380 unsigned char CAL3:1;
381 unsigned char CAL4:1;
382 unsigned char CAL5:1;
387 unsigned char ANS2:1;
388 unsigned char ANS3:1;
389 unsigned char ANS4:1;
390 unsigned char ANS5:1;
391 unsigned char ANS6:1;
392 unsigned char ANS7:1;
395 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
397 #define ANS0 OSCCAL_bits.ANS0
398 #define ANS1 OSCCAL_bits.ANS1
399 #define CAL0 OSCCAL_bits.CAL0
400 #define ANS2 OSCCAL_bits.ANS2
401 #define CAL1 OSCCAL_bits.CAL1
402 #define ANS3 OSCCAL_bits.ANS3
403 #define CAL2 OSCCAL_bits.CAL2
404 #define ANS4 OSCCAL_bits.ANS4
405 #define CAL3 OSCCAL_bits.CAL3
406 #define ANS5 OSCCAL_bits.ANS5
407 #define CAL4 OSCCAL_bits.CAL4
408 #define ANS6 OSCCAL_bits.ANS6
409 #define CAL5 OSCCAL_bits.CAL5
410 #define ANS7 OSCCAL_bits.ANS7
412 // ----- PCON bits --------------------
415 unsigned char NOT_BOD:1;
416 unsigned char NOT_POR:1;
425 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
427 #define NOT_BOD PCON_bits.NOT_BOD
428 #define NOT_POR PCON_bits.NOT_POR
430 // ----- PIE1 bits --------------------
433 unsigned char T1IE:1;
436 unsigned char CMIE:1;
439 unsigned char ADIE:1;
440 unsigned char EEIE:1;
443 unsigned char TMR1IE:1;
453 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
455 #define T1IE PIE1_bits.T1IE
456 #define TMR1IE PIE1_bits.TMR1IE
457 #define CMIE PIE1_bits.CMIE
458 #define ADIE PIE1_bits.ADIE
459 #define EEIE PIE1_bits.EEIE
461 // ----- PIR1 bits --------------------
464 unsigned char T1IF:1;
467 unsigned char CMIF:1;
470 unsigned char ADIF:1;
471 unsigned char EEIF:1;
474 unsigned char TMR1IF:1;
484 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
486 #define T1IF PIR1_bits.T1IF
487 #define TMR1IF PIR1_bits.TMR1IF
488 #define CMIF PIR1_bits.CMIF
489 #define ADIF PIR1_bits.ADIF
490 #define EEIF PIR1_bits.EEIF
492 // ----- STATUS bits --------------------
498 unsigned char NOT_PD:1;
499 unsigned char NOT_TO:1;
505 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
507 #define C STATUS_bits.C
508 #define DC STATUS_bits.DC
509 #define Z STATUS_bits.Z
510 #define NOT_PD STATUS_bits.NOT_PD
511 #define NOT_TO STATUS_bits.NOT_TO
512 #define RP0 STATUS_bits.RP0
513 #define RP1 STATUS_bits.RP1
514 #define IRP STATUS_bits.IRP
516 // ----- T1CON bits --------------------
519 unsigned char TMR1ON:1;
520 unsigned char TMR1CS:1;
521 unsigned char NOT_T1SYNC:1;
522 unsigned char T1OSCEN:1;
523 unsigned char T1CKPS0:1;
524 unsigned char T1CKPS1:1;
525 unsigned char TMR1GE:1;
529 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
531 #define TMR1ON T1CON_bits.TMR1ON
532 #define TMR1CS T1CON_bits.TMR1CS
533 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
534 #define T1OSCEN T1CON_bits.T1OSCEN
535 #define T1CKPS0 T1CON_bits.T1CKPS0
536 #define T1CKPS1 T1CON_bits.T1CKPS1
537 #define TMR1GE T1CON_bits.TMR1GE
539 // ----- VRCON bits --------------------
546 unsigned char ADCS0:1;
548 unsigned char ADCS2:1;
549 unsigned char VREN:1;
554 unsigned char WREN:1;
555 unsigned char WRERR:1;
557 unsigned char ADCS1:1;
562 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
564 #define VR0 VRCON_bits.VR0
565 #define RD VRCON_bits.RD
566 #define VR1 VRCON_bits.VR1
567 #define WR VRCON_bits.WR
568 #define VR2 VRCON_bits.VR2
569 #define WREN VRCON_bits.WREN
570 #define VR3 VRCON_bits.VR3
571 #define WRERR VRCON_bits.WRERR
572 #define ADCS0 VRCON_bits.ADCS0
573 #define VRR VRCON_bits.VRR
574 #define ADCS1 VRCON_bits.ADCS1
575 #define ADCS2 VRCON_bits.ADCS2
576 #define VREN VRCON_bits.VREN