2 // Register Declarations for Microchip 16F676 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define CMCON_ADDR 0x0019
42 #define ADRESH_ADDR 0x001E
43 #define ADCON0_ADDR 0x001F
44 #define OPTION_REG_ADDR 0x0081
45 #define TRISA_ADDR 0x0085
46 #define TRISC_ADDR 0x0087
47 #define PIE1_ADDR 0x008C
48 #define PCON_ADDR 0x008E
49 #define OSCCAL_ADDR 0x0090
50 #define ANSEL_ADDR 0x0091
51 #define WPU_ADDR 0x0095
52 #define WPUA_ADDR 0x0095
53 #define IOC_ADDR 0x0096
54 #define IOCA_ADDR 0x0096
55 #define VRCON_ADDR 0x0099
56 #define EEDATA_ADDR 0x009A
57 #define EEDAT_ADDR 0x009A
58 #define EEADR_ADDR 0x009B
59 #define EECON1_ADDR 0x009C
60 #define EECON2_ADDR 0x009D
61 #define ADRESL_ADDR 0x009E
62 #define ADCON1_ADDR 0x009F
65 // Memory organization.
68 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
69 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
70 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
71 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
72 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
73 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
74 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
75 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
76 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
77 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
78 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
79 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
80 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
81 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
82 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
83 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
84 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
85 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
86 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
87 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
88 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
89 #pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL
90 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
91 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
92 #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
93 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
94 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
95 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
96 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
97 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
98 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
99 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
100 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
101 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
102 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
106 // P16F676.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
109 // This header file defines configurations, registers, and other useful bits of
110 // information for the PIC16F676 microcontroller. These names are taken to match
111 // the data sheets as closely as possible.
113 // Note that the processor must be selected before this file is
114 // included. The processor may be selected the following ways:
116 // 1. Command line switch:
117 // C:\ MPASM MYFILE.ASM /PIC16F676
118 // 2. LIST directive in the source file
120 // 3. Processor Type entry in the MPASM full-screen interface
122 //==========================================================================
126 //==========================================================================
127 //1.00 05/13/02 Original
129 //==========================================================================
133 //==========================================================================
136 // MESSG "Processor-header file mismatch. Verify selected processor."
139 //==========================================================================
141 // Register Definitions
143 //==========================================================================
148 //----- Register Files------------------------------------------------------
150 extern __data __at (INDF_ADDR) volatile char INDF;
151 extern __sfr __at (TMR0_ADDR) TMR0;
152 extern __data __at (PCL_ADDR) volatile char PCL;
153 extern __sfr __at (STATUS_ADDR) STATUS;
154 extern __sfr __at (FSR_ADDR) FSR;
155 extern __sfr __at (PORTA_ADDR) PORTA;
157 extern __sfr __at (PORTC_ADDR) PORTC;
159 extern __sfr __at (PCLATH_ADDR) PCLATH;
160 extern __sfr __at (INTCON_ADDR) INTCON;
161 extern __sfr __at (PIR1_ADDR) PIR1;
163 extern __sfr __at (TMR1L_ADDR) TMR1L;
164 extern __sfr __at (TMR1H_ADDR) TMR1H;
165 extern __sfr __at (T1CON_ADDR) T1CON;
167 extern __sfr __at (CMCON_ADDR) CMCON;
169 extern __sfr __at (ADRESH_ADDR) ADRESH;
170 extern __sfr __at (ADCON0_ADDR) ADCON0;
173 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
175 extern __sfr __at (TRISA_ADDR) TRISA;
176 extern __sfr __at (TRISC_ADDR) TRISC;
178 extern __sfr __at (PIE1_ADDR) PIE1;
180 extern __sfr __at (PCON_ADDR) PCON;
182 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
183 extern __sfr __at (ANSEL_ADDR) ANSEL;
185 extern __sfr __at (WPU_ADDR) WPU;
186 extern __sfr __at (WPUA_ADDR) WPUA;
187 extern __sfr __at (IOC_ADDR) IOC;
188 extern __sfr __at (IOCA_ADDR) IOCA;
190 extern __sfr __at (VRCON_ADDR) VRCON;
191 extern __sfr __at (EEDATA_ADDR) EEDATA;
192 extern __sfr __at (EEDAT_ADDR) EEDAT;
193 extern __sfr __at (EEADR_ADDR) EEADR;
194 extern __sfr __at (EECON1_ADDR) EECON1;
195 extern __sfr __at (EECON2_ADDR) EECON2;
196 extern __sfr __at (ADRESL_ADDR) ADRESL;
197 extern __sfr __at (ADCON1_ADDR) ADCON1;
200 //----- STATUS Bits --------------------------------------------------------
203 //----- INTCON Bits --------------------------------------------------------
206 //----- PIR1 Bits ----------------------------------------------------------
209 //----- T1CON Bits ---------------------------------------------------------
212 //----- CMCON Bits --------------------------------------------------------
215 //----- ADCON0 Bits --------------------------------------------------------
218 //----- OPTION Bits --------------------------------------------------------
221 //----- PIE1 Bits ----------------------------------------------------------
224 //----- PCON Bits ----------------------------------------------------------
227 //----- OSCCAL Bits --------------------------------------------------------
230 //----- ANSEL --------------------------------------------------------------
233 //----- VRCON Bits ---------------------------------------------------------
236 //----- EECON1 -------------------------------------------------------------
239 //----- ADCON1 -------------------------------------------------------------
242 //==========================================================================
246 //==========================================================================
249 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'18', H'1A'-H'1D', H'60'-H'7F'
250 // __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'92'-H'94', H'97'-H'98', H'E0'-H'FF'
252 //==========================================================================
254 // Configuration Bits
256 //==========================================================================
259 #define _CPD_OFF 0x3FFF
261 #define _CP_OFF 0x3FFF
262 #define _BODEN 0x3FFF
263 #define _BODEN_OFF 0x3FBF
264 #define _MCLRE_ON 0x3FFF
265 #define _MCLRE_OFF 0x3FDF
266 #define _PWRTE_OFF 0x3FFF
267 #define _PWRTE_ON 0x3FEF
268 #define _WDT_ON 0x3FFF
269 #define _WDT_OFF 0x3FF7
270 #define _LP_OSC 0x3FF8
271 #define _XT_OSC 0x3FF9
272 #define _HS_OSC 0x3FFA
273 #define _EC_OSC 0x3FFB
274 #define _INTRC_OSC_NOCLKOUT 0x3FFC
275 #define _INTRC_OSC_CLKOUT 0x3FFD
276 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
277 #define _EXTRC_OSC_CLKOUT 0x3FFF
281 // ----- ADCON0 bits --------------------
284 unsigned char ADON:1;
286 unsigned char CHS0:1;
287 unsigned char CHS1:1;
288 unsigned char CHS2:1;
290 unsigned char VCFG:1;
291 unsigned char ADFM:1;
295 unsigned char NOT_DONE:1;
305 unsigned char GO_DONE:1;
314 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
316 #define ADON ADCON0_bits.ADON
317 #define GO ADCON0_bits.GO
318 #define NOT_DONE ADCON0_bits.NOT_DONE
319 #define GO_DONE ADCON0_bits.GO_DONE
320 #define CHS0 ADCON0_bits.CHS0
321 #define CHS1 ADCON0_bits.CHS1
322 #define CHS2 ADCON0_bits.CHS2
323 #define VCFG ADCON0_bits.VCFG
324 #define ADFM ADCON0_bits.ADFM
326 // ----- CMCON bits --------------------
333 unsigned char CINV:1;
335 unsigned char COUT:1;
339 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
341 #define CM0 CMCON_bits.CM0
342 #define CM1 CMCON_bits.CM1
343 #define CM2 CMCON_bits.CM2
344 #define CIS CMCON_bits.CIS
345 #define CINV CMCON_bits.CINV
346 #define COUT CMCON_bits.COUT
348 // ----- INTCON bits --------------------
351 unsigned char RAIF:1;
352 unsigned char INTF:1;
353 unsigned char T0IF:1;
354 unsigned char RAIE:1;
355 unsigned char INTE:1;
356 unsigned char T0IE:1;
357 unsigned char PEIE:1;
361 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
363 #define RAIF INTCON_bits.RAIF
364 #define INTF INTCON_bits.INTF
365 #define T0IF INTCON_bits.T0IF
366 #define RAIE INTCON_bits.RAIE
367 #define INTE INTCON_bits.INTE
368 #define T0IE INTCON_bits.T0IE
369 #define PEIE INTCON_bits.PEIE
370 #define GIE INTCON_bits.GIE
372 // ----- OPTION_REG bits --------------------
379 unsigned char T0SE:1;
380 unsigned char T0CS:1;
381 unsigned char INTEDG:1;
382 unsigned char NOT_GPPU:1;
392 unsigned char NOT_RAPU:1;
394 } __OPTION_REG_bits_t;
395 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
397 #define PS0 OPTION_REG_bits.PS0
398 #define PS1 OPTION_REG_bits.PS1
399 #define PS2 OPTION_REG_bits.PS2
400 #define PSA OPTION_REG_bits.PSA
401 #define T0SE OPTION_REG_bits.T0SE
402 #define T0CS OPTION_REG_bits.T0CS
403 #define INTEDG OPTION_REG_bits.INTEDG
404 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
405 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
407 // ----- OSCCAL bits --------------------
410 unsigned char ANS0:1;
411 unsigned char ANS1:1;
412 unsigned char CAL0:1;
413 unsigned char CAL1:1;
414 unsigned char CAL2:1;
415 unsigned char CAL3:1;
416 unsigned char CAL4:1;
417 unsigned char CAL5:1;
422 unsigned char ANS2:1;
423 unsigned char ANS3:1;
424 unsigned char ANS4:1;
425 unsigned char ANS5:1;
426 unsigned char ANS6:1;
427 unsigned char ANS7:1;
430 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
432 #define ANS0 OSCCAL_bits.ANS0
433 #define ANS1 OSCCAL_bits.ANS1
434 #define CAL0 OSCCAL_bits.CAL0
435 #define ANS2 OSCCAL_bits.ANS2
436 #define CAL1 OSCCAL_bits.CAL1
437 #define ANS3 OSCCAL_bits.ANS3
438 #define CAL2 OSCCAL_bits.CAL2
439 #define ANS4 OSCCAL_bits.ANS4
440 #define CAL3 OSCCAL_bits.CAL3
441 #define ANS5 OSCCAL_bits.ANS5
442 #define CAL4 OSCCAL_bits.CAL4
443 #define ANS6 OSCCAL_bits.ANS6
444 #define CAL5 OSCCAL_bits.CAL5
445 #define ANS7 OSCCAL_bits.ANS7
447 // ----- PCON bits --------------------
450 unsigned char NOT_BOD:1;
451 unsigned char NOT_POR:1;
460 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
462 #define NOT_BOD PCON_bits.NOT_BOD
463 #define NOT_POR PCON_bits.NOT_POR
465 // ----- PIE1 bits --------------------
468 unsigned char T1IE:1;
471 unsigned char CMIE:1;
474 unsigned char ADIE:1;
475 unsigned char EEIE:1;
478 unsigned char TMR1IE:1;
488 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
490 #define T1IE PIE1_bits.T1IE
491 #define TMR1IE PIE1_bits.TMR1IE
492 #define CMIE PIE1_bits.CMIE
493 #define ADIE PIE1_bits.ADIE
494 #define EEIE PIE1_bits.EEIE
496 // ----- PIR1 bits --------------------
499 unsigned char T1IF:1;
502 unsigned char CMIF:1;
505 unsigned char ADIF:1;
506 unsigned char EEIF:1;
509 unsigned char TMR1IF:1;
519 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
521 #define T1IF PIR1_bits.T1IF
522 #define TMR1IF PIR1_bits.TMR1IF
523 #define CMIF PIR1_bits.CMIF
524 #define ADIF PIR1_bits.ADIF
525 #define EEIF PIR1_bits.EEIF
527 // ----- STATUS bits --------------------
533 unsigned char NOT_PD:1;
534 unsigned char NOT_TO:1;
540 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
542 #define C STATUS_bits.C
543 #define DC STATUS_bits.DC
544 #define Z STATUS_bits.Z
545 #define NOT_PD STATUS_bits.NOT_PD
546 #define NOT_TO STATUS_bits.NOT_TO
547 #define RP0 STATUS_bits.RP0
548 #define RP1 STATUS_bits.RP1
549 #define IRP STATUS_bits.IRP
551 // ----- T1CON bits --------------------
554 unsigned char TMR1ON:1;
555 unsigned char TMR1CS:1;
556 unsigned char NOT_T1SYNC:1;
557 unsigned char T1OSCEN:1;
558 unsigned char T1CKPS0:1;
559 unsigned char T1CKPS1:1;
560 unsigned char TMR1GE:1;
564 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
566 #define TMR1ON T1CON_bits.TMR1ON
567 #define TMR1CS T1CON_bits.TMR1CS
568 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
569 #define T1OSCEN T1CON_bits.T1OSCEN
570 #define T1CKPS0 T1CON_bits.T1CKPS0
571 #define T1CKPS1 T1CON_bits.T1CKPS1
572 #define TMR1GE T1CON_bits.TMR1GE
574 // ----- VRCON bits --------------------
581 unsigned char ADCS0:1;
583 unsigned char ADCS2:1;
584 unsigned char VREN:1;
589 unsigned char WREN:1;
590 unsigned char WRERR:1;
592 unsigned char ADCS1:1;
597 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
599 #define VR0 VRCON_bits.VR0
600 #define RD VRCON_bits.RD
601 #define VR1 VRCON_bits.VR1
602 #define WR VRCON_bits.WR
603 #define VR2 VRCON_bits.VR2
604 #define WREN VRCON_bits.WREN
605 #define VR3 VRCON_bits.VR3
606 #define WRERR VRCON_bits.WRERR
607 #define ADCS0 VRCON_bits.ADCS0
608 #define VRR VRCON_bits.VRR
609 #define ADCS1 VRCON_bits.ADCS1
610 #define ADCS2 VRCON_bits.ADCS2
611 #define VREN VRCON_bits.VREN