2 // Register Declarations for Microchip 16F648A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define TMR2_ADDR 0x0011
42 #define T2CON_ADDR 0x0012
43 #define CCPR1L_ADDR 0x0015
44 #define CCPR1H_ADDR 0x0016
45 #define CCP1CON_ADDR 0x0017
46 #define RCSTA_ADDR 0x0018
47 #define TXREG_ADDR 0x0019
48 #define RCREG_ADDR 0x001A
49 #define CMCON_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define PIE1_ADDR 0x008C
54 #define PCON_ADDR 0x008E
55 #define PR2_ADDR 0x0092
56 #define TXSTA_ADDR 0x0098
57 #define SPBRG_ADDR 0x0099
58 #define EEDATA_ADDR 0x009A
59 #define EEADR_ADDR 0x009B
60 #define EECON1_ADDR 0x009C
61 #define EECON2_ADDR 0x009D
62 #define VRCON_ADDR 0x009F
65 // Memory organization.
71 // P16F648A.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
74 // This header file defines configurations, registers, and other useful bits of
75 // information for the PIC16F648A microcontroller. These names are taken to match
76 // the data sheets as closely as possible.
78 // Note that the processor must be selected before this file is
79 // included. The processor may be selected the following ways:
81 // 1. Command line switch:
82 // C:\ MPASM MYFILE.ASM /PIC16F648A
83 // 2. LIST directive in the source file
85 // 3. Processor Type entry in the MPASM full-screen interface
87 //==========================================================================
91 //==========================================================================
94 //1.00 14 Nov 2002 Initial Release
96 //==========================================================================
100 //==========================================================================
103 // MESSG "Processor-header file mismatch. Verify selected processor."
106 //==========================================================================
108 // Register Definitions
110 //==========================================================================
115 //----- Register Files------------------------------------------------------
117 extern __data __at (INDF_ADDR) volatile char INDF;
118 extern __sfr __at (TMR0_ADDR) TMR0;
119 extern __data __at (PCL_ADDR) volatile char PCL;
120 extern __sfr __at (STATUS_ADDR) STATUS;
121 extern __sfr __at (FSR_ADDR) FSR;
122 extern __sfr __at (PORTA_ADDR) PORTA;
123 extern __sfr __at (PORTB_ADDR) PORTB;
124 extern __sfr __at (PCLATH_ADDR) PCLATH;
125 extern __sfr __at (INTCON_ADDR) INTCON;
126 extern __sfr __at (PIR1_ADDR) PIR1;
127 extern __sfr __at (TMR1L_ADDR) TMR1L;
128 extern __sfr __at (TMR1H_ADDR) TMR1H;
129 extern __sfr __at (T1CON_ADDR) T1CON;
130 extern __sfr __at (TMR2_ADDR) TMR2;
131 extern __sfr __at (T2CON_ADDR) T2CON;
132 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
133 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
134 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
135 extern __sfr __at (RCSTA_ADDR) RCSTA;
136 extern __sfr __at (TXREG_ADDR) TXREG;
137 extern __sfr __at (RCREG_ADDR) RCREG;
138 extern __sfr __at (CMCON_ADDR) CMCON;
140 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
141 extern __sfr __at (TRISA_ADDR) TRISA;
142 extern __sfr __at (TRISB_ADDR) TRISB;
143 extern __sfr __at (PIE1_ADDR) PIE1;
144 extern __sfr __at (PCON_ADDR) PCON;
145 extern __sfr __at (PR2_ADDR) PR2;
146 extern __sfr __at (TXSTA_ADDR) TXSTA;
147 extern __sfr __at (SPBRG_ADDR) SPBRG;
148 extern __sfr __at (EEDATA_ADDR) EEDATA;
149 extern __sfr __at (EEADR_ADDR) EEADR;
150 extern __sfr __at (EECON1_ADDR) EECON1;
151 extern __sfr __at (EECON2_ADDR) EECON2;
152 extern __sfr __at (VRCON_ADDR) VRCON;
154 //----- STATUS Bits --------------------------------------------------------
157 //----- INTCON Bits --------------------------------------------------------
160 //----- PIR1 Bits ----------------------------------------------------------
163 //----- T1CON Bits ---------------------------------------------------------
165 //----- T2CON Bits ---------------------------------------------------------
167 //----- CCP1CON Bits ---------------------------------------------------------
169 //----- RCSTA Bits ---------------------------------------------------------
171 //----- CMCON Bits ---------------------------------------------------------
174 //----- OPTION Bits --------------------------------------------------------
177 //----- PIE1 Bits ----------------------------------------------------------
180 //----- PCON Bits ----------------------------------------------------------
183 //----- TXSTA Bits ----------------------------------------------------------
185 //----- EECON1 Bits ---------------------------------------------------------
187 //----- VRCON Bits ---------------------------------------------------------
190 //==========================================================================
194 //==========================================================================
197 // __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E'
198 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E'
199 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F'
200 // __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF'
202 //==========================================================================
204 // Configuration Bits
206 //==========================================================================
208 #define _BODEN_ON 0x3FFF //Backwards compatability to 16F62X
209 #define _BODEN_OFF 0x3FBF //Backwards compatability to 16F62X
210 #define _BOREN_ON 0x3FFF
211 #define _BOREN_OFF 0x3FBF
212 #define _CP_ON 0x1FFF
213 #define _CP_OFF 0x3FFF
214 #define _DATA_CP_ON 0x3EFF
215 #define _DATA_CP_OFF 0x3FFF
216 #define _PWRTE_OFF 0x3FFF
217 #define _PWRTE_ON 0x3FF7
218 #define _WDT_ON 0x3FFF
219 #define _WDT_OFF 0x3FFB
220 #define _LVP_ON 0x3FFF
221 #define _LVP_OFF 0x3F7F
222 #define _MCLRE_ON 0x3FFF
223 #define _MCLRE_OFF 0x3FDF
224 #define _RC_OSC_CLKOUT 0x3FFF
225 #define _RC_OSC_NOCLKOUT 0x3FFE
226 #define _ER_OSC_CLKOUT 0x3FFF //Backwards compatability to 16F62X
227 #define _ER_OSC_NOCLKOUT 0x3FFE //Backwards compatability to 16F62X
228 #define _INTOSC_OSC_CLKOUT 0x3FFD
229 #define _INTOSC_OSC_NOCLKOUT 0x3FFC
230 #define _INTRC_OSC_CLKOUT 0x3FFD //Backwards compatability to 16F62X
231 #define _INTRC_OSC_NOCLKOUT 0x3FFC //Backwards compatability to 16F62X
232 #define _EXTCLK_OSC 0x3FEF
233 #define _HS_OSC 0x3FEE
234 #define _XT_OSC 0x3FED
235 #define _LP_OSC 0x3FEC
239 // ----- CCP1CON bits --------------------
242 unsigned char CCP1M0:1;
243 unsigned char CCP1M1:1;
244 unsigned char CCP1M2:1;
245 unsigned char CCP1M3:1;
246 unsigned char CCP1Y:1;
247 unsigned char CCP1X:1;
252 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
254 #define CCP1M0 CCP1CON_bits.CCP1M0
255 #define CCP1M1 CCP1CON_bits.CCP1M1
256 #define CCP1M2 CCP1CON_bits.CCP1M2
257 #define CCP1M3 CCP1CON_bits.CCP1M3
258 #define CCP1Y CCP1CON_bits.CCP1Y
259 #define CCP1X CCP1CON_bits.CCP1X
261 // ----- CMCON bits --------------------
268 unsigned char C1INV:1;
269 unsigned char C2INV:1;
270 unsigned char C1OUT:1;
271 unsigned char C2OUT:1;
274 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
276 #define CM0 CMCON_bits.CM0
277 #define CM1 CMCON_bits.CM1
278 #define CM2 CMCON_bits.CM2
279 #define CIS CMCON_bits.CIS
280 #define C1INV CMCON_bits.C1INV
281 #define C2INV CMCON_bits.C2INV
282 #define C1OUT CMCON_bits.C1OUT
283 #define C2OUT CMCON_bits.C2OUT
285 // ----- EECON1 bits --------------------
290 unsigned char WREN:1;
291 unsigned char WRERR:1;
298 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
300 #define RD EECON1_bits.RD
301 #define WR EECON1_bits.WR
302 #define WREN EECON1_bits.WREN
303 #define WRERR EECON1_bits.WRERR
305 // ----- INTCON bits --------------------
308 unsigned char RBIF:1;
309 unsigned char INTF:1;
310 unsigned char T0IF:1;
311 unsigned char RBIE:1;
312 unsigned char INTE:1;
313 unsigned char T0IE:1;
314 unsigned char PEIE:1;
318 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
320 #define RBIF INTCON_bits.RBIF
321 #define INTF INTCON_bits.INTF
322 #define T0IF INTCON_bits.T0IF
323 #define RBIE INTCON_bits.RBIE
324 #define INTE INTCON_bits.INTE
325 #define T0IE INTCON_bits.T0IE
326 #define PEIE INTCON_bits.PEIE
327 #define GIE INTCON_bits.GIE
329 // ----- OPTION_REG bits --------------------
336 unsigned char T0SE:1;
337 unsigned char T0CS:1;
338 unsigned char INTEDG:1;
339 unsigned char NOT_RBPU:1;
341 } __OPTION_REG_bits_t;
342 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
344 #define PS0 OPTION_REG_bits.PS0
345 #define PS1 OPTION_REG_bits.PS1
346 #define PS2 OPTION_REG_bits.PS2
347 #define PSA OPTION_REG_bits.PSA
348 #define T0SE OPTION_REG_bits.T0SE
349 #define T0CS OPTION_REG_bits.T0CS
350 #define INTEDG OPTION_REG_bits.INTEDG
351 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
353 // ----- PCON bits --------------------
356 unsigned char NOT_BO:1;
357 unsigned char NOT_POR:1;
359 unsigned char OSCF:1;
366 unsigned char NOT_BOR:1;
376 unsigned char NOT_BOD:1;
386 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
388 #define NOT_BO PCON_bits.NOT_BO
389 #define NOT_BOR PCON_bits.NOT_BOR
390 #define NOT_BOD PCON_bits.NOT_BOD
391 #define NOT_POR PCON_bits.NOT_POR
392 #define OSCF PCON_bits.OSCF
394 // ----- PIE1 bits --------------------
397 unsigned char TMR1IE:1;
398 unsigned char TMR2IE:1;
399 unsigned char CCP1IE:1;
401 unsigned char TXIE:1;
402 unsigned char RCIE:1;
403 unsigned char CMIE:1;
404 unsigned char EEIE:1;
407 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
409 #define TMR1IE PIE1_bits.TMR1IE
410 #define TMR2IE PIE1_bits.TMR2IE
411 #define CCP1IE PIE1_bits.CCP1IE
412 #define TXIE PIE1_bits.TXIE
413 #define RCIE PIE1_bits.RCIE
414 #define CMIE PIE1_bits.CMIE
415 #define EEIE PIE1_bits.EEIE
417 // ----- PIR1 bits --------------------
420 unsigned char TMR1IF:1;
421 unsigned char TMR2IF:1;
422 unsigned char CCP1IF:1;
424 unsigned char TXIF:1;
425 unsigned char RCIF:1;
426 unsigned char CMIF:1;
427 unsigned char EEIF:1;
430 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
432 #define TMR1IF PIR1_bits.TMR1IF
433 #define TMR2IF PIR1_bits.TMR2IF
434 #define CCP1IF PIR1_bits.CCP1IF
435 #define TXIF PIR1_bits.TXIF
436 #define RCIF PIR1_bits.RCIF
437 #define CMIF PIR1_bits.CMIF
438 #define EEIF PIR1_bits.EEIF
440 // ----- RCSTA bits --------------------
443 unsigned char RX9D:1;
444 unsigned char OERR:1;
445 unsigned char FERR:1;
446 unsigned char ADEN:1;
447 unsigned char CREN:1;
448 unsigned char SREN:1;
450 unsigned char SPEN:1;
453 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
455 #define RX9D RCSTA_bits.RX9D
456 #define OERR RCSTA_bits.OERR
457 #define FERR RCSTA_bits.FERR
458 #define ADEN RCSTA_bits.ADEN
459 #define CREN RCSTA_bits.CREN
460 #define SREN RCSTA_bits.SREN
461 #define RX9 RCSTA_bits.RX9
462 #define SPEN RCSTA_bits.SPEN
464 // ----- STATUS bits --------------------
470 unsigned char NOT_PD:1;
471 unsigned char NOT_TO:1;
477 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
479 #define C STATUS_bits.C
480 #define DC STATUS_bits.DC
481 #define Z STATUS_bits.Z
482 #define NOT_PD STATUS_bits.NOT_PD
483 #define NOT_TO STATUS_bits.NOT_TO
484 #define RP0 STATUS_bits.RP0
485 #define RP1 STATUS_bits.RP1
486 #define IRP STATUS_bits.IRP
488 // ----- T1CON bits --------------------
491 unsigned char TMR1ON:1;
492 unsigned char TMR1CS:1;
493 unsigned char NOT_T1SYNC:1;
494 unsigned char T1OSCEN:1;
495 unsigned char T1CKPS0:1;
496 unsigned char T1CKPS1:1;
501 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
503 #define TMR1ON T1CON_bits.TMR1ON
504 #define TMR1CS T1CON_bits.TMR1CS
505 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
506 #define T1OSCEN T1CON_bits.T1OSCEN
507 #define T1CKPS0 T1CON_bits.T1CKPS0
508 #define T1CKPS1 T1CON_bits.T1CKPS1
510 // ----- T2CON bits --------------------
513 unsigned char T2CKPS0:1;
514 unsigned char T2CKPS1:1;
515 unsigned char TMR2ON:1;
516 unsigned char TOUTPS0:1;
517 unsigned char TOUTPS1:1;
518 unsigned char TOUTPS2:1;
519 unsigned char TOUTPS3:1;
523 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
525 #define T2CKPS0 T2CON_bits.T2CKPS0
526 #define T2CKPS1 T2CON_bits.T2CKPS1
527 #define TMR2ON T2CON_bits.TMR2ON
528 #define TOUTPS0 T2CON_bits.TOUTPS0
529 #define TOUTPS1 T2CON_bits.TOUTPS1
530 #define TOUTPS2 T2CON_bits.TOUTPS2
531 #define TOUTPS3 T2CON_bits.TOUTPS3
533 // ----- TXSTA bits --------------------
536 unsigned char TX9D:1;
537 unsigned char TRMT:1;
538 unsigned char BRGH:1;
540 unsigned char SYNC:1;
541 unsigned char TXEN:1;
543 unsigned char CSRC:1;
546 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
548 #define TX9D TXSTA_bits.TX9D
549 #define TRMT TXSTA_bits.TRMT
550 #define BRGH TXSTA_bits.BRGH
551 #define SYNC TXSTA_bits.SYNC
552 #define TXEN TXSTA_bits.TXEN
553 #define TX9 TXSTA_bits.TX9
554 #define CSRC TXSTA_bits.CSRC
556 // ----- VRCON bits --------------------
565 unsigned char VROE:1;
566 unsigned char VREN:1;
569 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
571 #define VR0 VRCON_bits.VR0
572 #define VR1 VRCON_bits.VR1
573 #define VR2 VRCON_bits.VR2
574 #define VR3 VRCON_bits.VR3
575 #define VRR VRCON_bits.VRR
576 #define VROE VRCON_bits.VROE
577 #define VREN VRCON_bits.VREN