2 // Register Declarations for Microchip 16F639 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define WDTCON_ADDR 0x0018
42 #define CMCON0_ADDR 0x0019
43 #define CMCON1_ADDR 0x001A
44 #define OPTION_REG_ADDR 0x0081
45 #define TRISA_ADDR 0x0085
46 #define TRISC_ADDR 0x0087
47 #define PIE1_ADDR 0x008C
48 #define PCON_ADDR 0x008E
49 #define OSCCON_ADDR 0x008F
50 #define OSCTUNE_ADDR 0x0090
51 #define LVDCON_ADDR 0x0094
52 #define WPUDA_ADDR 0x0095
53 #define IOCA_ADDR 0x0096
54 #define WDA_ADDR 0x0097
55 #define VRCON_ADDR 0x0099
56 #define EEDAT_ADDR 0x009A
57 #define EEDATA_ADDR 0x009A
58 #define EEADR_ADDR 0x009B
59 #define EECON1_ADDR 0x009C
60 #define EECON2_ADDR 0x009D
61 #define CRCON_ADDR 0x0110
62 #define CRDAT0_ADDR 0x0111
63 #define CRDAT1_ADDR 0x0112
64 #define CRDAT2_ADDR 0x0113
65 #define CRDAT3_ADDR 0x0114
68 // Memory organization.
71 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
72 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
73 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
74 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
75 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
76 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
77 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
78 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
79 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
80 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
81 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
82 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
83 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
84 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
85 #pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
86 #pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
87 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
88 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
89 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
90 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
91 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
92 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
93 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
94 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
95 #pragma memmap WPUDA_ADDR WPUDA_ADDR SFR 0x000 // WPUDA
96 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
97 #pragma memmap WDA_ADDR WDA_ADDR SFR 0x000 // WDA
98 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
99 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
100 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
101 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
102 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
103 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
104 #pragma memmap CRCON_ADDR CRCON_ADDR SFR 0x000 // CRCON
105 #pragma memmap CRDAT0_ADDR CRDAT0_ADDR SFR 0x000 // CRDAT0
106 #pragma memmap CRDAT1_ADDR CRDAT1_ADDR SFR 0x000 // CRDAT1
107 #pragma memmap CRDAT2_ADDR CRDAT2_ADDR SFR 0x000 // CRDAT2
108 #pragma memmap CRDAT3_ADDR CRDAT3_ADDR SFR 0x000 // CRDAT3
112 // P16F639.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
115 // This header file defines configurations, registers, and other useful bits of
116 // information for the PIC16F639 microcontroller. These names are taken to match
117 // the data sheets as closely as possible.
119 // Note that the processor must be selected before this file is
120 // included. The processor may be selected the following ways:
122 // 1. Command line switch:
123 // C:\ MPASM MYFILE.ASM /PIC16F639
124 // 2. LIST directive in the source file
126 // 3. Processor Type entry in the MPASM full-screen interface
128 //==========================================================================
132 //==========================================================================
133 //1.00 10/28/04 Original based on P16F636.INC
134 //==========================================================================
138 //==========================================================================
141 // MESSG "Processor-header file mismatch. Verify selected processor."
144 //==========================================================================
146 // Register Definitions
148 //==========================================================================
153 //----- Register Files------------------------------------------------------
155 extern __data __at (INDF_ADDR) volatile char INDF;
156 extern __sfr __at (TMR0_ADDR) TMR0;
157 extern __data __at (PCL_ADDR) volatile char PCL;
158 extern __sfr __at (STATUS_ADDR) STATUS;
159 extern __sfr __at (FSR_ADDR) FSR;
160 extern __sfr __at (PORTA_ADDR) PORTA;
162 extern __sfr __at (PORTC_ADDR) PORTC;
164 extern __sfr __at (PCLATH_ADDR) PCLATH;
165 extern __sfr __at (INTCON_ADDR) INTCON;
166 extern __sfr __at (PIR1_ADDR) PIR1;
168 extern __sfr __at (TMR1L_ADDR) TMR1L;
169 extern __sfr __at (TMR1H_ADDR) TMR1H;
170 extern __sfr __at (T1CON_ADDR) T1CON;
172 extern __sfr __at (WDTCON_ADDR) WDTCON;
173 extern __sfr __at (CMCON0_ADDR) CMCON0;
174 extern __sfr __at (CMCON1_ADDR) CMCON1;
177 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
178 extern __sfr __at (TRISA_ADDR) TRISA;
179 extern __sfr __at (TRISC_ADDR) TRISC;
180 extern __sfr __at (PIE1_ADDR) PIE1;
182 extern __sfr __at (PCON_ADDR) PCON;
183 extern __sfr __at (OSCCON_ADDR) OSCCON;
184 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
186 extern __sfr __at (LVDCON_ADDR) LVDCON;
187 extern __sfr __at (WPUDA_ADDR) WPUDA;
188 extern __sfr __at (IOCA_ADDR) IOCA;
189 extern __sfr __at (WDA_ADDR) WDA;
191 extern __sfr __at (VRCON_ADDR) VRCON;
192 extern __sfr __at (EEDAT_ADDR) EEDAT;
193 extern __sfr __at (EEDATA_ADDR) EEDATA;
194 extern __sfr __at (EEADR_ADDR) EEADR;
195 extern __sfr __at (EECON1_ADDR) EECON1;
196 extern __sfr __at (EECON2_ADDR) EECON2;
199 extern __sfr __at (CRCON_ADDR) CRCON;
200 extern __sfr __at (CRDAT0_ADDR) CRDAT0;
201 extern __sfr __at (CRDAT1_ADDR) CRDAT1;
202 extern __sfr __at (CRDAT2_ADDR) CRDAT2;
203 extern __sfr __at (CRDAT3_ADDR) CRDAT3;
205 //----- STATUS Bits --------------------------------------------------------
208 //----- INTCON Bits --------------------------------------------------------
211 //----- PIR1 Bits ----------------------------------------------------------
214 //----- T1CON Bits ---------------------------------------------------------
217 //----- WDTCON Bits --------------------------------------------------------
220 //----- CMCON0 Bits -------------------------------------------------------
223 //----- CMCON1 Bits -------------------------------------------------------
226 //----- OPTION Bits --------------------------------------------------------
229 //----- PIE1 Bits ----------------------------------------------------------
232 //----- PCON Bits ----------------------------------------------------------
235 //----- OSCCON Bits --------------------------------------------------------
238 //----- OSCTUNE Bits -------------------------------------------------------
241 //----- IOCA --------------------------------------------------------------
244 //----- EECON1 -------------------------------------------------------------
247 //----- VRCON ---------------------------------------------------------
251 //----- CRCON -------------------------------------------------------------
254 //----- LVDCON -------------------------------------------------------------
257 //----- WDA -------------------------------------------------------------
260 //----- WPUDA -------------------------------------------------------------
264 //==========================================================================
268 //==========================================================================
271 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F'
272 // __BADRAM H'86', H'88'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'C0'-H'EF'
273 // __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106', H'108'-H'109', H'186'
274 // __BADRAM H'188'-H'189', H'18C'-H'1EF'
276 //==========================================================================
278 // Configuration Bits
280 //==========================================================================
281 #define _WUREN_ON 0x2FFF
282 #define _WUREN_OFF 0x3FFF
283 #define _FCMEN_ON 0x3FFF
284 #define _FCMEN_OFF 0x37FF
285 #define _IESO_ON 0x3FFF
286 #define _IESO_OFF 0x3BFF
287 #define _BOD_ON 0x3FFF
288 #define _BOD_NSLEEP 0x3EFF
289 #define _BOD_SBODEN 0x3DFF
290 #define _BOD_OFF 0x3CFF
291 #define _CPD_ON 0x3F7F
292 #define _CPD_OFF 0x3FFF
293 #define _CP_ON 0x3FBF
294 #define _CP_OFF 0x3FFF
295 #define _MCLRE_ON 0x3FFF
296 #define _MCLRE_OFF 0x3FDF
297 #define _PWRTE_OFF 0x3FFF
298 #define _PWRTE_ON 0x3FEF
299 #define _WDT_ON 0x3FFF
300 #define _WDT_OFF 0x3FF7
301 #define _LP_OSC 0x3FF8
302 #define _XT_OSC 0x3FF9
303 #define _HS_OSC 0x3FFA
304 #define _EC_OSC 0x3FFB
305 #define _INTRC_OSC_NOCLKOUT 0x3FFC
306 #define _INTRC_OSC_CLKOUT 0x3FFD
307 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
308 #define _EXTRC_OSC_CLKOUT 0x3FFF
312 // ----- CMCON0 bits --------------------
319 unsigned char C1INV:1;
320 unsigned char C2INV:1;
321 unsigned char C1OUT:1;
322 unsigned char C2OUT:1;
325 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
327 #define CM0 CMCON0_bits.CM0
328 #define CM1 CMCON0_bits.CM1
329 #define CM2 CMCON0_bits.CM2
330 #define CIS CMCON0_bits.CIS
331 #define C1INV CMCON0_bits.C1INV
332 #define C2INV CMCON0_bits.C2INV
333 #define C1OUT CMCON0_bits.C1OUT
334 #define C2OUT CMCON0_bits.C2OUT
336 // ----- CMCON1 bits --------------------
339 unsigned char C2SYNC:1;
340 unsigned char T1GSS:1;
349 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
351 #define C2SYNC CMCON1_bits.C2SYNC
352 #define T1GSS CMCON1_bits.T1GSS
354 // ----- INTCON bits --------------------
357 unsigned char RAIF:1;
358 unsigned char INTF:1;
359 unsigned char T0IF:1;
360 unsigned char RAIE:1;
361 unsigned char INTE:1;
362 unsigned char T0IE:1;
363 unsigned char PEIE:1;
367 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
369 #define RAIF INTCON_bits.RAIF
370 #define INTF INTCON_bits.INTF
371 #define T0IF INTCON_bits.T0IF
372 #define RAIE INTCON_bits.RAIE
373 #define INTE INTCON_bits.INTE
374 #define T0IE INTCON_bits.T0IE
375 #define PEIE INTCON_bits.PEIE
376 #define GIE INTCON_bits.GIE
378 // ----- OPTION_REG bits --------------------
385 unsigned char T0SE:1;
386 unsigned char T0CS:1;
387 unsigned char INTEDG:1;
388 unsigned char NOT_RAPU:1;
390 } __OPTION_REG_bits_t;
391 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
393 #define PS0 OPTION_REG_bits.PS0
394 #define PS1 OPTION_REG_bits.PS1
395 #define PS2 OPTION_REG_bits.PS2
396 #define PSA OPTION_REG_bits.PSA
397 #define T0SE OPTION_REG_bits.T0SE
398 #define T0CS OPTION_REG_bits.T0CS
399 #define INTEDG OPTION_REG_bits.INTEDG
400 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
402 // ----- OSCCON bits --------------------
408 unsigned char OSTS:1;
409 unsigned char IRCF0:1;
410 unsigned char IRCF1:1;
411 unsigned char IRCF2:1;
415 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
417 #define SCS OSCCON_bits.SCS
418 #define LTS OSCCON_bits.LTS
419 #define HTS OSCCON_bits.HTS
420 #define OSTS OSCCON_bits.OSTS
421 #define IRCF0 OSCCON_bits.IRCF0
422 #define IRCF1 OSCCON_bits.IRCF1
423 #define IRCF2 OSCCON_bits.IRCF2
425 // ----- OSCTUNE bits --------------------
428 unsigned char TUN0:1;
429 unsigned char TUN1:1;
430 unsigned char TUN2:1;
431 unsigned char TUN3:1;
432 unsigned char TUN4:1;
433 unsigned char IOCA5:1;
434 unsigned char ENC_DEC:1;
435 unsigned char VREN:1;
438 unsigned char IOCA0:1;
439 unsigned char IOCA1:1;
440 unsigned char IOCA2:1;
441 unsigned char IOCA3:1;
442 unsigned char IOCA4:1;
450 unsigned char WREN:1;
451 unsigned char WRERR:1;
452 unsigned char LVDEN:1;
453 unsigned char IRVST:1;
462 unsigned char WDA4:1;
463 unsigned char WDA5:1;
468 unsigned char CRREG0:1;
469 unsigned char CRREG1:1;
470 unsigned char LVDL2:1;
472 unsigned char WPUDA4:1;
473 unsigned char WPUDA5:1;
478 unsigned char LVDL0:1;
479 unsigned char LVDL1:1;
480 unsigned char WDA2:1;
488 unsigned char WDA0:1;
489 unsigned char WDA1:1;
490 unsigned char WPUDA2:1;
498 unsigned char WPUDA0:1;
499 unsigned char WPUDA1:1;
508 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
510 #define TUN0 OSCTUNE_bits.TUN0
511 #define IOCA0 OSCTUNE_bits.IOCA0
512 #define RD OSCTUNE_bits.RD
513 #define VR0 OSCTUNE_bits.VR0
514 #define CRREG0 OSCTUNE_bits.CRREG0
515 #define LVDL0 OSCTUNE_bits.LVDL0
516 #define WDA0 OSCTUNE_bits.WDA0
517 #define WPUDA0 OSCTUNE_bits.WPUDA0
518 #define TUN1 OSCTUNE_bits.TUN1
519 #define IOCA1 OSCTUNE_bits.IOCA1
520 #define WR OSCTUNE_bits.WR
521 #define VR1 OSCTUNE_bits.VR1
522 #define CRREG1 OSCTUNE_bits.CRREG1
523 #define LVDL1 OSCTUNE_bits.LVDL1
524 #define WDA1 OSCTUNE_bits.WDA1
525 #define WPUDA1 OSCTUNE_bits.WPUDA1
526 #define TUN2 OSCTUNE_bits.TUN2
527 #define IOCA2 OSCTUNE_bits.IOCA2
528 #define WREN OSCTUNE_bits.WREN
529 #define VR2 OSCTUNE_bits.VR2
530 #define LVDL2 OSCTUNE_bits.LVDL2
531 #define WDA2 OSCTUNE_bits.WDA2
532 #define WPUDA2 OSCTUNE_bits.WPUDA2
533 #define TUN3 OSCTUNE_bits.TUN3
534 #define IOCA3 OSCTUNE_bits.IOCA3
535 #define WRERR OSCTUNE_bits.WRERR
536 #define VR3 OSCTUNE_bits.VR3
537 #define TUN4 OSCTUNE_bits.TUN4
538 #define IOCA4 OSCTUNE_bits.IOCA4
539 #define LVDEN OSCTUNE_bits.LVDEN
540 #define WDA4 OSCTUNE_bits.WDA4
541 #define WPUDA4 OSCTUNE_bits.WPUDA4
542 #define IOCA5 OSCTUNE_bits.IOCA5
543 #define VRR OSCTUNE_bits.VRR
544 #define IRVST OSCTUNE_bits.IRVST
545 #define WDA5 OSCTUNE_bits.WDA5
546 #define WPUDA5 OSCTUNE_bits.WPUDA5
547 #define ENC_DEC OSCTUNE_bits.ENC_DEC
548 #define VREN OSCTUNE_bits.VREN
549 #define GO OSCTUNE_bits.GO
551 // ----- PCON bits --------------------
554 unsigned char NOT_BOD:1;
555 unsigned char NOT_POR:1;
557 unsigned char NOT_WUR:1;
558 unsigned char SBODEN:1;
559 unsigned char ULPWUE:1;
564 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
566 #define NOT_BOD PCON_bits.NOT_BOD
567 #define NOT_POR PCON_bits.NOT_POR
568 #define NOT_WUR PCON_bits.NOT_WUR
569 #define SBODEN PCON_bits.SBODEN
570 #define ULPWUE PCON_bits.ULPWUE
572 // ----- PIE1 bits --------------------
575 unsigned char TMR1IE:1;
577 unsigned char OSFIE:1;
578 unsigned char C1IE:1;
579 unsigned char C2IE:1;
580 unsigned char CRIE:1;
581 unsigned char LVDIE:1;
582 unsigned char EEIE:1;
585 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
587 #define TMR1IE PIE1_bits.TMR1IE
588 #define OSFIE PIE1_bits.OSFIE
589 #define C1IE PIE1_bits.C1IE
590 #define C2IE PIE1_bits.C2IE
591 #define CRIE PIE1_bits.CRIE
592 #define LVDIE PIE1_bits.LVDIE
593 #define EEIE PIE1_bits.EEIE
595 // ----- PIR1 bits --------------------
598 unsigned char TMR1IF:1;
600 unsigned char OSFIF:1;
601 unsigned char C1IF:1;
602 unsigned char C2IF:1;
603 unsigned char CRIF:1;
604 unsigned char LVDIF:1;
605 unsigned char EEIF:1;
608 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
610 #define TMR1IF PIR1_bits.TMR1IF
611 #define OSFIF PIR1_bits.OSFIF
612 #define C1IF PIR1_bits.C1IF
613 #define C2IF PIR1_bits.C2IF
614 #define CRIF PIR1_bits.CRIF
615 #define LVDIF PIR1_bits.LVDIF
616 #define EEIF PIR1_bits.EEIF
618 // ----- STATUS bits --------------------
624 unsigned char NOT_PD:1;
625 unsigned char NOT_TO:1;
631 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
633 #define C STATUS_bits.C
634 #define DC STATUS_bits.DC
635 #define Z STATUS_bits.Z
636 #define NOT_PD STATUS_bits.NOT_PD
637 #define NOT_TO STATUS_bits.NOT_TO
638 #define RP0 STATUS_bits.RP0
639 #define RP1 STATUS_bits.RP1
640 #define IRP STATUS_bits.IRP
642 // ----- T1CON bits --------------------
645 unsigned char TMR1ON:1;
646 unsigned char TMR1CS:1;
647 unsigned char NOT_T1SYNC:1;
648 unsigned char T1OSCEN:1;
649 unsigned char T1CKPS0:1;
650 unsigned char T1CKPS1:1;
651 unsigned char TMR1GE:1;
652 unsigned char T1GINV:1;
655 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
657 #define TMR1ON T1CON_bits.TMR1ON
658 #define TMR1CS T1CON_bits.TMR1CS
659 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
660 #define T1OSCEN T1CON_bits.T1OSCEN
661 #define T1CKPS0 T1CON_bits.T1CKPS0
662 #define T1CKPS1 T1CON_bits.T1CKPS1
663 #define TMR1GE T1CON_bits.TMR1GE
664 #define T1GINV T1CON_bits.T1GINV
666 // ----- WDTCON bits --------------------
669 unsigned char SWDTEN:1;
670 unsigned char WDTPS0:1;
671 unsigned char WDTPS1:1;
672 unsigned char WDTPS2:1;
673 unsigned char WDTPS3:1;
679 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
681 #define SWDTEN WDTCON_bits.SWDTEN
682 #define WDTPS0 WDTCON_bits.WDTPS0
683 #define WDTPS1 WDTCON_bits.WDTPS1
684 #define WDTPS2 WDTCON_bits.WDTPS2
685 #define WDTPS3 WDTCON_bits.WDTPS3