2 // Register Declarations for Microchip 16F639 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define WDTCON_ADDR 0x0018
42 #define CMCON0_ADDR 0x0019
43 #define CMCON1_ADDR 0x001A
44 #define OPTION_REG_ADDR 0x0081
45 #define TRISA_ADDR 0x0085
46 #define TRISC_ADDR 0x0087
47 #define PIE1_ADDR 0x008C
48 #define PCON_ADDR 0x008E
49 #define OSCCON_ADDR 0x008F
50 #define OSCTUNE_ADDR 0x0090
51 #define LVDCON_ADDR 0x0094
52 #define WPUDA_ADDR 0x0095
53 #define IOCA_ADDR 0x0096
54 #define WDA_ADDR 0x0097
55 #define VRCON_ADDR 0x0099
56 #define EEDAT_ADDR 0x009A
57 #define EEDATA_ADDR 0x009A
58 #define EEADR_ADDR 0x009B
59 #define EECON1_ADDR 0x009C
60 #define EECON2_ADDR 0x009D
61 #define CRCON_ADDR 0x0110
62 #define CRDAT0_ADDR 0x0111
63 #define CRDAT1_ADDR 0x0112
64 #define CRDAT2_ADDR 0x0113
65 #define CRDAT3_ADDR 0x0114
68 // Memory organization.
74 // P16F639.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
77 // This header file defines configurations, registers, and other useful bits of
78 // information for the PIC16F639 microcontroller. These names are taken to match
79 // the data sheets as closely as possible.
81 // Note that the processor must be selected before this file is
82 // included. The processor may be selected the following ways:
84 // 1. Command line switch:
85 // C:\ MPASM MYFILE.ASM /PIC16F639
86 // 2. LIST directive in the source file
88 // 3. Processor Type entry in the MPASM full-screen interface
90 //==========================================================================
94 //==========================================================================
95 //1.00 10/28/04 Original based on P16F636.INC
96 //==========================================================================
100 //==========================================================================
103 // MESSG "Processor-header file mismatch. Verify selected processor."
106 //==========================================================================
108 // Register Definitions
110 //==========================================================================
115 //----- Register Files------------------------------------------------------
117 extern __sfr __at (INDF_ADDR) INDF;
118 extern __sfr __at (TMR0_ADDR) TMR0;
119 extern __sfr __at (PCL_ADDR) PCL;
120 extern __sfr __at (STATUS_ADDR) STATUS;
121 extern __sfr __at (FSR_ADDR) FSR;
122 extern __sfr __at (PORTA_ADDR) PORTA;
124 extern __sfr __at (PORTC_ADDR) PORTC;
126 extern __sfr __at (PCLATH_ADDR) PCLATH;
127 extern __sfr __at (INTCON_ADDR) INTCON;
128 extern __sfr __at (PIR1_ADDR) PIR1;
130 extern __sfr __at (TMR1L_ADDR) TMR1L;
131 extern __sfr __at (TMR1H_ADDR) TMR1H;
132 extern __sfr __at (T1CON_ADDR) T1CON;
134 extern __sfr __at (WDTCON_ADDR) WDTCON;
135 extern __sfr __at (CMCON0_ADDR) CMCON0;
136 extern __sfr __at (CMCON1_ADDR) CMCON1;
139 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
141 extern __sfr __at (TRISA_ADDR) TRISA;
142 extern __sfr __at (TRISC_ADDR) TRISC;
144 extern __sfr __at (PIE1_ADDR) PIE1;
146 extern __sfr __at (PCON_ADDR) PCON;
147 extern __sfr __at (OSCCON_ADDR) OSCCON;
148 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
150 extern __sfr __at (LVDCON_ADDR) LVDCON;
151 extern __sfr __at (WPUDA_ADDR) WPUDA;
152 extern __sfr __at (IOCA_ADDR) IOCA;
153 extern __sfr __at (WDA_ADDR) WDA;
155 extern __sfr __at (VRCON_ADDR) VRCON;
156 extern __sfr __at (EEDAT_ADDR) EEDAT;
157 extern __sfr __at (EEDATA_ADDR) EEDATA;
158 extern __sfr __at (EEADR_ADDR) EEADR;
159 extern __sfr __at (EECON1_ADDR) EECON1;
160 extern __sfr __at (EECON2_ADDR) EECON2;
163 extern __sfr __at (CRCON_ADDR) CRCON;
164 extern __sfr __at (CRDAT0_ADDR) CRDAT0;
165 extern __sfr __at (CRDAT1_ADDR) CRDAT1;
166 extern __sfr __at (CRDAT2_ADDR) CRDAT2;
167 extern __sfr __at (CRDAT3_ADDR) CRDAT3;
169 //----- STATUS Bits --------------------------------------------------------
172 //----- INTCON Bits --------------------------------------------------------
175 //----- PIR1 Bits ----------------------------------------------------------
178 //----- T1CON Bits ---------------------------------------------------------
181 //----- WDTCON Bits --------------------------------------------------------
184 //----- CMCON0 Bits -------------------------------------------------------
187 //----- CMCON1 Bits -------------------------------------------------------
190 //----- OPTION Bits --------------------------------------------------------
193 //----- PIE1 Bits ----------------------------------------------------------
196 //----- PCON Bits ----------------------------------------------------------
199 //----- OSCCON Bits --------------------------------------------------------
202 //----- OSCTUNE Bits -------------------------------------------------------
205 //----- IOCA --------------------------------------------------------------
208 //----- EECON1 -------------------------------------------------------------
211 //----- VRCON ---------------------------------------------------------
215 //----- CRCON -------------------------------------------------------------
218 //----- LVDCON -------------------------------------------------------------
221 //----- WDA -------------------------------------------------------------
224 //----- WPUDA -------------------------------------------------------------
228 //==========================================================================
232 //==========================================================================
235 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F'
236 // __BADRAM H'86', H'88'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'C0'-H'EF'
237 // __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106', H'108'-H'109', H'186'
238 // __BADRAM H'188'-H'189', H'18C'-H'1EF'
240 //==========================================================================
242 // Configuration Bits
244 //==========================================================================
245 #define _WUREN_ON 0x2FFF
246 #define _WUREN_OFF 0x3FFF
247 #define _FCMEN_ON 0x3FFF
248 #define _FCMEN_OFF 0x37FF
249 #define _IESO_ON 0x3FFF
250 #define _IESO_OFF 0x3BFF
251 #define _BOD_ON 0x3FFF
252 #define _BOD_NSLEEP 0x3EFF
253 #define _BOD_SBODEN 0x3DFF
254 #define _BOD_OFF 0x3CFF
255 #define _CPD_ON 0x3F7F
256 #define _CPD_OFF 0x3FFF
257 #define _CP_ON 0x3FBF
258 #define _CP_OFF 0x3FFF
259 #define _MCLRE_ON 0x3FFF
260 #define _MCLRE_OFF 0x3FDF
261 #define _PWRTE_OFF 0x3FFF
262 #define _PWRTE_ON 0x3FEF
263 #define _WDT_ON 0x3FFF
264 #define _WDT_OFF 0x3FF7
265 #define _LP_OSC 0x3FF8
266 #define _XT_OSC 0x3FF9
267 #define _HS_OSC 0x3FFA
268 #define _EC_OSC 0x3FFB
269 #define _INTRC_OSC_NOCLKOUT 0x3FFC
270 #define _INTRC_OSC_CLKOUT 0x3FFD
271 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
272 #define _EXTRC_OSC_CLKOUT 0x3FFF
276 // ----- CMCON0 bits --------------------
283 unsigned char C1INV:1;
284 unsigned char C2INV:1;
285 unsigned char C1OUT:1;
286 unsigned char C2OUT:1;
289 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
291 #define CM0 CMCON0_bits.CM0
292 #define CM1 CMCON0_bits.CM1
293 #define CM2 CMCON0_bits.CM2
294 #define CIS CMCON0_bits.CIS
295 #define C1INV CMCON0_bits.C1INV
296 #define C2INV CMCON0_bits.C2INV
297 #define C1OUT CMCON0_bits.C1OUT
298 #define C2OUT CMCON0_bits.C2OUT
300 // ----- CMCON1 bits --------------------
303 unsigned char C2SYNC:1;
304 unsigned char T1GSS:1;
313 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
315 #define C2SYNC CMCON1_bits.C2SYNC
316 #define T1GSS CMCON1_bits.T1GSS
318 // ----- CRCON bits --------------------
321 unsigned char CRREG0:1;
322 unsigned char CRREG1:1;
327 unsigned char ENC_DEC:1;
331 extern volatile __CRCON_bits_t __at(CRCON_ADDR) CRCON_bits;
333 #define CRREG0 CRCON_bits.CRREG0
334 #define CRREG1 CRCON_bits.CRREG1
335 #define ENC_DEC CRCON_bits.ENC_DEC
336 #define GO CRCON_bits.GO
338 // ----- EECON1 bits --------------------
343 unsigned char WREN:1;
344 unsigned char WRERR:1;
351 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
353 #define RD EECON1_bits.RD
354 #define WR EECON1_bits.WR
355 #define WREN EECON1_bits.WREN
356 #define WRERR EECON1_bits.WRERR
358 // ----- INTCON bits --------------------
361 unsigned char RAIF:1;
362 unsigned char INTF:1;
363 unsigned char T0IF:1;
364 unsigned char RAIE:1;
365 unsigned char INTE:1;
366 unsigned char T0IE:1;
367 unsigned char PEIE:1;
371 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
373 #define RAIF INTCON_bits.RAIF
374 #define INTF INTCON_bits.INTF
375 #define T0IF INTCON_bits.T0IF
376 #define RAIE INTCON_bits.RAIE
377 #define INTE INTCON_bits.INTE
378 #define T0IE INTCON_bits.T0IE
379 #define PEIE INTCON_bits.PEIE
380 #define GIE INTCON_bits.GIE
382 // ----- IOCA bits --------------------
385 unsigned char IOCA0:1;
386 unsigned char IOCA1:1;
387 unsigned char IOCA2:1;
388 unsigned char IOCA3:1;
389 unsigned char IOCA4:1;
390 unsigned char IOCA5:1;
395 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
397 #define IOCA0 IOCA_bits.IOCA0
398 #define IOCA1 IOCA_bits.IOCA1
399 #define IOCA2 IOCA_bits.IOCA2
400 #define IOCA3 IOCA_bits.IOCA3
401 #define IOCA4 IOCA_bits.IOCA4
402 #define IOCA5 IOCA_bits.IOCA5
404 // ----- LVDCON bits --------------------
407 unsigned char LVDL0:1;
408 unsigned char LVDL1:1;
409 unsigned char LVDL2:1;
411 unsigned char LVDEN:1;
412 unsigned char IRVST:1;
417 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
419 #define LVDL0 LVDCON_bits.LVDL0
420 #define LVDL1 LVDCON_bits.LVDL1
421 #define LVDL2 LVDCON_bits.LVDL2
422 #define LVDEN LVDCON_bits.LVDEN
423 #define IRVST LVDCON_bits.IRVST
425 // ----- OPTION_REG bits --------------------
432 unsigned char T0SE:1;
433 unsigned char T0CS:1;
434 unsigned char INTEDG:1;
435 unsigned char NOT_RAPU:1;
437 } __OPTION_REG_bits_t;
438 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
440 #define PS0 OPTION_REG_bits.PS0
441 #define PS1 OPTION_REG_bits.PS1
442 #define PS2 OPTION_REG_bits.PS2
443 #define PSA OPTION_REG_bits.PSA
444 #define T0SE OPTION_REG_bits.T0SE
445 #define T0CS OPTION_REG_bits.T0CS
446 #define INTEDG OPTION_REG_bits.INTEDG
447 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
449 // ----- OSCCON bits --------------------
455 unsigned char OSTS:1;
456 unsigned char IRCF0:1;
457 unsigned char IRCF1:1;
458 unsigned char IRCF2:1;
462 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
464 #define SCS OSCCON_bits.SCS
465 #define LTS OSCCON_bits.LTS
466 #define HTS OSCCON_bits.HTS
467 #define OSTS OSCCON_bits.OSTS
468 #define IRCF0 OSCCON_bits.IRCF0
469 #define IRCF1 OSCCON_bits.IRCF1
470 #define IRCF2 OSCCON_bits.IRCF2
472 // ----- OSCTUNE bits --------------------
475 unsigned char TUN0:1;
476 unsigned char TUN1:1;
477 unsigned char TUN2:1;
478 unsigned char TUN3:1;
479 unsigned char TUN4:1;
485 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
487 #define TUN0 OSCTUNE_bits.TUN0
488 #define TUN1 OSCTUNE_bits.TUN1
489 #define TUN2 OSCTUNE_bits.TUN2
490 #define TUN3 OSCTUNE_bits.TUN3
491 #define TUN4 OSCTUNE_bits.TUN4
493 // ----- PCON bits --------------------
496 unsigned char NOT_BOD:1;
497 unsigned char NOT_POR:1;
499 unsigned char NOT_WUR:1;
500 unsigned char SBODEN:1;
501 unsigned char ULPWUE:1;
506 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
508 #define NOT_BOD PCON_bits.NOT_BOD
509 #define NOT_POR PCON_bits.NOT_POR
510 #define NOT_WUR PCON_bits.NOT_WUR
511 #define SBODEN PCON_bits.SBODEN
512 #define ULPWUE PCON_bits.ULPWUE
514 // ----- PIE1 bits --------------------
517 unsigned char TMR1IE:1;
519 unsigned char OSFIE:1;
520 unsigned char C1IE:1;
521 unsigned char C2IE:1;
522 unsigned char CRIE:1;
523 unsigned char LVDIE:1;
524 unsigned char EEIE:1;
527 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
529 #define TMR1IE PIE1_bits.TMR1IE
530 #define OSFIE PIE1_bits.OSFIE
531 #define C1IE PIE1_bits.C1IE
532 #define C2IE PIE1_bits.C2IE
533 #define CRIE PIE1_bits.CRIE
534 #define LVDIE PIE1_bits.LVDIE
535 #define EEIE PIE1_bits.EEIE
537 // ----- PIR1 bits --------------------
540 unsigned char TMR1IF:1;
542 unsigned char OSFIF:1;
543 unsigned char C1IF:1;
544 unsigned char C2IF:1;
545 unsigned char CRIF:1;
546 unsigned char LVDIF:1;
547 unsigned char EEIF:1;
550 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
552 #define TMR1IF PIR1_bits.TMR1IF
553 #define OSFIF PIR1_bits.OSFIF
554 #define C1IF PIR1_bits.C1IF
555 #define C2IF PIR1_bits.C2IF
556 #define CRIF PIR1_bits.CRIF
557 #define LVDIF PIR1_bits.LVDIF
558 #define EEIF PIR1_bits.EEIF
560 // ----- PORTA bits --------------------
573 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
575 #define RA0 PORTA_bits.RA0
576 #define RA1 PORTA_bits.RA1
577 #define RA2 PORTA_bits.RA2
578 #define RA3 PORTA_bits.RA3
579 #define RA4 PORTA_bits.RA4
580 #define RA5 PORTA_bits.RA5
582 // ----- PORTC bits --------------------
595 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
597 #define RC0 PORTC_bits.RC0
598 #define RC1 PORTC_bits.RC1
599 #define RC2 PORTC_bits.RC2
600 #define RC3 PORTC_bits.RC3
601 #define RC4 PORTC_bits.RC4
602 #define RC5 PORTC_bits.RC5
603 #define RC6 PORTC_bits.RC6
604 #define RC7 PORTC_bits.RC7
606 // ----- STATUS bits --------------------
612 unsigned char NOT_PD:1;
613 unsigned char NOT_TO:1;
619 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
621 #define C STATUS_bits.C
622 #define DC STATUS_bits.DC
623 #define Z STATUS_bits.Z
624 #define NOT_PD STATUS_bits.NOT_PD
625 #define NOT_TO STATUS_bits.NOT_TO
626 #define RP0 STATUS_bits.RP0
627 #define RP1 STATUS_bits.RP1
628 #define IRP STATUS_bits.IRP
630 // ----- T1CON bits --------------------
633 unsigned char TMR1ON:1;
634 unsigned char TMR1CS:1;
635 unsigned char NOT_T1SYNC:1;
636 unsigned char T1OSCEN:1;
637 unsigned char T1CKPS0:1;
638 unsigned char T1CKPS1:1;
639 unsigned char TMR1GE:1;
640 unsigned char T1GINV:1;
643 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
645 #define TMR1ON T1CON_bits.TMR1ON
646 #define TMR1CS T1CON_bits.TMR1CS
647 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
648 #define T1OSCEN T1CON_bits.T1OSCEN
649 #define T1CKPS0 T1CON_bits.T1CKPS0
650 #define T1CKPS1 T1CON_bits.T1CKPS1
651 #define TMR1GE T1CON_bits.TMR1GE
652 #define T1GINV T1CON_bits.T1GINV
654 // ----- TRISA bits --------------------
657 unsigned char TRISA0:1;
658 unsigned char TRISA1:1;
659 unsigned char TRISA2:1;
660 unsigned char TRISA3:1;
661 unsigned char TRISA4:1;
662 unsigned char TRISA5:1;
667 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
669 #define TRISA0 TRISA_bits.TRISA0
670 #define TRISA1 TRISA_bits.TRISA1
671 #define TRISA2 TRISA_bits.TRISA2
672 #define TRISA3 TRISA_bits.TRISA3
673 #define TRISA4 TRISA_bits.TRISA4
674 #define TRISA5 TRISA_bits.TRISA5
676 // ----- TRISC bits --------------------
679 unsigned char TRISC0:1;
680 unsigned char TRISC1:1;
681 unsigned char TRISC2:1;
682 unsigned char TRISC3:1;
683 unsigned char TRISC4:1;
684 unsigned char TRISC5:1;
685 unsigned char TRISC6:1;
686 unsigned char TRISC7:1;
689 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
691 #define TRISC0 TRISC_bits.TRISC0
692 #define TRISC1 TRISC_bits.TRISC1
693 #define TRISC2 TRISC_bits.TRISC2
694 #define TRISC3 TRISC_bits.TRISC3
695 #define TRISC4 TRISC_bits.TRISC4
696 #define TRISC5 TRISC_bits.TRISC5
697 #define TRISC6 TRISC_bits.TRISC6
698 #define TRISC7 TRISC_bits.TRISC7
700 // ----- VRCON bits --------------------
710 unsigned char VREN:1;
713 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
715 #define VR0 VRCON_bits.VR0
716 #define VR1 VRCON_bits.VR1
717 #define VR2 VRCON_bits.VR2
718 #define VR3 VRCON_bits.VR3
719 #define VRR VRCON_bits.VRR
720 #define VREN VRCON_bits.VREN
722 // ----- WDA bits --------------------
725 unsigned char WDA0:1;
726 unsigned char WDA1:1;
727 unsigned char WDA2:1;
729 unsigned char WDA4:1;
730 unsigned char WDA5:1;
735 extern volatile __WDA_bits_t __at(WDA_ADDR) WDA_bits;
737 #define WDA0 WDA_bits.WDA0
738 #define WDA1 WDA_bits.WDA1
739 #define WDA2 WDA_bits.WDA2
740 #define WDA4 WDA_bits.WDA4
741 #define WDA5 WDA_bits.WDA5
743 // ----- WDTCON bits --------------------
746 unsigned char SWDTEN:1;
747 unsigned char WDTPS0:1;
748 unsigned char WDTPS1:1;
749 unsigned char WDTPS2:1;
750 unsigned char WDTPS3:1;
756 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
758 #define SWDTEN WDTCON_bits.SWDTEN
759 #define WDTPS0 WDTCON_bits.WDTPS0
760 #define WDTPS1 WDTCON_bits.WDTPS1
761 #define WDTPS2 WDTCON_bits.WDTPS2
762 #define WDTPS3 WDTCON_bits.WDTPS3
764 // ----- WPUDA bits --------------------
767 unsigned char WPUDA0:1;
768 unsigned char WPUDA1:1;
769 unsigned char WPUDA2:1;
771 unsigned char WPUDA4:1;
772 unsigned char WPUDA5:1;
777 extern volatile __WPUDA_bits_t __at(WPUDA_ADDR) WPUDA_bits;
779 #define WPUDA0 WPUDA_bits.WPUDA0
780 #define WPUDA1 WPUDA_bits.WPUDA1
781 #define WPUDA2 WPUDA_bits.WPUDA2
782 #define WPUDA4 WPUDA_bits.WPUDA4
783 #define WPUDA5 WPUDA_bits.WPUDA5