2 // Register Declarations for Microchip 16F636 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define WDTCON_ADDR 0x0018
42 #define CMCON0_ADDR 0x0019
43 #define CMCON1_ADDR 0x001A
44 #define OPTION_REG_ADDR 0x0081
45 #define TRISA_ADDR 0x0085
46 #define TRISC_ADDR 0x0087
47 #define PIE1_ADDR 0x008C
48 #define PCON_ADDR 0x008E
49 #define OSCCON_ADDR 0x008F
50 #define OSCTUNE_ADDR 0x0090
51 #define LVDCON_ADDR 0x0094
52 #define WPUDA_ADDR 0x0095
53 #define IOCA_ADDR 0x0096
54 #define WDA_ADDR 0x0097
55 #define VRCON_ADDR 0x0099
56 #define EEDAT_ADDR 0x009A
57 #define EEDATA_ADDR 0x009A
58 #define EEADR_ADDR 0x009B
59 #define EECON1_ADDR 0x009C
60 #define EECON2_ADDR 0x009D
61 #define CRCON_ADDR 0x0110
62 #define CRDAT0_ADDR 0x0111
63 #define CRDAT1_ADDR 0x0112
64 #define CRDAT2_ADDR 0x0113
65 #define CRDAT3_ADDR 0x0114
68 // Memory organization.
71 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
72 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
73 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
74 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
75 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
76 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
77 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
78 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
79 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
80 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
81 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
82 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
83 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
84 #pragma memmap WDTCON_ADDR WDTCON_ADDR SFR 0x000 // WDTCON
85 #pragma memmap CMCON0_ADDR CMCON0_ADDR SFR 0x000 // CMCON0
86 #pragma memmap CMCON1_ADDR CMCON1_ADDR SFR 0x000 // CMCON1
87 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
88 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
89 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
90 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
91 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
92 #pragma memmap OSCCON_ADDR OSCCON_ADDR SFR 0x000 // OSCCON
93 #pragma memmap OSCTUNE_ADDR OSCTUNE_ADDR SFR 0x000 // OSCTUNE
94 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
95 #pragma memmap WPUDA_ADDR WPUDA_ADDR SFR 0x000 // WPUDA
96 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
97 #pragma memmap WDA_ADDR WDA_ADDR SFR 0x000 // WDA
98 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
99 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
100 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
101 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
102 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
103 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
104 #pragma memmap CRCON_ADDR CRCON_ADDR SFR 0x000 // CRCON
105 #pragma memmap CRDAT0_ADDR CRDAT0_ADDR SFR 0x000 // CRDAT0
106 #pragma memmap CRDAT1_ADDR CRDAT1_ADDR SFR 0x000 // CRDAT1
107 #pragma memmap CRDAT2_ADDR CRDAT2_ADDR SFR 0x000 // CRDAT2
108 #pragma memmap CRDAT3_ADDR CRDAT3_ADDR SFR 0x000 // CRDAT3
112 // P16F636.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
115 // This header file defines configurations, registers, and other useful bits of
116 // information for the PIC16F636 microcontroller. These names are taken to match
117 // the data sheets as closely as possible.
119 // Note that the processor must be selected before this file is
120 // included. The processor may be selected the following ways:
122 // 1. Command line switch:
123 // C:\ MPASM MYFILE.ASM /PIC16F636
124 // 2. LIST directive in the source file
126 // 3. Processor Type entry in the MPASM full-screen interface
128 //==========================================================================
132 //==========================================================================
133 //1.00 12/07/03 Original
134 //1.10 04/19/04 Update to match first release datasheet --kjd
135 //1.20 06/07/04 Update and correct badram definitions --kjd
136 //==========================================================================
140 //==========================================================================
143 // MESSG "Processor-header file mismatch. Verify selected processor."
146 //==========================================================================
148 // Register Definitions
150 //==========================================================================
155 //----- Register Files------------------------------------------------------
157 extern __data __at (INDF_ADDR) volatile char INDF;
158 extern __sfr __at (TMR0_ADDR) TMR0;
159 extern __data __at (PCL_ADDR) volatile char PCL;
160 extern __sfr __at (STATUS_ADDR) STATUS;
161 extern __sfr __at (FSR_ADDR) FSR;
162 extern __sfr __at (PORTA_ADDR) PORTA;
164 extern __sfr __at (PORTC_ADDR) PORTC;
166 extern __sfr __at (PCLATH_ADDR) PCLATH;
167 extern __sfr __at (INTCON_ADDR) INTCON;
168 extern __sfr __at (PIR1_ADDR) PIR1;
170 extern __sfr __at (TMR1L_ADDR) TMR1L;
171 extern __sfr __at (TMR1H_ADDR) TMR1H;
172 extern __sfr __at (T1CON_ADDR) T1CON;
174 extern __sfr __at (WDTCON_ADDR) WDTCON;
175 extern __sfr __at (CMCON0_ADDR) CMCON0;
176 extern __sfr __at (CMCON1_ADDR) CMCON1;
179 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
181 extern __sfr __at (TRISA_ADDR) TRISA;
182 extern __sfr __at (TRISC_ADDR) TRISC;
184 extern __sfr __at (PIE1_ADDR) PIE1;
186 extern __sfr __at (PCON_ADDR) PCON;
187 extern __sfr __at (OSCCON_ADDR) OSCCON;
188 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
190 extern __sfr __at (LVDCON_ADDR) LVDCON;
191 extern __sfr __at (WPUDA_ADDR) WPUDA;
192 extern __sfr __at (IOCA_ADDR) IOCA;
193 extern __sfr __at (WDA_ADDR) WDA;
195 extern __sfr __at (VRCON_ADDR) VRCON;
196 extern __sfr __at (EEDAT_ADDR) EEDAT;
197 extern __sfr __at (EEDATA_ADDR) EEDATA;
198 extern __sfr __at (EEADR_ADDR) EEADR;
199 extern __sfr __at (EECON1_ADDR) EECON1;
200 extern __sfr __at (EECON2_ADDR) EECON2;
203 extern __sfr __at (CRCON_ADDR) CRCON;
204 extern __sfr __at (CRDAT0_ADDR) CRDAT0;
205 extern __sfr __at (CRDAT1_ADDR) CRDAT1;
206 extern __sfr __at (CRDAT2_ADDR) CRDAT2;
207 extern __sfr __at (CRDAT3_ADDR) CRDAT3;
209 //----- STATUS Bits --------------------------------------------------------
212 //----- INTCON Bits --------------------------------------------------------
215 //----- PIR1 Bits ----------------------------------------------------------
218 //----- T1CON Bits ---------------------------------------------------------
221 //----- WDTCON Bits --------------------------------------------------------
224 //----- CMCON0 Bits -------------------------------------------------------
227 //----- CMCON1 Bits -------------------------------------------------------
230 //----- OPTION Bits --------------------------------------------------------
233 //----- PIE1 Bits ----------------------------------------------------------
236 //----- PCON Bits ----------------------------------------------------------
239 //----- OSCCON Bits --------------------------------------------------------
242 //----- OSCTUNE Bits -------------------------------------------------------
245 //----- IOCA --------------------------------------------------------------
248 //----- EECON1 -------------------------------------------------------------
251 //----- VRCON ---------------------------------------------------------
255 //----- CRCON -------------------------------------------------------------
258 //----- LVDCON -------------------------------------------------------------
261 //----- WDA -------------------------------------------------------------
264 //----- WPUDA -------------------------------------------------------------
268 //==========================================================================
272 //==========================================================================
275 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F'
276 // __BADRAM H'86', H'88'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'C0'-H'EF'
277 // __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106', H'108'-H'109', H'186'
278 // __BADRAM H'188'-H'189', H'18C'-H'1EF'
280 //==========================================================================
282 // Configuration Bits
284 //==========================================================================
285 #define _WUREN_ON 0x2FFF
286 #define _WUREN_OFF 0x3FFF
287 #define _FCMEN_ON 0x3FFF
288 #define _FCMEN_OFF 0x37FF
289 #define _IESO_ON 0x3FFF
290 #define _IESO_OFF 0x3BFF
291 #define _BOD_ON 0x3FFF
292 #define _BOD_NSLEEP 0x3EFF
293 #define _BOD_SBODEN 0x3DFF
294 #define _BOD_OFF 0x3CFF
295 #define _CPD_ON 0x3F7F
296 #define _CPD_OFF 0x3FFF
297 #define _CP_ON 0x3FBF
298 #define _CP_OFF 0x3FFF
299 #define _MCLRE_ON 0x3FFF
300 #define _MCLRE_OFF 0x3FDF
301 #define _PWRTE_OFF 0x3FFF
302 #define _PWRTE_ON 0x3FEF
303 #define _WDT_ON 0x3FFF
304 #define _WDT_OFF 0x3FF7
305 #define _LP_OSC 0x3FF8
306 #define _XT_OSC 0x3FF9
307 #define _HS_OSC 0x3FFA
308 #define _EC_OSC 0x3FFB
309 #define _INTRC_OSC_NOCLKOUT 0x3FFC
310 #define _INTRC_OSC_CLKOUT 0x3FFD
311 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
312 #define _EXTRC_OSC_CLKOUT 0x3FFF
316 // ----- CMCON0 bits --------------------
323 unsigned char C1INV:1;
324 unsigned char C2INV:1;
325 unsigned char C1OUT:1;
326 unsigned char C2OUT:1;
329 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
331 #define CM0 CMCON0_bits.CM0
332 #define CM1 CMCON0_bits.CM1
333 #define CM2 CMCON0_bits.CM2
334 #define CIS CMCON0_bits.CIS
335 #define C1INV CMCON0_bits.C1INV
336 #define C2INV CMCON0_bits.C2INV
337 #define C1OUT CMCON0_bits.C1OUT
338 #define C2OUT CMCON0_bits.C2OUT
340 // ----- CMCON1 bits --------------------
343 unsigned char C2SYNC:1;
344 unsigned char T1GSS:1;
353 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
355 #define C2SYNC CMCON1_bits.C2SYNC
356 #define T1GSS CMCON1_bits.T1GSS
358 // ----- INTCON bits --------------------
361 unsigned char RAIF:1;
362 unsigned char INTF:1;
363 unsigned char T0IF:1;
364 unsigned char RAIE:1;
365 unsigned char INTE:1;
366 unsigned char T0IE:1;
367 unsigned char PEIE:1;
371 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
373 #define RAIF INTCON_bits.RAIF
374 #define INTF INTCON_bits.INTF
375 #define T0IF INTCON_bits.T0IF
376 #define RAIE INTCON_bits.RAIE
377 #define INTE INTCON_bits.INTE
378 #define T0IE INTCON_bits.T0IE
379 #define PEIE INTCON_bits.PEIE
380 #define GIE INTCON_bits.GIE
382 // ----- OPTION_REG bits --------------------
389 unsigned char T0SE:1;
390 unsigned char T0CS:1;
391 unsigned char INTEDG:1;
392 unsigned char NOT_RAPU:1;
394 } __OPTION_REG_bits_t;
395 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
397 #define PS0 OPTION_REG_bits.PS0
398 #define PS1 OPTION_REG_bits.PS1
399 #define PS2 OPTION_REG_bits.PS2
400 #define PSA OPTION_REG_bits.PSA
401 #define T0SE OPTION_REG_bits.T0SE
402 #define T0CS OPTION_REG_bits.T0CS
403 #define INTEDG OPTION_REG_bits.INTEDG
404 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
406 // ----- OSCCON bits --------------------
412 unsigned char OSTS:1;
413 unsigned char IRCF0:1;
414 unsigned char IRCF1:1;
415 unsigned char IRCF2:1;
419 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
421 #define SCS OSCCON_bits.SCS
422 #define LTS OSCCON_bits.LTS
423 #define HTS OSCCON_bits.HTS
424 #define OSTS OSCCON_bits.OSTS
425 #define IRCF0 OSCCON_bits.IRCF0
426 #define IRCF1 OSCCON_bits.IRCF1
427 #define IRCF2 OSCCON_bits.IRCF2
429 // ----- OSCTUNE bits --------------------
432 unsigned char TUN0:1;
433 unsigned char TUN1:1;
434 unsigned char TUN2:1;
435 unsigned char TUN3:1;
436 unsigned char TUN4:1;
437 unsigned char IOCA5:1;
438 unsigned char ENC_DEC:1;
439 unsigned char VREN:1;
442 unsigned char IOCA0:1;
443 unsigned char IOCA1:1;
444 unsigned char IOCA2:1;
445 unsigned char IOCA3:1;
446 unsigned char IOCA4:1;
454 unsigned char WREN:1;
455 unsigned char WRERR:1;
456 unsigned char LVDEN:1;
457 unsigned char IRVST:1;
466 unsigned char WDA4:1;
467 unsigned char WDA5:1;
472 unsigned char CRREG0:1;
473 unsigned char CRREG1:1;
474 unsigned char LVDL2:1;
476 unsigned char WPUDA4:1;
477 unsigned char WPUDA5:1;
482 unsigned char LVDL0:1;
483 unsigned char LVDL1:1;
484 unsigned char WDA2:1;
492 unsigned char WDA0:1;
493 unsigned char WDA1:1;
494 unsigned char WPUDA2:1;
502 unsigned char WPUDA0:1;
503 unsigned char WPUDA1:1;
512 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
514 #define TUN0 OSCTUNE_bits.TUN0
515 #define IOCA0 OSCTUNE_bits.IOCA0
516 #define RD OSCTUNE_bits.RD
517 #define VR0 OSCTUNE_bits.VR0
518 #define CRREG0 OSCTUNE_bits.CRREG0
519 #define LVDL0 OSCTUNE_bits.LVDL0
520 #define WDA0 OSCTUNE_bits.WDA0
521 #define WPUDA0 OSCTUNE_bits.WPUDA0
522 #define TUN1 OSCTUNE_bits.TUN1
523 #define IOCA1 OSCTUNE_bits.IOCA1
524 #define WR OSCTUNE_bits.WR
525 #define VR1 OSCTUNE_bits.VR1
526 #define CRREG1 OSCTUNE_bits.CRREG1
527 #define LVDL1 OSCTUNE_bits.LVDL1
528 #define WDA1 OSCTUNE_bits.WDA1
529 #define WPUDA1 OSCTUNE_bits.WPUDA1
530 #define TUN2 OSCTUNE_bits.TUN2
531 #define IOCA2 OSCTUNE_bits.IOCA2
532 #define WREN OSCTUNE_bits.WREN
533 #define VR2 OSCTUNE_bits.VR2
534 #define LVDL2 OSCTUNE_bits.LVDL2
535 #define WDA2 OSCTUNE_bits.WDA2
536 #define WPUDA2 OSCTUNE_bits.WPUDA2
537 #define TUN3 OSCTUNE_bits.TUN3
538 #define IOCA3 OSCTUNE_bits.IOCA3
539 #define WRERR OSCTUNE_bits.WRERR
540 #define VR3 OSCTUNE_bits.VR3
541 #define TUN4 OSCTUNE_bits.TUN4
542 #define IOCA4 OSCTUNE_bits.IOCA4
543 #define LVDEN OSCTUNE_bits.LVDEN
544 #define WDA4 OSCTUNE_bits.WDA4
545 #define WPUDA4 OSCTUNE_bits.WPUDA4
546 #define IOCA5 OSCTUNE_bits.IOCA5
547 #define VRR OSCTUNE_bits.VRR
548 #define IRVST OSCTUNE_bits.IRVST
549 #define WDA5 OSCTUNE_bits.WDA5
550 #define WPUDA5 OSCTUNE_bits.WPUDA5
551 #define ENC_DEC OSCTUNE_bits.ENC_DEC
552 #define VREN OSCTUNE_bits.VREN
553 #define GO OSCTUNE_bits.GO
555 // ----- PCON bits --------------------
558 unsigned char NOT_BOD:1;
559 unsigned char NOT_POR:1;
561 unsigned char NOT_WUR:1;
562 unsigned char SBODEN:1;
563 unsigned char ULPWUE:1;
568 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
570 #define NOT_BOD PCON_bits.NOT_BOD
571 #define NOT_POR PCON_bits.NOT_POR
572 #define NOT_WUR PCON_bits.NOT_WUR
573 #define SBODEN PCON_bits.SBODEN
574 #define ULPWUE PCON_bits.ULPWUE
576 // ----- PIE1 bits --------------------
579 unsigned char TMR1IE:1;
581 unsigned char OSFIE:1;
582 unsigned char C1IE:1;
583 unsigned char C2IE:1;
584 unsigned char CRIE:1;
585 unsigned char LVDIE:1;
586 unsigned char EEIE:1;
589 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
591 #define TMR1IE PIE1_bits.TMR1IE
592 #define OSFIE PIE1_bits.OSFIE
593 #define C1IE PIE1_bits.C1IE
594 #define C2IE PIE1_bits.C2IE
595 #define CRIE PIE1_bits.CRIE
596 #define LVDIE PIE1_bits.LVDIE
597 #define EEIE PIE1_bits.EEIE
599 // ----- PIR1 bits --------------------
602 unsigned char TMR1IF:1;
604 unsigned char OSFIF:1;
605 unsigned char C1IF:1;
606 unsigned char C2IF:1;
607 unsigned char CRIF:1;
608 unsigned char LVDIF:1;
609 unsigned char EEIF:1;
612 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
614 #define TMR1IF PIR1_bits.TMR1IF
615 #define OSFIF PIR1_bits.OSFIF
616 #define C1IF PIR1_bits.C1IF
617 #define C2IF PIR1_bits.C2IF
618 #define CRIF PIR1_bits.CRIF
619 #define LVDIF PIR1_bits.LVDIF
620 #define EEIF PIR1_bits.EEIF
622 // ----- STATUS bits --------------------
628 unsigned char NOT_PD:1;
629 unsigned char NOT_TO:1;
635 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
637 #define C STATUS_bits.C
638 #define DC STATUS_bits.DC
639 #define Z STATUS_bits.Z
640 #define NOT_PD STATUS_bits.NOT_PD
641 #define NOT_TO STATUS_bits.NOT_TO
642 #define RP0 STATUS_bits.RP0
643 #define RP1 STATUS_bits.RP1
644 #define IRP STATUS_bits.IRP
646 // ----- T1CON bits --------------------
649 unsigned char TMR1ON:1;
650 unsigned char TMR1CS:1;
651 unsigned char NOT_T1SYNC:1;
652 unsigned char T1OSCEN:1;
653 unsigned char T1CKPS0:1;
654 unsigned char T1CKPS1:1;
655 unsigned char TMR1GE:1;
656 unsigned char T1GINV:1;
659 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
661 #define TMR1ON T1CON_bits.TMR1ON
662 #define TMR1CS T1CON_bits.TMR1CS
663 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
664 #define T1OSCEN T1CON_bits.T1OSCEN
665 #define T1CKPS0 T1CON_bits.T1CKPS0
666 #define T1CKPS1 T1CON_bits.T1CKPS1
667 #define TMR1GE T1CON_bits.TMR1GE
668 #define T1GINV T1CON_bits.T1GINV
670 // ----- WDTCON bits --------------------
673 unsigned char SWDTEN:1;
674 unsigned char WDTPS0:1;
675 unsigned char WDTPS1:1;
676 unsigned char WDTPS2:1;
677 unsigned char WDTPS3:1;
683 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
685 #define SWDTEN WDTCON_bits.SWDTEN
686 #define WDTPS0 WDTCON_bits.WDTPS0
687 #define WDTPS1 WDTCON_bits.WDTPS1
688 #define WDTPS2 WDTCON_bits.WDTPS2
689 #define WDTPS3 WDTCON_bits.WDTPS3