2 // Register Declarations for Microchip 16F636 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define WDTCON_ADDR 0x0018
42 #define CMCON0_ADDR 0x0019
43 #define CMCON1_ADDR 0x001A
44 #define OPTION_REG_ADDR 0x0081
45 #define TRISA_ADDR 0x0085
46 #define TRISC_ADDR 0x0087
47 #define PIE1_ADDR 0x008C
48 #define PCON_ADDR 0x008E
49 #define OSCCON_ADDR 0x008F
50 #define OSCTUNE_ADDR 0x0090
51 #define LVDCON_ADDR 0x0094
52 #define WPUDA_ADDR 0x0095
53 #define IOCA_ADDR 0x0096
54 #define WDA_ADDR 0x0097
55 #define VRCON_ADDR 0x0099
56 #define EEDAT_ADDR 0x009A
57 #define EEDATA_ADDR 0x009A
58 #define EEADR_ADDR 0x009B
59 #define EECON1_ADDR 0x009C
60 #define EECON2_ADDR 0x009D
61 #define CRCON_ADDR 0x0110
62 #define CRDAT0_ADDR 0x0111
63 #define CRDAT1_ADDR 0x0112
64 #define CRDAT2_ADDR 0x0113
65 #define CRDAT3_ADDR 0x0114
68 // Memory organization.
74 // P16F636.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
77 // This header file defines configurations, registers, and other useful bits of
78 // information for the PIC16F636 microcontroller. These names are taken to match
79 // the data sheets as closely as possible.
81 // Note that the processor must be selected before this file is
82 // included. The processor may be selected the following ways:
84 // 1. Command line switch:
85 // C:\ MPASM MYFILE.ASM /PIC16F636
86 // 2. LIST directive in the source file
88 // 3. Processor Type entry in the MPASM full-screen interface
90 //==========================================================================
94 //==========================================================================
95 //1.00 12/07/03 Original
96 //1.10 04/19/04 Update to match first release datasheet --kjd
97 //1.20 06/07/04 Update and correct badram definitions --kjd
98 //==========================================================================
102 //==========================================================================
105 // MESSG "Processor-header file mismatch. Verify selected processor."
108 //==========================================================================
110 // Register Definitions
112 //==========================================================================
117 //----- Register Files------------------------------------------------------
119 extern __sfr __at (INDF_ADDR) INDF;
120 extern __sfr __at (TMR0_ADDR) TMR0;
121 extern __sfr __at (PCL_ADDR) PCL;
122 extern __sfr __at (STATUS_ADDR) STATUS;
123 extern __sfr __at (FSR_ADDR) FSR;
124 extern __sfr __at (PORTA_ADDR) PORTA;
126 extern __sfr __at (PORTC_ADDR) PORTC;
128 extern __sfr __at (PCLATH_ADDR) PCLATH;
129 extern __sfr __at (INTCON_ADDR) INTCON;
130 extern __sfr __at (PIR1_ADDR) PIR1;
132 extern __sfr __at (TMR1L_ADDR) TMR1L;
133 extern __sfr __at (TMR1H_ADDR) TMR1H;
134 extern __sfr __at (T1CON_ADDR) T1CON;
136 extern __sfr __at (WDTCON_ADDR) WDTCON;
137 extern __sfr __at (CMCON0_ADDR) CMCON0;
138 extern __sfr __at (CMCON1_ADDR) CMCON1;
141 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
143 extern __sfr __at (TRISA_ADDR) TRISA;
144 extern __sfr __at (TRISC_ADDR) TRISC;
146 extern __sfr __at (PIE1_ADDR) PIE1;
148 extern __sfr __at (PCON_ADDR) PCON;
149 extern __sfr __at (OSCCON_ADDR) OSCCON;
150 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
152 extern __sfr __at (LVDCON_ADDR) LVDCON;
153 extern __sfr __at (WPUDA_ADDR) WPUDA;
154 extern __sfr __at (IOCA_ADDR) IOCA;
155 extern __sfr __at (WDA_ADDR) WDA;
157 extern __sfr __at (VRCON_ADDR) VRCON;
158 extern __sfr __at (EEDAT_ADDR) EEDAT;
159 extern __sfr __at (EEDATA_ADDR) EEDATA;
160 extern __sfr __at (EEADR_ADDR) EEADR;
161 extern __sfr __at (EECON1_ADDR) EECON1;
162 extern __sfr __at (EECON2_ADDR) EECON2;
165 extern __sfr __at (CRCON_ADDR) CRCON;
166 extern __sfr __at (CRDAT0_ADDR) CRDAT0;
167 extern __sfr __at (CRDAT1_ADDR) CRDAT1;
168 extern __sfr __at (CRDAT2_ADDR) CRDAT2;
169 extern __sfr __at (CRDAT3_ADDR) CRDAT3;
171 //----- STATUS Bits --------------------------------------------------------
174 //----- INTCON Bits --------------------------------------------------------
177 //----- PIR1 Bits ----------------------------------------------------------
180 //----- T1CON Bits ---------------------------------------------------------
183 //----- WDTCON Bits --------------------------------------------------------
186 //----- CMCON0 Bits -------------------------------------------------------
189 //----- CMCON1 Bits -------------------------------------------------------
192 //----- OPTION Bits --------------------------------------------------------
195 //----- PIE1 Bits ----------------------------------------------------------
198 //----- PCON Bits ----------------------------------------------------------
201 //----- OSCCON Bits --------------------------------------------------------
204 //----- OSCTUNE Bits -------------------------------------------------------
207 //----- IOCA --------------------------------------------------------------
210 //----- EECON1 -------------------------------------------------------------
213 //----- VRCON ---------------------------------------------------------
217 //----- CRCON -------------------------------------------------------------
220 //----- LVDCON -------------------------------------------------------------
223 //----- WDA -------------------------------------------------------------
226 //----- WPUDA -------------------------------------------------------------
230 //==========================================================================
234 //==========================================================================
237 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F'
238 // __BADRAM H'86', H'88'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'C0'-H'EF'
239 // __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106', H'108'-H'109', H'186'
240 // __BADRAM H'188'-H'189', H'18C'-H'1EF'
242 //==========================================================================
244 // Configuration Bits
246 //==========================================================================
247 #define _WUREN_ON 0x2FFF
248 #define _WUREN_OFF 0x3FFF
249 #define _FCMEN_ON 0x3FFF
250 #define _FCMEN_OFF 0x37FF
251 #define _IESO_ON 0x3FFF
252 #define _IESO_OFF 0x3BFF
253 #define _BOD_ON 0x3FFF
254 #define _BOD_NSLEEP 0x3EFF
255 #define _BOD_SBODEN 0x3DFF
256 #define _BOD_OFF 0x3CFF
257 #define _CPD_ON 0x3F7F
258 #define _CPD_OFF 0x3FFF
259 #define _CP_ON 0x3FBF
260 #define _CP_OFF 0x3FFF
261 #define _MCLRE_ON 0x3FFF
262 #define _MCLRE_OFF 0x3FDF
263 #define _PWRTE_OFF 0x3FFF
264 #define _PWRTE_ON 0x3FEF
265 #define _WDT_ON 0x3FFF
266 #define _WDT_OFF 0x3FF7
267 #define _LP_OSC 0x3FF8
268 #define _XT_OSC 0x3FF9
269 #define _HS_OSC 0x3FFA
270 #define _EC_OSC 0x3FFB
271 #define _INTRC_OSC_NOCLKOUT 0x3FFC
272 #define _INTRC_OSC_CLKOUT 0x3FFD
273 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
274 #define _EXTRC_OSC_CLKOUT 0x3FFF
278 // ----- CMCON0 bits --------------------
285 unsigned char C1INV:1;
286 unsigned char C2INV:1;
287 unsigned char C1OUT:1;
288 unsigned char C2OUT:1;
291 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
293 #ifndef NO_BIT_DEFINES
294 #define CM0 CMCON0_bits.CM0
295 #define CM1 CMCON0_bits.CM1
296 #define CM2 CMCON0_bits.CM2
297 #define CIS CMCON0_bits.CIS
298 #define C1INV CMCON0_bits.C1INV
299 #define C2INV CMCON0_bits.C2INV
300 #define C1OUT CMCON0_bits.C1OUT
301 #define C2OUT CMCON0_bits.C2OUT
302 #endif /* NO_BIT_DEFINES */
304 // ----- CMCON1 bits --------------------
307 unsigned char C2SYNC:1;
308 unsigned char T1GSS:1;
317 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
319 #ifndef NO_BIT_DEFINES
320 #define C2SYNC CMCON1_bits.C2SYNC
321 #define T1GSS CMCON1_bits.T1GSS
322 #endif /* NO_BIT_DEFINES */
324 // ----- CRCON bits --------------------
327 unsigned char CRREG0:1;
328 unsigned char CRREG1:1;
333 unsigned char ENC_DEC:1;
337 extern volatile __CRCON_bits_t __at(CRCON_ADDR) CRCON_bits;
339 #ifndef NO_BIT_DEFINES
340 #define CRREG0 CRCON_bits.CRREG0
341 #define CRREG1 CRCON_bits.CRREG1
342 #define ENC_DEC CRCON_bits.ENC_DEC
343 #define GO CRCON_bits.GO
344 #endif /* NO_BIT_DEFINES */
346 // ----- EECON1 bits --------------------
351 unsigned char WREN:1;
352 unsigned char WRERR:1;
359 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
361 #ifndef NO_BIT_DEFINES
362 #define RD EECON1_bits.RD
363 #define WR EECON1_bits.WR
364 #define WREN EECON1_bits.WREN
365 #define WRERR EECON1_bits.WRERR
366 #endif /* NO_BIT_DEFINES */
368 // ----- INTCON bits --------------------
371 unsigned char RAIF:1;
372 unsigned char INTF:1;
373 unsigned char T0IF:1;
374 unsigned char RAIE:1;
375 unsigned char INTE:1;
376 unsigned char T0IE:1;
377 unsigned char PEIE:1;
381 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
383 #ifndef NO_BIT_DEFINES
384 #define RAIF INTCON_bits.RAIF
385 #define INTF INTCON_bits.INTF
386 #define T0IF INTCON_bits.T0IF
387 #define RAIE INTCON_bits.RAIE
388 #define INTE INTCON_bits.INTE
389 #define T0IE INTCON_bits.T0IE
390 #define PEIE INTCON_bits.PEIE
391 #define GIE INTCON_bits.GIE
392 #endif /* NO_BIT_DEFINES */
394 // ----- IOCA bits --------------------
397 unsigned char IOCA0:1;
398 unsigned char IOCA1:1;
399 unsigned char IOCA2:1;
400 unsigned char IOCA3:1;
401 unsigned char IOCA4:1;
402 unsigned char IOCA5:1;
407 extern volatile __IOCA_bits_t __at(IOCA_ADDR) IOCA_bits;
409 #ifndef NO_BIT_DEFINES
410 #define IOCA0 IOCA_bits.IOCA0
411 #define IOCA1 IOCA_bits.IOCA1
412 #define IOCA2 IOCA_bits.IOCA2
413 #define IOCA3 IOCA_bits.IOCA3
414 #define IOCA4 IOCA_bits.IOCA4
415 #define IOCA5 IOCA_bits.IOCA5
416 #endif /* NO_BIT_DEFINES */
418 // ----- LVDCON bits --------------------
421 unsigned char LVDL0:1;
422 unsigned char LVDL1:1;
423 unsigned char LVDL2:1;
425 unsigned char LVDEN:1;
426 unsigned char IRVST:1;
431 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
433 #ifndef NO_BIT_DEFINES
434 #define LVDL0 LVDCON_bits.LVDL0
435 #define LVDL1 LVDCON_bits.LVDL1
436 #define LVDL2 LVDCON_bits.LVDL2
437 #define LVDEN LVDCON_bits.LVDEN
438 #define IRVST LVDCON_bits.IRVST
439 #endif /* NO_BIT_DEFINES */
441 // ----- OPTION_REG bits --------------------
448 unsigned char T0SE:1;
449 unsigned char T0CS:1;
450 unsigned char INTEDG:1;
451 unsigned char NOT_RAPU:1;
453 } __OPTION_REG_bits_t;
454 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
456 #ifndef NO_BIT_DEFINES
457 #define PS0 OPTION_REG_bits.PS0
458 #define PS1 OPTION_REG_bits.PS1
459 #define PS2 OPTION_REG_bits.PS2
460 #define PSA OPTION_REG_bits.PSA
461 #define T0SE OPTION_REG_bits.T0SE
462 #define T0CS OPTION_REG_bits.T0CS
463 #define INTEDG OPTION_REG_bits.INTEDG
464 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
465 #endif /* NO_BIT_DEFINES */
467 // ----- OSCCON bits --------------------
473 unsigned char OSTS:1;
474 unsigned char IRCF0:1;
475 unsigned char IRCF1:1;
476 unsigned char IRCF2:1;
480 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
482 #ifndef NO_BIT_DEFINES
483 #define SCS OSCCON_bits.SCS
484 #define LTS OSCCON_bits.LTS
485 #define HTS OSCCON_bits.HTS
486 #define OSTS OSCCON_bits.OSTS
487 #define IRCF0 OSCCON_bits.IRCF0
488 #define IRCF1 OSCCON_bits.IRCF1
489 #define IRCF2 OSCCON_bits.IRCF2
490 #endif /* NO_BIT_DEFINES */
492 // ----- OSCTUNE bits --------------------
495 unsigned char TUN0:1;
496 unsigned char TUN1:1;
497 unsigned char TUN2:1;
498 unsigned char TUN3:1;
499 unsigned char TUN4:1;
505 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
507 #ifndef NO_BIT_DEFINES
508 #define TUN0 OSCTUNE_bits.TUN0
509 #define TUN1 OSCTUNE_bits.TUN1
510 #define TUN2 OSCTUNE_bits.TUN2
511 #define TUN3 OSCTUNE_bits.TUN3
512 #define TUN4 OSCTUNE_bits.TUN4
513 #endif /* NO_BIT_DEFINES */
515 // ----- PCON bits --------------------
518 unsigned char NOT_BOD:1;
519 unsigned char NOT_POR:1;
521 unsigned char NOT_WUR:1;
522 unsigned char SBODEN:1;
523 unsigned char ULPWUE:1;
528 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
530 #ifndef NO_BIT_DEFINES
531 #define NOT_BOD PCON_bits.NOT_BOD
532 #define NOT_POR PCON_bits.NOT_POR
533 #define NOT_WUR PCON_bits.NOT_WUR
534 #define SBODEN PCON_bits.SBODEN
535 #define ULPWUE PCON_bits.ULPWUE
536 #endif /* NO_BIT_DEFINES */
538 // ----- PIE1 bits --------------------
541 unsigned char TMR1IE:1;
543 unsigned char OSFIE:1;
544 unsigned char C1IE:1;
545 unsigned char C2IE:1;
546 unsigned char CRIE:1;
547 unsigned char LVDIE:1;
548 unsigned char EEIE:1;
551 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
553 #ifndef NO_BIT_DEFINES
554 #define TMR1IE PIE1_bits.TMR1IE
555 #define OSFIE PIE1_bits.OSFIE
556 #define C1IE PIE1_bits.C1IE
557 #define C2IE PIE1_bits.C2IE
558 #define CRIE PIE1_bits.CRIE
559 #define LVDIE PIE1_bits.LVDIE
560 #define EEIE PIE1_bits.EEIE
561 #endif /* NO_BIT_DEFINES */
563 // ----- PIR1 bits --------------------
566 unsigned char TMR1IF:1;
568 unsigned char OSFIF:1;
569 unsigned char C1IF:1;
570 unsigned char C2IF:1;
571 unsigned char CRIF:1;
572 unsigned char LVDIF:1;
573 unsigned char EEIF:1;
576 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
578 #ifndef NO_BIT_DEFINES
579 #define TMR1IF PIR1_bits.TMR1IF
580 #define OSFIF PIR1_bits.OSFIF
581 #define C1IF PIR1_bits.C1IF
582 #define C2IF PIR1_bits.C2IF
583 #define CRIF PIR1_bits.CRIF
584 #define LVDIF PIR1_bits.LVDIF
585 #define EEIF PIR1_bits.EEIF
586 #endif /* NO_BIT_DEFINES */
588 // ----- PORTA bits --------------------
601 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
603 #ifndef NO_BIT_DEFINES
604 #define RA0 PORTA_bits.RA0
605 #define RA1 PORTA_bits.RA1
606 #define RA2 PORTA_bits.RA2
607 #define RA3 PORTA_bits.RA3
608 #define RA4 PORTA_bits.RA4
609 #define RA5 PORTA_bits.RA5
610 #endif /* NO_BIT_DEFINES */
612 // ----- PORTC bits --------------------
625 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
627 #ifndef NO_BIT_DEFINES
628 #define RC0 PORTC_bits.RC0
629 #define RC1 PORTC_bits.RC1
630 #define RC2 PORTC_bits.RC2
631 #define RC3 PORTC_bits.RC3
632 #define RC4 PORTC_bits.RC4
633 #define RC5 PORTC_bits.RC5
634 #define RC6 PORTC_bits.RC6
635 #define RC7 PORTC_bits.RC7
636 #endif /* NO_BIT_DEFINES */
638 // ----- STATUS bits --------------------
644 unsigned char NOT_PD:1;
645 unsigned char NOT_TO:1;
651 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
653 #ifndef NO_BIT_DEFINES
654 #define C STATUS_bits.C
655 #define DC STATUS_bits.DC
656 #define Z STATUS_bits.Z
657 #define NOT_PD STATUS_bits.NOT_PD
658 #define NOT_TO STATUS_bits.NOT_TO
659 #define RP0 STATUS_bits.RP0
660 #define RP1 STATUS_bits.RP1
661 #define IRP STATUS_bits.IRP
662 #endif /* NO_BIT_DEFINES */
664 // ----- T1CON bits --------------------
667 unsigned char TMR1ON:1;
668 unsigned char TMR1CS:1;
669 unsigned char NOT_T1SYNC:1;
670 unsigned char T1OSCEN:1;
671 unsigned char T1CKPS0:1;
672 unsigned char T1CKPS1:1;
673 unsigned char TMR1GE:1;
674 unsigned char T1GINV:1;
677 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
679 #ifndef NO_BIT_DEFINES
680 #define TMR1ON T1CON_bits.TMR1ON
681 #define TMR1CS T1CON_bits.TMR1CS
682 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
683 #define T1OSCEN T1CON_bits.T1OSCEN
684 #define T1CKPS0 T1CON_bits.T1CKPS0
685 #define T1CKPS1 T1CON_bits.T1CKPS1
686 #define TMR1GE T1CON_bits.TMR1GE
687 #define T1GINV T1CON_bits.T1GINV
688 #endif /* NO_BIT_DEFINES */
690 // ----- TRISA bits --------------------
693 unsigned char TRISA0:1;
694 unsigned char TRISA1:1;
695 unsigned char TRISA2:1;
696 unsigned char TRISA3:1;
697 unsigned char TRISA4:1;
698 unsigned char TRISA5:1;
703 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
705 #ifndef NO_BIT_DEFINES
706 #define TRISA0 TRISA_bits.TRISA0
707 #define TRISA1 TRISA_bits.TRISA1
708 #define TRISA2 TRISA_bits.TRISA2
709 #define TRISA3 TRISA_bits.TRISA3
710 #define TRISA4 TRISA_bits.TRISA4
711 #define TRISA5 TRISA_bits.TRISA5
712 #endif /* NO_BIT_DEFINES */
714 // ----- TRISC bits --------------------
717 unsigned char TRISC0:1;
718 unsigned char TRISC1:1;
719 unsigned char TRISC2:1;
720 unsigned char TRISC3:1;
721 unsigned char TRISC4:1;
722 unsigned char TRISC5:1;
723 unsigned char TRISC6:1;
724 unsigned char TRISC7:1;
727 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
729 #ifndef NO_BIT_DEFINES
730 #define TRISC0 TRISC_bits.TRISC0
731 #define TRISC1 TRISC_bits.TRISC1
732 #define TRISC2 TRISC_bits.TRISC2
733 #define TRISC3 TRISC_bits.TRISC3
734 #define TRISC4 TRISC_bits.TRISC4
735 #define TRISC5 TRISC_bits.TRISC5
736 #define TRISC6 TRISC_bits.TRISC6
737 #define TRISC7 TRISC_bits.TRISC7
738 #endif /* NO_BIT_DEFINES */
740 // ----- VRCON bits --------------------
750 unsigned char VREN:1;
753 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
755 #ifndef NO_BIT_DEFINES
756 #define VR0 VRCON_bits.VR0
757 #define VR1 VRCON_bits.VR1
758 #define VR2 VRCON_bits.VR2
759 #define VR3 VRCON_bits.VR3
760 #define VRR VRCON_bits.VRR
761 #define VREN VRCON_bits.VREN
762 #endif /* NO_BIT_DEFINES */
764 // ----- WDA bits --------------------
767 unsigned char WDA0:1;
768 unsigned char WDA1:1;
769 unsigned char WDA2:1;
771 unsigned char WDA4:1;
772 unsigned char WDA5:1;
777 extern volatile __WDA_bits_t __at(WDA_ADDR) WDA_bits;
779 #ifndef NO_BIT_DEFINES
780 #define WDA0 WDA_bits.WDA0
781 #define WDA1 WDA_bits.WDA1
782 #define WDA2 WDA_bits.WDA2
783 #define WDA4 WDA_bits.WDA4
784 #define WDA5 WDA_bits.WDA5
785 #endif /* NO_BIT_DEFINES */
787 // ----- WDTCON bits --------------------
790 unsigned char SWDTEN:1;
791 unsigned char WDTPS0:1;
792 unsigned char WDTPS1:1;
793 unsigned char WDTPS2:1;
794 unsigned char WDTPS3:1;
800 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
802 #ifndef NO_BIT_DEFINES
803 #define SWDTEN WDTCON_bits.SWDTEN
804 #define WDTPS0 WDTCON_bits.WDTPS0
805 #define WDTPS1 WDTCON_bits.WDTPS1
806 #define WDTPS2 WDTCON_bits.WDTPS2
807 #define WDTPS3 WDTCON_bits.WDTPS3
808 #endif /* NO_BIT_DEFINES */
810 // ----- WPUDA bits --------------------
813 unsigned char WPUDA0:1;
814 unsigned char WPUDA1:1;
815 unsigned char WPUDA2:1;
817 unsigned char WPUDA4:1;
818 unsigned char WPUDA5:1;
823 extern volatile __WPUDA_bits_t __at(WPUDA_ADDR) WPUDA_bits;
825 #ifndef NO_BIT_DEFINES
826 #define WPUDA0 WPUDA_bits.WPUDA0
827 #define WPUDA1 WPUDA_bits.WPUDA1
828 #define WPUDA2 WPUDA_bits.WPUDA2
829 #define WPUDA4 WPUDA_bits.WPUDA4
830 #define WPUDA5 WPUDA_bits.WPUDA5
831 #endif /* NO_BIT_DEFINES */