2 // Register Declarations for Microchip 16F636 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define WDTCON_ADDR 0x0018
42 #define CMCON0_ADDR 0x0019
43 #define CMCON1_ADDR 0x001A
44 #define OPTION_REG_ADDR 0x0081
45 #define TRISA_ADDR 0x0085
46 #define TRISC_ADDR 0x0087
47 #define PIE1_ADDR 0x008C
48 #define PCON_ADDR 0x008E
49 #define OSCCON_ADDR 0x008F
50 #define OSCTUNE_ADDR 0x0090
51 #define LVDCON_ADDR 0x0094
52 #define WPUDA_ADDR 0x0095
53 #define IOCA_ADDR 0x0096
54 #define WDA_ADDR 0x0097
55 #define VRCON_ADDR 0x0099
56 #define EEDAT_ADDR 0x009A
57 #define EEDATA_ADDR 0x009A
58 #define EEADR_ADDR 0x009B
59 #define EECON1_ADDR 0x009C
60 #define EECON2_ADDR 0x009D
61 #define CRCON_ADDR 0x0110
62 #define CRDAT0_ADDR 0x0111
63 #define CRDAT1_ADDR 0x0112
64 #define CRDAT2_ADDR 0x0113
65 #define CRDAT3_ADDR 0x0114
68 // Memory organization.
74 // P16F636.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
77 // This header file defines configurations, registers, and other useful bits of
78 // information for the PIC16F636 microcontroller. These names are taken to match
79 // the data sheets as closely as possible.
81 // Note that the processor must be selected before this file is
82 // included. The processor may be selected the following ways:
84 // 1. Command line switch:
85 // C:\ MPASM MYFILE.ASM /PIC16F636
86 // 2. LIST directive in the source file
88 // 3. Processor Type entry in the MPASM full-screen interface
90 //==========================================================================
94 //==========================================================================
95 //1.00 12/07/03 Original
96 //1.10 04/19/04 Update to match first release datasheet --kjd
97 //1.20 06/07/04 Update and correct badram definitions --kjd
98 //==========================================================================
102 //==========================================================================
105 // MESSG "Processor-header file mismatch. Verify selected processor."
108 //==========================================================================
110 // Register Definitions
112 //==========================================================================
117 //----- Register Files------------------------------------------------------
119 extern __data __at (INDF_ADDR) volatile char INDF;
120 extern __sfr __at (TMR0_ADDR) TMR0;
121 extern __data __at (PCL_ADDR) volatile char PCL;
122 extern __sfr __at (STATUS_ADDR) STATUS;
123 extern __sfr __at (FSR_ADDR) FSR;
124 extern __sfr __at (PORTA_ADDR) PORTA;
126 extern __sfr __at (PORTC_ADDR) PORTC;
128 extern __sfr __at (PCLATH_ADDR) PCLATH;
129 extern __sfr __at (INTCON_ADDR) INTCON;
130 extern __sfr __at (PIR1_ADDR) PIR1;
132 extern __sfr __at (TMR1L_ADDR) TMR1L;
133 extern __sfr __at (TMR1H_ADDR) TMR1H;
134 extern __sfr __at (T1CON_ADDR) T1CON;
136 extern __sfr __at (WDTCON_ADDR) WDTCON;
137 extern __sfr __at (CMCON0_ADDR) CMCON0;
138 extern __sfr __at (CMCON1_ADDR) CMCON1;
141 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
143 extern __sfr __at (TRISA_ADDR) TRISA;
144 extern __sfr __at (TRISC_ADDR) TRISC;
146 extern __sfr __at (PIE1_ADDR) PIE1;
148 extern __sfr __at (PCON_ADDR) PCON;
149 extern __sfr __at (OSCCON_ADDR) OSCCON;
150 extern __sfr __at (OSCTUNE_ADDR) OSCTUNE;
152 extern __sfr __at (LVDCON_ADDR) LVDCON;
153 extern __sfr __at (WPUDA_ADDR) WPUDA;
154 extern __sfr __at (IOCA_ADDR) IOCA;
155 extern __sfr __at (WDA_ADDR) WDA;
157 extern __sfr __at (VRCON_ADDR) VRCON;
158 extern __sfr __at (EEDAT_ADDR) EEDAT;
159 extern __sfr __at (EEDATA_ADDR) EEDATA;
160 extern __sfr __at (EEADR_ADDR) EEADR;
161 extern __sfr __at (EECON1_ADDR) EECON1;
162 extern __sfr __at (EECON2_ADDR) EECON2;
165 extern __sfr __at (CRCON_ADDR) CRCON;
166 extern __sfr __at (CRDAT0_ADDR) CRDAT0;
167 extern __sfr __at (CRDAT1_ADDR) CRDAT1;
168 extern __sfr __at (CRDAT2_ADDR) CRDAT2;
169 extern __sfr __at (CRDAT3_ADDR) CRDAT3;
171 //----- STATUS Bits --------------------------------------------------------
174 //----- INTCON Bits --------------------------------------------------------
177 //----- PIR1 Bits ----------------------------------------------------------
180 //----- T1CON Bits ---------------------------------------------------------
183 //----- WDTCON Bits --------------------------------------------------------
186 //----- CMCON0 Bits -------------------------------------------------------
189 //----- CMCON1 Bits -------------------------------------------------------
192 //----- OPTION Bits --------------------------------------------------------
195 //----- PIE1 Bits ----------------------------------------------------------
198 //----- PCON Bits ----------------------------------------------------------
201 //----- OSCCON Bits --------------------------------------------------------
204 //----- OSCTUNE Bits -------------------------------------------------------
207 //----- IOCA --------------------------------------------------------------
210 //----- EECON1 -------------------------------------------------------------
213 //----- VRCON ---------------------------------------------------------
217 //----- CRCON -------------------------------------------------------------
220 //----- LVDCON -------------------------------------------------------------
223 //----- WDA -------------------------------------------------------------
226 //----- WPUDA -------------------------------------------------------------
230 //==========================================================================
234 //==========================================================================
237 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'17', H'1B'-H'1F'
238 // __BADRAM H'86', H'88'-H'89', H'8D', H'91'-H'93', H'98', H'9E'-H'9F', H'C0'-H'EF'
239 // __BADRAM H'10C'-H'10F', H'115'-H'16F', H'106', H'108'-H'109', H'186'
240 // __BADRAM H'188'-H'189', H'18C'-H'1EF'
242 //==========================================================================
244 // Configuration Bits
246 //==========================================================================
247 #define _WUREN_ON 0x2FFF
248 #define _WUREN_OFF 0x3FFF
249 #define _FCMEN_ON 0x3FFF
250 #define _FCMEN_OFF 0x37FF
251 #define _IESO_ON 0x3FFF
252 #define _IESO_OFF 0x3BFF
253 #define _BOD_ON 0x3FFF
254 #define _BOD_NSLEEP 0x3EFF
255 #define _BOD_SBODEN 0x3DFF
256 #define _BOD_OFF 0x3CFF
257 #define _CPD_ON 0x3F7F
258 #define _CPD_OFF 0x3FFF
259 #define _CP_ON 0x3FBF
260 #define _CP_OFF 0x3FFF
261 #define _MCLRE_ON 0x3FFF
262 #define _MCLRE_OFF 0x3FDF
263 #define _PWRTE_OFF 0x3FFF
264 #define _PWRTE_ON 0x3FEF
265 #define _WDT_ON 0x3FFF
266 #define _WDT_OFF 0x3FF7
267 #define _LP_OSC 0x3FF8
268 #define _XT_OSC 0x3FF9
269 #define _HS_OSC 0x3FFA
270 #define _EC_OSC 0x3FFB
271 #define _INTRC_OSC_NOCLKOUT 0x3FFC
272 #define _INTRC_OSC_CLKOUT 0x3FFD
273 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
274 #define _EXTRC_OSC_CLKOUT 0x3FFF
278 // ----- CMCON0 bits --------------------
285 unsigned char C1INV:1;
286 unsigned char C2INV:1;
287 unsigned char C1OUT:1;
288 unsigned char C2OUT:1;
291 extern volatile __CMCON0_bits_t __at(CMCON0_ADDR) CMCON0_bits;
293 #define CM0 CMCON0_bits.CM0
294 #define CM1 CMCON0_bits.CM1
295 #define CM2 CMCON0_bits.CM2
296 #define CIS CMCON0_bits.CIS
297 #define C1INV CMCON0_bits.C1INV
298 #define C2INV CMCON0_bits.C2INV
299 #define C1OUT CMCON0_bits.C1OUT
300 #define C2OUT CMCON0_bits.C2OUT
302 // ----- CMCON1 bits --------------------
305 unsigned char C2SYNC:1;
306 unsigned char T1GSS:1;
315 extern volatile __CMCON1_bits_t __at(CMCON1_ADDR) CMCON1_bits;
317 #define C2SYNC CMCON1_bits.C2SYNC
318 #define T1GSS CMCON1_bits.T1GSS
320 // ----- INTCON bits --------------------
323 unsigned char RAIF:1;
324 unsigned char INTF:1;
325 unsigned char T0IF:1;
326 unsigned char RAIE:1;
327 unsigned char INTE:1;
328 unsigned char T0IE:1;
329 unsigned char PEIE:1;
333 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
335 #define RAIF INTCON_bits.RAIF
336 #define INTF INTCON_bits.INTF
337 #define T0IF INTCON_bits.T0IF
338 #define RAIE INTCON_bits.RAIE
339 #define INTE INTCON_bits.INTE
340 #define T0IE INTCON_bits.T0IE
341 #define PEIE INTCON_bits.PEIE
342 #define GIE INTCON_bits.GIE
344 // ----- OPTION_REG bits --------------------
351 unsigned char T0SE:1;
352 unsigned char T0CS:1;
353 unsigned char INTEDG:1;
354 unsigned char NOT_RAPU:1;
356 } __OPTION_REG_bits_t;
357 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
359 #define PS0 OPTION_REG_bits.PS0
360 #define PS1 OPTION_REG_bits.PS1
361 #define PS2 OPTION_REG_bits.PS2
362 #define PSA OPTION_REG_bits.PSA
363 #define T0SE OPTION_REG_bits.T0SE
364 #define T0CS OPTION_REG_bits.T0CS
365 #define INTEDG OPTION_REG_bits.INTEDG
366 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
368 // ----- OSCCON bits --------------------
374 unsigned char OSTS:1;
375 unsigned char IRCF0:1;
376 unsigned char IRCF1:1;
377 unsigned char IRCF2:1;
381 extern volatile __OSCCON_bits_t __at(OSCCON_ADDR) OSCCON_bits;
383 #define SCS OSCCON_bits.SCS
384 #define LTS OSCCON_bits.LTS
385 #define HTS OSCCON_bits.HTS
386 #define OSTS OSCCON_bits.OSTS
387 #define IRCF0 OSCCON_bits.IRCF0
388 #define IRCF1 OSCCON_bits.IRCF1
389 #define IRCF2 OSCCON_bits.IRCF2
391 // ----- OSCTUNE bits --------------------
394 unsigned char TUN0:1;
395 unsigned char TUN1:1;
396 unsigned char TUN2:1;
397 unsigned char TUN3:1;
398 unsigned char TUN4:1;
399 unsigned char IOCA5:1;
400 unsigned char ENC_DEC:1;
401 unsigned char VREN:1;
404 unsigned char IOCA0:1;
405 unsigned char IOCA1:1;
406 unsigned char IOCA2:1;
407 unsigned char IOCA3:1;
408 unsigned char IOCA4:1;
416 unsigned char WREN:1;
417 unsigned char WRERR:1;
418 unsigned char LVDEN:1;
419 unsigned char IRVST:1;
428 unsigned char WDA4:1;
429 unsigned char WDA5:1;
434 unsigned char CRREG0:1;
435 unsigned char CRREG1:1;
436 unsigned char LVDL2:1;
438 unsigned char WPUDA4:1;
439 unsigned char WPUDA5:1;
444 unsigned char LVDL0:1;
445 unsigned char LVDL1:1;
446 unsigned char WDA2:1;
454 unsigned char WDA0:1;
455 unsigned char WDA1:1;
456 unsigned char WPUDA2:1;
464 unsigned char WPUDA0:1;
465 unsigned char WPUDA1:1;
474 extern volatile __OSCTUNE_bits_t __at(OSCTUNE_ADDR) OSCTUNE_bits;
476 #define TUN0 OSCTUNE_bits.TUN0
477 #define IOCA0 OSCTUNE_bits.IOCA0
478 #define RD OSCTUNE_bits.RD
479 #define VR0 OSCTUNE_bits.VR0
480 #define CRREG0 OSCTUNE_bits.CRREG0
481 #define LVDL0 OSCTUNE_bits.LVDL0
482 #define WDA0 OSCTUNE_bits.WDA0
483 #define WPUDA0 OSCTUNE_bits.WPUDA0
484 #define TUN1 OSCTUNE_bits.TUN1
485 #define IOCA1 OSCTUNE_bits.IOCA1
486 #define WR OSCTUNE_bits.WR
487 #define VR1 OSCTUNE_bits.VR1
488 #define CRREG1 OSCTUNE_bits.CRREG1
489 #define LVDL1 OSCTUNE_bits.LVDL1
490 #define WDA1 OSCTUNE_bits.WDA1
491 #define WPUDA1 OSCTUNE_bits.WPUDA1
492 #define TUN2 OSCTUNE_bits.TUN2
493 #define IOCA2 OSCTUNE_bits.IOCA2
494 #define WREN OSCTUNE_bits.WREN
495 #define VR2 OSCTUNE_bits.VR2
496 #define LVDL2 OSCTUNE_bits.LVDL2
497 #define WDA2 OSCTUNE_bits.WDA2
498 #define WPUDA2 OSCTUNE_bits.WPUDA2
499 #define TUN3 OSCTUNE_bits.TUN3
500 #define IOCA3 OSCTUNE_bits.IOCA3
501 #define WRERR OSCTUNE_bits.WRERR
502 #define VR3 OSCTUNE_bits.VR3
503 #define TUN4 OSCTUNE_bits.TUN4
504 #define IOCA4 OSCTUNE_bits.IOCA4
505 #define LVDEN OSCTUNE_bits.LVDEN
506 #define WDA4 OSCTUNE_bits.WDA4
507 #define WPUDA4 OSCTUNE_bits.WPUDA4
508 #define IOCA5 OSCTUNE_bits.IOCA5
509 #define VRR OSCTUNE_bits.VRR
510 #define IRVST OSCTUNE_bits.IRVST
511 #define WDA5 OSCTUNE_bits.WDA5
512 #define WPUDA5 OSCTUNE_bits.WPUDA5
513 #define ENC_DEC OSCTUNE_bits.ENC_DEC
514 #define VREN OSCTUNE_bits.VREN
515 #define GO OSCTUNE_bits.GO
517 // ----- PCON bits --------------------
520 unsigned char NOT_BOD:1;
521 unsigned char NOT_POR:1;
523 unsigned char NOT_WUR:1;
524 unsigned char SBODEN:1;
525 unsigned char ULPWUE:1;
530 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
532 #define NOT_BOD PCON_bits.NOT_BOD
533 #define NOT_POR PCON_bits.NOT_POR
534 #define NOT_WUR PCON_bits.NOT_WUR
535 #define SBODEN PCON_bits.SBODEN
536 #define ULPWUE PCON_bits.ULPWUE
538 // ----- PIE1 bits --------------------
541 unsigned char TMR1IE:1;
543 unsigned char OSFIE:1;
544 unsigned char C1IE:1;
545 unsigned char C2IE:1;
546 unsigned char CRIE:1;
547 unsigned char LVDIE:1;
548 unsigned char EEIE:1;
551 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
553 #define TMR1IE PIE1_bits.TMR1IE
554 #define OSFIE PIE1_bits.OSFIE
555 #define C1IE PIE1_bits.C1IE
556 #define C2IE PIE1_bits.C2IE
557 #define CRIE PIE1_bits.CRIE
558 #define LVDIE PIE1_bits.LVDIE
559 #define EEIE PIE1_bits.EEIE
561 // ----- PIR1 bits --------------------
564 unsigned char TMR1IF:1;
566 unsigned char OSFIF:1;
567 unsigned char C1IF:1;
568 unsigned char C2IF:1;
569 unsigned char CRIF:1;
570 unsigned char LVDIF:1;
571 unsigned char EEIF:1;
574 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
576 #define TMR1IF PIR1_bits.TMR1IF
577 #define OSFIF PIR1_bits.OSFIF
578 #define C1IF PIR1_bits.C1IF
579 #define C2IF PIR1_bits.C2IF
580 #define CRIF PIR1_bits.CRIF
581 #define LVDIF PIR1_bits.LVDIF
582 #define EEIF PIR1_bits.EEIF
584 // ----- STATUS bits --------------------
590 unsigned char NOT_PD:1;
591 unsigned char NOT_TO:1;
597 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
599 #define C STATUS_bits.C
600 #define DC STATUS_bits.DC
601 #define Z STATUS_bits.Z
602 #define NOT_PD STATUS_bits.NOT_PD
603 #define NOT_TO STATUS_bits.NOT_TO
604 #define RP0 STATUS_bits.RP0
605 #define RP1 STATUS_bits.RP1
606 #define IRP STATUS_bits.IRP
608 // ----- T1CON bits --------------------
611 unsigned char TMR1ON:1;
612 unsigned char TMR1CS:1;
613 unsigned char NOT_T1SYNC:1;
614 unsigned char T1OSCEN:1;
615 unsigned char T1CKPS0:1;
616 unsigned char T1CKPS1:1;
617 unsigned char TMR1GE:1;
618 unsigned char T1GINV:1;
621 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
623 #define TMR1ON T1CON_bits.TMR1ON
624 #define TMR1CS T1CON_bits.TMR1CS
625 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
626 #define T1OSCEN T1CON_bits.T1OSCEN
627 #define T1CKPS0 T1CON_bits.T1CKPS0
628 #define T1CKPS1 T1CON_bits.T1CKPS1
629 #define TMR1GE T1CON_bits.TMR1GE
630 #define T1GINV T1CON_bits.T1GINV
632 // ----- WDTCON bits --------------------
635 unsigned char SWDTEN:1;
636 unsigned char WDTPS0:1;
637 unsigned char WDTPS1:1;
638 unsigned char WDTPS2:1;
639 unsigned char WDTPS3:1;
645 extern volatile __WDTCON_bits_t __at(WDTCON_ADDR) WDTCON_bits;
647 #define SWDTEN WDTCON_bits.SWDTEN
648 #define WDTPS0 WDTCON_bits.WDTPS0
649 #define WDTPS1 WDTCON_bits.WDTPS1
650 #define WDTPS2 WDTCON_bits.WDTPS2
651 #define WDTPS3 WDTCON_bits.WDTPS3