2 // Register Declarations for Microchip 16F630 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define CMCON_ADDR 0x0019
42 #define OPTION_REG_ADDR 0x0081
43 #define TRISA_ADDR 0x0085
44 #define TRISC_ADDR 0x0087
45 #define PIE1_ADDR 0x008C
46 #define PCON_ADDR 0x008E
47 #define OSCCAL_ADDR 0x0090
48 #define WPUA_ADDR 0x0095
49 #define WPU_ADDR 0x0095
50 #define IOCA_ADDR 0x0096
51 #define IOC_ADDR 0x0096
52 #define VRCON_ADDR 0x0099
53 #define EEDATA_ADDR 0x009A
54 #define EEDAT_ADDR 0x009A
55 #define EEADR_ADDR 0x009B
56 #define EECON1_ADDR 0x009C
57 #define EECON2_ADDR 0x009D
60 // Memory organization.
66 // P16F630.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
69 // This header file defines configurations, registers, and other useful bits of
70 // information for the PIC16F630 microcontroller. These names are taken to match
71 // the data sheets as closely as possible.
73 // Note that the processor must be selected before this file is
74 // included. The processor may be selected the following ways:
76 // 1. Command line switch:
77 // C:\ MPASM MYFILE.ASM /PIC16F630
78 // 2. LIST directive in the source file
80 // 3. Processor Type entry in the MPASM full-screen interface
82 //==========================================================================
86 //==========================================================================
87 //1.00 05/13/02 Original
89 //==========================================================================
93 //==========================================================================
96 // MESSG "Processor-header file mismatch. Verify selected processor."
99 //==========================================================================
101 // Register Definitions
103 //==========================================================================
108 //----- Register Files------------------------------------------------------
110 extern __data __at (INDF_ADDR) volatile char INDF;
111 extern __sfr __at (TMR0_ADDR) TMR0;
112 extern __data __at (PCL_ADDR) volatile char PCL;
113 extern __sfr __at (STATUS_ADDR) STATUS;
114 extern __sfr __at (FSR_ADDR) FSR;
115 extern __sfr __at (PORTA_ADDR) PORTA;
116 extern __sfr __at (PORTC_ADDR) PORTC;
118 extern __sfr __at (PCLATH_ADDR) PCLATH;
119 extern __sfr __at (INTCON_ADDR) INTCON;
120 extern __sfr __at (PIR1_ADDR) PIR1;
122 extern __sfr __at (TMR1L_ADDR) TMR1L;
123 extern __sfr __at (TMR1H_ADDR) TMR1H;
124 extern __sfr __at (T1CON_ADDR) T1CON;
126 extern __sfr __at (CMCON_ADDR) CMCON;
128 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
130 extern __sfr __at (TRISA_ADDR) TRISA;
131 extern __sfr __at (TRISC_ADDR) TRISC;
133 extern __sfr __at (PIE1_ADDR) PIE1;
135 extern __sfr __at (PCON_ADDR) PCON;
137 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
139 extern __sfr __at (WPUA_ADDR) WPUA;
140 extern __sfr __at (WPU_ADDR) WPU;
141 extern __sfr __at (IOCA_ADDR) IOCA;
142 extern __sfr __at (IOC_ADDR) IOC;
144 extern __sfr __at (VRCON_ADDR) VRCON;
145 extern __sfr __at (EEDATA_ADDR) EEDATA;
146 extern __sfr __at (EEDAT_ADDR) EEDAT;
147 extern __sfr __at (EEADR_ADDR) EEADR;
148 extern __sfr __at (EECON1_ADDR) EECON1;
149 extern __sfr __at (EECON2_ADDR) EECON2;
151 //----- STATUS Bits --------------------------------------------------------
154 //----- INTCON Bits --------------------------------------------------------
157 //----- PIR1 Bits ----------------------------------------------------------
160 //----- T1CON Bits ---------------------------------------------------------
163 //----- COMCON Bits --------------------------------------------------------
166 //----- OPTION Bits --------------------------------------------------------
169 //----- PIE1 Bits ----------------------------------------------------------
172 //----- PCON Bits ----------------------------------------------------------
175 //----- OSCCAL Bits --------------------------------------------------------
178 //----- VRCON Bits ---------------------------------------------------------
181 //----- EECON1 -------------------------------------------------------------
184 //==========================================================================
188 //==========================================================================
191 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'18', H'1A'-H'1F', H'60'-H'7F'
192 // __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'9E'-H'9F', H'E0'-H'FF'
194 //==========================================================================
196 // Configuration Bits
198 //==========================================================================
201 #define _CPD_OFF 0x3FFF
203 #define _CP_OFF 0x3FFF
204 #define _BODEN 0x3FFF
205 #define _BODEN_OFF 0x3FBF
206 #define _MCLRE_ON 0x3FFF
207 #define _MCLRE_OFF 0x3FDF
208 #define _PWRTE_OFF 0x3FFF
209 #define _PWRTE_ON 0x3FEF
210 #define _WDT_ON 0x3FFF
211 #define _WDT_OFF 0x3FF7
212 #define _LP_OSC 0x3FF8
213 #define _XT_OSC 0x3FF9
214 #define _HS_OSC 0x3FFA
215 #define _EC_OSC 0x3FFB
216 #define _INTRC_OSC_NOCLKOUT 0x3FFC
217 #define _INTRC_OSC_CLKOUT 0x3FFD
218 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
219 #define _EXTRC_OSC_CLKOUT 0x3FFF
223 // ----- CMCON bits --------------------
230 unsigned char CINV:1;
232 unsigned char COUT:1;
236 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
238 #define CM0 CMCON_bits.CM0
239 #define CM1 CMCON_bits.CM1
240 #define CM2 CMCON_bits.CM2
241 #define CIS CMCON_bits.CIS
242 #define CINV CMCON_bits.CINV
243 #define COUT CMCON_bits.COUT
245 // ----- EECON1 bits --------------------
250 unsigned char WREN:1;
251 unsigned char WRERR:1;
258 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
260 #define RD EECON1_bits.RD
261 #define WR EECON1_bits.WR
262 #define WREN EECON1_bits.WREN
263 #define WRERR EECON1_bits.WRERR
265 // ----- INTCON bits --------------------
268 unsigned char RAIF:1;
269 unsigned char INTF:1;
270 unsigned char T0IF:1;
271 unsigned char RAIE:1;
272 unsigned char INTE:1;
273 unsigned char T0IE:1;
274 unsigned char PEIE:1;
278 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
280 #define RAIF INTCON_bits.RAIF
281 #define INTF INTCON_bits.INTF
282 #define T0IF INTCON_bits.T0IF
283 #define RAIE INTCON_bits.RAIE
284 #define INTE INTCON_bits.INTE
285 #define T0IE INTCON_bits.T0IE
286 #define PEIE INTCON_bits.PEIE
287 #define GIE INTCON_bits.GIE
289 // ----- OPTION_REG bits --------------------
296 unsigned char T0SE:1;
297 unsigned char T0CS:1;
298 unsigned char INTEDG:1;
299 unsigned char NOT_GPPU:1;
309 unsigned char NOT_RAPU:1;
311 } __OPTION_REG_bits_t;
312 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
314 #define PS0 OPTION_REG_bits.PS0
315 #define PS1 OPTION_REG_bits.PS1
316 #define PS2 OPTION_REG_bits.PS2
317 #define PSA OPTION_REG_bits.PSA
318 #define T0SE OPTION_REG_bits.T0SE
319 #define T0CS OPTION_REG_bits.T0CS
320 #define INTEDG OPTION_REG_bits.INTEDG
321 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
322 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
324 // ----- OSCCAL bits --------------------
329 unsigned char CAL0:1;
330 unsigned char CAL1:1;
331 unsigned char CAL2:1;
332 unsigned char CAL3:1;
333 unsigned char CAL4:1;
334 unsigned char CAL5:1;
337 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
339 #define CAL0 OSCCAL_bits.CAL0
340 #define CAL1 OSCCAL_bits.CAL1
341 #define CAL2 OSCCAL_bits.CAL2
342 #define CAL3 OSCCAL_bits.CAL3
343 #define CAL4 OSCCAL_bits.CAL4
344 #define CAL5 OSCCAL_bits.CAL5
346 // ----- PCON bits --------------------
349 unsigned char NOT_BOD:1;
350 unsigned char NOT_POR:1;
359 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
361 #define NOT_BOD PCON_bits.NOT_BOD
362 #define NOT_POR PCON_bits.NOT_POR
364 // ----- PIE1 bits --------------------
367 unsigned char T1IE:1;
370 unsigned char CMIE:1;
373 unsigned char ADIE:1;
374 unsigned char EEIE:1;
377 unsigned char TMR1IE:1;
387 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
389 #define T1IE PIE1_bits.T1IE
390 #define TMR1IE PIE1_bits.TMR1IE
391 #define CMIE PIE1_bits.CMIE
392 #define ADIE PIE1_bits.ADIE
393 #define EEIE PIE1_bits.EEIE
395 // ----- PIR1 bits --------------------
398 unsigned char T1IF:1;
401 unsigned char CMIF:1;
404 unsigned char ADIF:1;
405 unsigned char EEIF:1;
408 unsigned char TMR1IF:1;
418 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
420 #define T1IF PIR1_bits.T1IF
421 #define TMR1IF PIR1_bits.TMR1IF
422 #define CMIF PIR1_bits.CMIF
423 #define ADIF PIR1_bits.ADIF
424 #define EEIF PIR1_bits.EEIF
426 // ----- PORTA bits --------------------
439 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
441 #define RA0 PORTA_bits.RA0
442 #define RA1 PORTA_bits.RA1
443 #define RA2 PORTA_bits.RA2
444 #define RA3 PORTA_bits.RA3
445 #define RA4 PORTA_bits.RA4
446 #define RA5 PORTA_bits.RA5
448 // ----- PORTC bits --------------------
461 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
463 #define RC0 PORTC_bits.RC0
464 #define RC1 PORTC_bits.RC1
465 #define RC2 PORTC_bits.RC2
466 #define RC3 PORTC_bits.RC3
467 #define RC4 PORTC_bits.RC4
468 #define RC5 PORTC_bits.RC5
469 #define RC6 PORTC_bits.RC6
470 #define RC7 PORTC_bits.RC7
472 // ----- STATUS bits --------------------
478 unsigned char NOT_PD:1;
479 unsigned char NOT_TO:1;
485 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
487 #define C STATUS_bits.C
488 #define DC STATUS_bits.DC
489 #define Z STATUS_bits.Z
490 #define NOT_PD STATUS_bits.NOT_PD
491 #define NOT_TO STATUS_bits.NOT_TO
492 #define RP0 STATUS_bits.RP0
493 #define RP1 STATUS_bits.RP1
494 #define IRP STATUS_bits.IRP
496 // ----- T1CON bits --------------------
499 unsigned char TMR1ON:1;
500 unsigned char TMR1CS:1;
501 unsigned char NOT_T1SYNC:1;
502 unsigned char T1OSCEN:1;
503 unsigned char T1CKPS0:1;
504 unsigned char T1CKPS1:1;
505 unsigned char TMR1GE:1;
509 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
511 #define TMR1ON T1CON_bits.TMR1ON
512 #define TMR1CS T1CON_bits.TMR1CS
513 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
514 #define T1OSCEN T1CON_bits.T1OSCEN
515 #define T1CKPS0 T1CON_bits.T1CKPS0
516 #define T1CKPS1 T1CON_bits.T1CKPS1
517 #define TMR1GE T1CON_bits.TMR1GE
519 // ----- TRISA bits --------------------
522 unsigned char TRISA0:1;
523 unsigned char TRISA1:1;
524 unsigned char TRISA2:1;
525 unsigned char TRISA3:1;
526 unsigned char TRISA4:1;
527 unsigned char TRISA5:1;
532 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
534 #define TRISA0 TRISA_bits.TRISA0
535 #define TRISA1 TRISA_bits.TRISA1
536 #define TRISA2 TRISA_bits.TRISA2
537 #define TRISA3 TRISA_bits.TRISA3
538 #define TRISA4 TRISA_bits.TRISA4
539 #define TRISA5 TRISA_bits.TRISA5
541 // ----- TRISC bits --------------------
544 unsigned char TRISC0:1;
545 unsigned char TRISC1:1;
546 unsigned char TRISC2:1;
547 unsigned char TRISC3:1;
548 unsigned char TRISC4:1;
549 unsigned char TRISC5:1;
550 unsigned char TRISC6:1;
551 unsigned char TRISC7:1;
554 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
556 #define TRISC0 TRISC_bits.TRISC0
557 #define TRISC1 TRISC_bits.TRISC1
558 #define TRISC2 TRISC_bits.TRISC2
559 #define TRISC3 TRISC_bits.TRISC3
560 #define TRISC4 TRISC_bits.TRISC4
561 #define TRISC5 TRISC_bits.TRISC5
562 #define TRISC6 TRISC_bits.TRISC6
563 #define TRISC7 TRISC_bits.TRISC7
565 // ----- VRCON bits --------------------
575 unsigned char VREN:1;
578 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
580 #define VR0 VRCON_bits.VR0
581 #define VR1 VRCON_bits.VR1
582 #define VR2 VRCON_bits.VR2
583 #define VR3 VRCON_bits.VR3
584 #define VRR VRCON_bits.VRR
585 #define VREN VRCON_bits.VREN