2 // Register Declarations for Microchip 16F630 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTC_ADDR 0x0007
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define CMCON_ADDR 0x0019
42 #define OPTION_REG_ADDR 0x0081
43 #define TRISA_ADDR 0x0085
44 #define TRISC_ADDR 0x0087
45 #define PIE1_ADDR 0x008C
46 #define PCON_ADDR 0x008E
47 #define OSCCAL_ADDR 0x0090
48 #define WPUA_ADDR 0x0095
49 #define WPU_ADDR 0x0095
50 #define IOCA_ADDR 0x0096
51 #define IOC_ADDR 0x0096
52 #define VRCON_ADDR 0x0099
53 #define EEDATA_ADDR 0x009A
54 #define EEDAT_ADDR 0x009A
55 #define EEADR_ADDR 0x009B
56 #define EECON1_ADDR 0x009C
57 #define EECON2_ADDR 0x009D
60 // Memory organization.
63 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
64 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
65 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
66 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
67 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
68 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
69 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
70 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
71 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
72 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
73 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
74 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
75 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
76 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
77 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
78 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
79 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
80 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
81 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
82 #pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL
83 #pragma memmap WPUA_ADDR WPUA_ADDR SFR 0x000 // WPUA
84 #pragma memmap WPU_ADDR WPU_ADDR SFR 0x000 // WPU
85 #pragma memmap IOCA_ADDR IOCA_ADDR SFR 0x000 // IOCA
86 #pragma memmap IOC_ADDR IOC_ADDR SFR 0x000 // IOC
87 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
88 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
89 #pragma memmap EEDAT_ADDR EEDAT_ADDR SFR 0x000 // EEDAT
90 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
91 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
92 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
96 // P16F630.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
99 // This header file defines configurations, registers, and other useful bits of
100 // information for the PIC16F630 microcontroller. These names are taken to match
101 // the data sheets as closely as possible.
103 // Note that the processor must be selected before this file is
104 // included. The processor may be selected the following ways:
106 // 1. Command line switch:
107 // C:\ MPASM MYFILE.ASM /PIC16F630
108 // 2. LIST directive in the source file
110 // 3. Processor Type entry in the MPASM full-screen interface
112 //==========================================================================
116 //==========================================================================
117 //1.00 05/13/02 Original
119 //==========================================================================
123 //==========================================================================
126 // MESSG "Processor-header file mismatch. Verify selected processor."
129 //==========================================================================
131 // Register Definitions
133 //==========================================================================
138 //----- Register Files------------------------------------------------------
140 extern data __at (INDF_ADDR) volatile char INDF;
141 extern sfr __at (TMR0_ADDR) TMR0;
142 extern data __at (PCL_ADDR) volatile char PCL;
143 extern sfr __at (STATUS_ADDR) STATUS;
144 extern sfr __at (FSR_ADDR) FSR;
145 extern sfr __at (PORTA_ADDR) PORTA;
146 extern sfr __at (PORTC_ADDR) PORTC;
148 extern sfr __at (PCLATH_ADDR) PCLATH;
149 extern sfr __at (INTCON_ADDR) INTCON;
150 extern sfr __at (PIR1_ADDR) PIR1;
152 extern sfr __at (TMR1L_ADDR) TMR1L;
153 extern sfr __at (TMR1H_ADDR) TMR1H;
154 extern sfr __at (T1CON_ADDR) T1CON;
156 extern sfr __at (CMCON_ADDR) CMCON;
158 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
160 extern sfr __at (TRISA_ADDR) TRISA;
161 extern sfr __at (TRISC_ADDR) TRISC;
163 extern sfr __at (PIE1_ADDR) PIE1;
165 extern sfr __at (PCON_ADDR) PCON;
167 extern sfr __at (OSCCAL_ADDR) OSCCAL;
169 extern sfr __at (WPUA_ADDR) WPUA;
170 extern sfr __at (WPU_ADDR) WPU;
171 extern sfr __at (IOCA_ADDR) IOCA;
172 extern sfr __at (IOC_ADDR) IOC;
174 extern sfr __at (VRCON_ADDR) VRCON;
175 extern sfr __at (EEDATA_ADDR) EEDATA;
176 extern sfr __at (EEDAT_ADDR) EEDAT;
177 extern sfr __at (EEADR_ADDR) EEADR;
178 extern sfr __at (EECON1_ADDR) EECON1;
179 extern sfr __at (EECON2_ADDR) EECON2;
181 //----- STATUS Bits --------------------------------------------------------
184 //----- INTCON Bits --------------------------------------------------------
187 //----- PIR1 Bits ----------------------------------------------------------
190 //----- T1CON Bits ---------------------------------------------------------
193 //----- CMCON Bits --------------------------------------------------------
196 //----- OPTION Bits --------------------------------------------------------
199 //----- PIE1 Bits ----------------------------------------------------------
202 //----- PCON Bits ----------------------------------------------------------
205 //----- OSCCAL Bits --------------------------------------------------------
208 //----- VRCON Bits ---------------------------------------------------------
211 //----- EECON1 -------------------------------------------------------------
214 //==========================================================================
218 //==========================================================================
221 // __BADRAM H'06', H'08'-H'09', H'0D', H'11'-H'18', H'1A'-H'1F', H'60'-H'7F'
222 // __BADRAM H'86', H'88'-H'89', H'8D', H'8F', H'91'-H'94', H'97'-H'98', H'9E'-H'9F', H'E0'-H'FF'
224 //==========================================================================
226 // Configuration Bits
228 //==========================================================================
231 #define _CPD_OFF 0x3FFF
233 #define _CP_OFF 0x3FFF
234 #define _BODEN 0x3FFF
235 #define _BODEN_OFF 0x3FBF
236 #define _MCLRE_ON 0x3FFF
237 #define _MCLRE_OFF 0x3FDF
238 #define _PWRTE_OFF 0x3FFF
239 #define _PWRTE_ON 0x3FEF
240 #define _WDT_ON 0x3FFF
241 #define _WDT_OFF 0x3FF7
242 #define _LP_OSC 0x3FF8
243 #define _XT_OSC 0x3FF9
244 #define _HS_OSC 0x3FFA
245 #define _EC_OSC 0x3FFB
246 #define _INTRC_OSC_NOCLKOUT 0x3FFC
247 #define _INTRC_OSC_CLKOUT 0x3FFD
248 #define _EXTRC_OSC_NOCLKOUT 0x3FFE
249 #define _EXTRC_OSC_CLKOUT 0x3FFF
253 // ----- CMCON bits --------------------
260 unsigned char CINV:1;
262 unsigned char COUT:1;
266 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
268 #define CM0 CMCON_bits.CM0
269 #define CM1 CMCON_bits.CM1
270 #define CM2 CMCON_bits.CM2
271 #define CIS CMCON_bits.CIS
272 #define CINV CMCON_bits.CINV
273 #define COUT CMCON_bits.COUT
275 // ----- INTCON bits --------------------
278 unsigned char RAIF:1;
279 unsigned char INTF:1;
280 unsigned char T0IF:1;
281 unsigned char RAIE:1;
282 unsigned char INTE:1;
283 unsigned char T0IE:1;
284 unsigned char PEIE:1;
288 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
290 #define RAIF INTCON_bits.RAIF
291 #define INTF INTCON_bits.INTF
292 #define T0IF INTCON_bits.T0IF
293 #define RAIE INTCON_bits.RAIE
294 #define INTE INTCON_bits.INTE
295 #define T0IE INTCON_bits.T0IE
296 #define PEIE INTCON_bits.PEIE
297 #define GIE INTCON_bits.GIE
299 // ----- OPTION_REG bits --------------------
306 unsigned char T0SE:1;
307 unsigned char T0CS:1;
308 unsigned char INTEDG:1;
309 unsigned char NOT_GPPU:1;
319 unsigned char NOT_RAPU:1;
321 } __OPTION_REG_bits_t;
322 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
324 #define PS0 OPTION_REG_bits.PS0
325 #define PS1 OPTION_REG_bits.PS1
326 #define PS2 OPTION_REG_bits.PS2
327 #define PSA OPTION_REG_bits.PSA
328 #define T0SE OPTION_REG_bits.T0SE
329 #define T0CS OPTION_REG_bits.T0CS
330 #define INTEDG OPTION_REG_bits.INTEDG
331 #define NOT_GPPU OPTION_REG_bits.NOT_GPPU
332 #define NOT_RAPU OPTION_REG_bits.NOT_RAPU
334 // ----- OSCCAL bits --------------------
339 unsigned char CAL0:1;
340 unsigned char CAL1:1;
341 unsigned char CAL2:1;
342 unsigned char CAL3:1;
343 unsigned char CAL4:1;
344 unsigned char CAL5:1;
347 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
349 #define CAL0 OSCCAL_bits.CAL0
350 #define CAL1 OSCCAL_bits.CAL1
351 #define CAL2 OSCCAL_bits.CAL2
352 #define CAL3 OSCCAL_bits.CAL3
353 #define CAL4 OSCCAL_bits.CAL4
354 #define CAL5 OSCCAL_bits.CAL5
356 // ----- PCON bits --------------------
359 unsigned char NOT_BOD:1;
360 unsigned char NOT_POR:1;
369 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
371 #define NOT_BOD PCON_bits.NOT_BOD
372 #define NOT_POR PCON_bits.NOT_POR
374 // ----- PIE1 bits --------------------
377 unsigned char T1IE:1;
380 unsigned char CMIE:1;
383 unsigned char ADIE:1;
384 unsigned char EEIE:1;
387 unsigned char TMR1IE:1;
397 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
399 #define T1IE PIE1_bits.T1IE
400 #define TMR1IE PIE1_bits.TMR1IE
401 #define CMIE PIE1_bits.CMIE
402 #define ADIE PIE1_bits.ADIE
403 #define EEIE PIE1_bits.EEIE
405 // ----- PIR1 bits --------------------
408 unsigned char T1IF:1;
411 unsigned char CMIF:1;
414 unsigned char ADIF:1;
415 unsigned char EEIF:1;
418 unsigned char TMR1IF:1;
428 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
430 #define T1IF PIR1_bits.T1IF
431 #define TMR1IF PIR1_bits.TMR1IF
432 #define CMIF PIR1_bits.CMIF
433 #define ADIF PIR1_bits.ADIF
434 #define EEIF PIR1_bits.EEIF
436 // ----- STATUS bits --------------------
442 unsigned char NOT_PD:1;
443 unsigned char NOT_TO:1;
449 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
451 #define C STATUS_bits.C
452 #define DC STATUS_bits.DC
453 #define Z STATUS_bits.Z
454 #define NOT_PD STATUS_bits.NOT_PD
455 #define NOT_TO STATUS_bits.NOT_TO
456 #define RP0 STATUS_bits.RP0
457 #define RP1 STATUS_bits.RP1
458 #define IRP STATUS_bits.IRP
460 // ----- T1CON bits --------------------
463 unsigned char TMR1ON:1;
464 unsigned char TMR1CS:1;
465 unsigned char NOT_T1SYNC:1;
466 unsigned char T1OSCEN:1;
467 unsigned char T1CKPS0:1;
468 unsigned char T1CKPS1:1;
469 unsigned char TMR1GE:1;
473 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
475 #define TMR1ON T1CON_bits.TMR1ON
476 #define TMR1CS T1CON_bits.TMR1CS
477 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
478 #define T1OSCEN T1CON_bits.T1OSCEN
479 #define T1CKPS0 T1CON_bits.T1CKPS0
480 #define T1CKPS1 T1CON_bits.T1CKPS1
481 #define TMR1GE T1CON_bits.TMR1GE
483 // ----- VRCON bits --------------------
493 unsigned char VREN:1;
498 unsigned char WREN:1;
499 unsigned char WRERR:1;
506 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
508 #define VR0 VRCON_bits.VR0
509 #define RD VRCON_bits.RD
510 #define VR1 VRCON_bits.VR1
511 #define WR VRCON_bits.WR
512 #define VR2 VRCON_bits.VR2
513 #define WREN VRCON_bits.WREN
514 #define VR3 VRCON_bits.VR3
515 #define WRERR VRCON_bits.WRERR
516 #define VRR VRCON_bits.VRR
517 #define VREN VRCON_bits.VREN