2 // Register Declarations for Microchip 16F628 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define TMR2_ADDR 0x0011
42 #define T2CON_ADDR 0x0012
43 #define CCPR1L_ADDR 0x0015
44 #define CCPR1H_ADDR 0x0016
45 #define CCP1CON_ADDR 0x0017
46 #define RCSTA_ADDR 0x0018
47 #define TXREG_ADDR 0x0019
48 #define RCREG_ADDR 0x001A
49 #define CMCON_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define PIE1_ADDR 0x008C
54 #define PCON_ADDR 0x008E
55 #define PR2_ADDR 0x0092
56 #define TXSTA_ADDR 0x0098
57 #define SPBRG_ADDR 0x0099
58 #define EEDATA_ADDR 0x009A
59 #define EEADR_ADDR 0x009B
60 #define EECON1_ADDR 0x009C
61 #define EECON2_ADDR 0x009D
62 #define VRCON_ADDR 0x009F
65 // Memory organization.
71 // P16F628.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
74 // This header file defines configurations, registers, and other useful bits of
75 // information for the PIC16F628 microcontroller. These names are taken to match
76 // the data sheets as closely as possible.
78 // Note that the processor must be selected before this file is
79 // included. The processor may be selected the following ways:
81 // 1. Command line switch:
82 // C:\ MPASM MYFILE.ASM /PIC16F628
83 // 2. LIST directive in the source file
85 // 3. Processor Type entry in the MPASM full-screen interface
87 //==========================================================================
91 //==========================================================================
94 //1.01 13 Sept 2001 Added _DATA_CP_ON and _DATA_CP_OFF
95 //1.00 10 Feb 1999 Initial Release
97 //==========================================================================
101 //==========================================================================
104 // MESSG "Processor-header file mismatch. Verify selected processor."
107 //==========================================================================
109 // Register Definitions
111 //==========================================================================
116 //----- Register Files------------------------------------------------------
118 extern __data __at (INDF_ADDR) volatile char INDF;
119 extern __sfr __at (TMR0_ADDR) TMR0;
120 extern __data __at (PCL_ADDR) volatile char PCL;
121 extern __sfr __at (STATUS_ADDR) STATUS;
122 extern __sfr __at (FSR_ADDR) FSR;
123 extern __sfr __at (PORTA_ADDR) PORTA;
124 extern __sfr __at (PORTB_ADDR) PORTB;
125 extern __sfr __at (PCLATH_ADDR) PCLATH;
126 extern __sfr __at (INTCON_ADDR) INTCON;
127 extern __sfr __at (PIR1_ADDR) PIR1;
128 extern __sfr __at (TMR1L_ADDR) TMR1L;
129 extern __sfr __at (TMR1H_ADDR) TMR1H;
130 extern __sfr __at (T1CON_ADDR) T1CON;
131 extern __sfr __at (TMR2_ADDR) TMR2;
132 extern __sfr __at (T2CON_ADDR) T2CON;
133 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
134 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
135 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
136 extern __sfr __at (RCSTA_ADDR) RCSTA;
137 extern __sfr __at (TXREG_ADDR) TXREG;
138 extern __sfr __at (RCREG_ADDR) RCREG;
139 extern __sfr __at (CMCON_ADDR) CMCON;
141 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
142 extern __sfr __at (TRISA_ADDR) TRISA;
143 extern __sfr __at (TRISB_ADDR) TRISB;
144 extern __sfr __at (PIE1_ADDR) PIE1;
145 extern __sfr __at (PCON_ADDR) PCON;
146 extern __sfr __at (PR2_ADDR) PR2;
147 extern __sfr __at (TXSTA_ADDR) TXSTA;
148 extern __sfr __at (SPBRG_ADDR) SPBRG;
149 extern __sfr __at (EEDATA_ADDR) EEDATA;
150 extern __sfr __at (EEADR_ADDR) EEADR;
151 extern __sfr __at (EECON1_ADDR) EECON1;
152 extern __sfr __at (EECON2_ADDR) EECON2;
153 extern __sfr __at (VRCON_ADDR) VRCON;
155 //----- STATUS Bits --------------------------------------------------------
158 //----- INTCON Bits --------------------------------------------------------
161 //----- PIR1 Bits ----------------------------------------------------------
164 //----- T1CON Bits ---------------------------------------------------------
166 //----- T2CON Bits ---------------------------------------------------------
168 //----- CCP1CON Bits ---------------------------------------------------------
170 //----- RCSTA Bits ---------------------------------------------------------
172 //----- CMCON Bits ---------------------------------------------------------
175 //----- OPTION Bits --------------------------------------------------------
178 //----- PIE1 Bits ----------------------------------------------------------
181 //----- PCON Bits ----------------------------------------------------------
184 //----- TXSTA Bits ----------------------------------------------------------
186 //----- EECON1 Bits ---------------------------------------------------------
188 //----- VRCON Bits ---------------------------------------------------------
191 //==========================================================================
195 //==========================================================================
198 // __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E'
199 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E'
200 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F'
201 // __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF'
203 //==========================================================================
205 // Configuration Bits
207 //==========================================================================
209 #define _BODEN_ON 0x3FFF
210 #define _BODEN_OFF 0x3FBF
211 #define _CP_ALL 0x03FF
212 #define _CP_75 0x17FF
213 #define _CP_50 0x2BFF
214 #define _CP_OFF 0x3FFF
215 #define _DATA_CP_ON 0x3EFF
216 #define _DATA_CP_OFF 0x3FFF
217 #define _PWRTE_OFF 0x3FFF
218 #define _PWRTE_ON 0x3FF7
219 #define _WDT_ON 0x3FFF
220 #define _WDT_OFF 0x3FFB
221 #define _LVP_ON 0x3FFF
222 #define _LVP_OFF 0x3F7F
223 #define _MCLRE_ON 0x3FFF
224 #define _MCLRE_OFF 0x3FDF
225 #define _ER_OSC_CLKOUT 0x3FFF
226 #define _ER_OSC_NOCLKOUT 0x3FFE
227 #define _INTRC_OSC_CLKOUT 0x3FFD
228 #define _INTRC_OSC_NOCLKOUT 0x3FFC
229 #define _EXTCLK_OSC 0x3FEF
230 #define _LP_OSC 0x3FEC
231 #define _XT_OSC 0x3FED
232 #define _HS_OSC 0x3FEE
236 // ----- CCP1CON bits --------------------
239 unsigned char CCP1M0:1;
240 unsigned char CCP1M1:1;
241 unsigned char CCP1M2:1;
242 unsigned char CCP1M3:1;
243 unsigned char CCP1Y:1;
244 unsigned char CCP1X:1;
249 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
251 #define CCP1M0 CCP1CON_bits.CCP1M0
252 #define CCP1M1 CCP1CON_bits.CCP1M1
253 #define CCP1M2 CCP1CON_bits.CCP1M2
254 #define CCP1M3 CCP1CON_bits.CCP1M3
255 #define CCP1Y CCP1CON_bits.CCP1Y
256 #define CCP1X CCP1CON_bits.CCP1X
258 // ----- CMCON bits --------------------
265 unsigned char C1INV:1;
266 unsigned char C2INV:1;
267 unsigned char C1OUT:1;
268 unsigned char C2OUT:1;
271 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
273 #define CM0 CMCON_bits.CM0
274 #define CM1 CMCON_bits.CM1
275 #define CM2 CMCON_bits.CM2
276 #define CIS CMCON_bits.CIS
277 #define C1INV CMCON_bits.C1INV
278 #define C2INV CMCON_bits.C2INV
279 #define C1OUT CMCON_bits.C1OUT
280 #define C2OUT CMCON_bits.C2OUT
282 // ----- EECON1 bits --------------------
287 unsigned char WREN:1;
288 unsigned char WRERR:1;
295 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
297 #define RD EECON1_bits.RD
298 #define WR EECON1_bits.WR
299 #define WREN EECON1_bits.WREN
300 #define WRERR EECON1_bits.WRERR
302 // ----- INTCON bits --------------------
305 unsigned char RBIF:1;
306 unsigned char INTF:1;
307 unsigned char T0IF:1;
308 unsigned char RBIE:1;
309 unsigned char INTE:1;
310 unsigned char T0IE:1;
311 unsigned char PEIE:1;
315 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
317 #define RBIF INTCON_bits.RBIF
318 #define INTF INTCON_bits.INTF
319 #define T0IF INTCON_bits.T0IF
320 #define RBIE INTCON_bits.RBIE
321 #define INTE INTCON_bits.INTE
322 #define T0IE INTCON_bits.T0IE
323 #define PEIE INTCON_bits.PEIE
324 #define GIE INTCON_bits.GIE
326 // ----- OPTION_REG bits --------------------
333 unsigned char T0SE:1;
334 unsigned char T0CS:1;
335 unsigned char INTEDG:1;
336 unsigned char NOT_RBPU:1;
338 } __OPTION_REG_bits_t;
339 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
341 #define PS0 OPTION_REG_bits.PS0
342 #define PS1 OPTION_REG_bits.PS1
343 #define PS2 OPTION_REG_bits.PS2
344 #define PSA OPTION_REG_bits.PSA
345 #define T0SE OPTION_REG_bits.T0SE
346 #define T0CS OPTION_REG_bits.T0CS
347 #define INTEDG OPTION_REG_bits.INTEDG
348 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
350 // ----- PCON bits --------------------
353 unsigned char NOT_BO:1;
354 unsigned char NOT_POR:1;
356 unsigned char OSCF:1;
363 unsigned char NOT_BOR:1;
373 unsigned char NOT_BOD:1;
383 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
385 #define NOT_BO PCON_bits.NOT_BO
386 #define NOT_BOR PCON_bits.NOT_BOR
387 #define NOT_BOD PCON_bits.NOT_BOD
388 #define NOT_POR PCON_bits.NOT_POR
389 #define OSCF PCON_bits.OSCF
391 // ----- PIE1 bits --------------------
394 unsigned char TMR1IE:1;
395 unsigned char TMR2IE:1;
396 unsigned char CCP1IE:1;
398 unsigned char TXIE:1;
399 unsigned char RCIE:1;
400 unsigned char CMIE:1;
401 unsigned char EEIE:1;
404 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
406 #define TMR1IE PIE1_bits.TMR1IE
407 #define TMR2IE PIE1_bits.TMR2IE
408 #define CCP1IE PIE1_bits.CCP1IE
409 #define TXIE PIE1_bits.TXIE
410 #define RCIE PIE1_bits.RCIE
411 #define CMIE PIE1_bits.CMIE
412 #define EEIE PIE1_bits.EEIE
414 // ----- PIR1 bits --------------------
417 unsigned char TMR1IF:1;
418 unsigned char TMR2IF:1;
419 unsigned char CCP1IF:1;
421 unsigned char TXIF:1;
422 unsigned char RCIF:1;
423 unsigned char CMIF:1;
424 unsigned char EEIF:1;
427 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
429 #define TMR1IF PIR1_bits.TMR1IF
430 #define TMR2IF PIR1_bits.TMR2IF
431 #define CCP1IF PIR1_bits.CCP1IF
432 #define TXIF PIR1_bits.TXIF
433 #define RCIF PIR1_bits.RCIF
434 #define CMIF PIR1_bits.CMIF
435 #define EEIF PIR1_bits.EEIF
437 // ----- RCSTA bits --------------------
440 unsigned char RX9D:1;
441 unsigned char OERR:1;
442 unsigned char FERR:1;
443 unsigned char ADEN:1;
444 unsigned char CREN:1;
445 unsigned char SREN:1;
447 unsigned char SPEN:1;
450 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
452 #define RX9D RCSTA_bits.RX9D
453 #define OERR RCSTA_bits.OERR
454 #define FERR RCSTA_bits.FERR
455 #define ADEN RCSTA_bits.ADEN
456 #define CREN RCSTA_bits.CREN
457 #define SREN RCSTA_bits.SREN
458 #define RX9 RCSTA_bits.RX9
459 #define SPEN RCSTA_bits.SPEN
461 // ----- STATUS bits --------------------
467 unsigned char NOT_PD:1;
468 unsigned char NOT_TO:1;
474 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
476 #define C STATUS_bits.C
477 #define DC STATUS_bits.DC
478 #define Z STATUS_bits.Z
479 #define NOT_PD STATUS_bits.NOT_PD
480 #define NOT_TO STATUS_bits.NOT_TO
481 #define RP0 STATUS_bits.RP0
482 #define RP1 STATUS_bits.RP1
483 #define IRP STATUS_bits.IRP
485 // ----- T1CON bits --------------------
488 unsigned char TMR1ON:1;
489 unsigned char TMR1CS:1;
490 unsigned char NOT_T1SYNC:1;
491 unsigned char T1OSCEN:1;
492 unsigned char T1CKPS0:1;
493 unsigned char T1CKPS1:1;
498 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
500 #define TMR1ON T1CON_bits.TMR1ON
501 #define TMR1CS T1CON_bits.TMR1CS
502 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
503 #define T1OSCEN T1CON_bits.T1OSCEN
504 #define T1CKPS0 T1CON_bits.T1CKPS0
505 #define T1CKPS1 T1CON_bits.T1CKPS1
507 // ----- T2CON bits --------------------
510 unsigned char T2CKPS0:1;
511 unsigned char T2CKPS1:1;
512 unsigned char TMR2ON:1;
513 unsigned char TOUTPS0:1;
514 unsigned char TOUTPS1:1;
515 unsigned char TOUTPS2:1;
516 unsigned char TOUTPS3:1;
520 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
522 #define T2CKPS0 T2CON_bits.T2CKPS0
523 #define T2CKPS1 T2CON_bits.T2CKPS1
524 #define TMR2ON T2CON_bits.TMR2ON
525 #define TOUTPS0 T2CON_bits.TOUTPS0
526 #define TOUTPS1 T2CON_bits.TOUTPS1
527 #define TOUTPS2 T2CON_bits.TOUTPS2
528 #define TOUTPS3 T2CON_bits.TOUTPS3
530 // ----- TXSTA bits --------------------
533 unsigned char TX9D:1;
534 unsigned char TRMT:1;
535 unsigned char BRGH:1;
537 unsigned char SYNC:1;
538 unsigned char TXEN:1;
540 unsigned char CSRC:1;
543 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
545 #define TX9D TXSTA_bits.TX9D
546 #define TRMT TXSTA_bits.TRMT
547 #define BRGH TXSTA_bits.BRGH
548 #define SYNC TXSTA_bits.SYNC
549 #define TXEN TXSTA_bits.TXEN
550 #define TX9 TXSTA_bits.TX9
551 #define CSRC TXSTA_bits.CSRC
553 // ----- VRCON bits --------------------
562 unsigned char VROE:1;
563 unsigned char VREN:1;
566 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
568 #define VR0 VRCON_bits.VR0
569 #define VR1 VRCON_bits.VR1
570 #define VR2 VRCON_bits.VR2
571 #define VR3 VRCON_bits.VR3
572 #define VRR VRCON_bits.VRR
573 #define VROE VRCON_bits.VROE
574 #define VREN VRCON_bits.VREN