2 // Register Declarations for Microchip 16F627A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define TMR2_ADDR 0x0011
42 #define T2CON_ADDR 0x0012
43 #define CCPR1L_ADDR 0x0015
44 #define CCPR1H_ADDR 0x0016
45 #define CCP1CON_ADDR 0x0017
46 #define RCSTA_ADDR 0x0018
47 #define TXREG_ADDR 0x0019
48 #define RCREG_ADDR 0x001A
49 #define CMCON_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define PIE1_ADDR 0x008C
54 #define PCON_ADDR 0x008E
55 #define PR2_ADDR 0x0092
56 #define TXSTA_ADDR 0x0098
57 #define SPBRG_ADDR 0x0099
58 #define EEDATA_ADDR 0x009A
59 #define EEADR_ADDR 0x009B
60 #define EECON1_ADDR 0x009C
61 #define EECON2_ADDR 0x009D
62 #define VRCON_ADDR 0x009F
65 // Memory organization.
71 // P16F627A.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
74 // This header file defines configurations, registers, and other useful bits of
75 // information for the PIC16F627A microcontroller. These names are taken to match
76 // the data sheets as closely as possible.
78 // Note that the processor must be selected before this file is
79 // included. The processor may be selected the following ways:
81 // 1. Command line switch:
82 // C:\ MPASM MYFILE.ASM /PIC16F627A
83 // 2. LIST directive in the source file
85 // 3. Processor Type entry in the MPASM full-screen interface
87 //==========================================================================
91 //==========================================================================
94 //1.01 14 Nov 2002 Updated to reflect BOD terminology changed to BOR
95 //1.00 22 Aug 2002 Initial Release
97 //==========================================================================
101 //==========================================================================
104 // MESSG "Processor-header file mismatch. Verify selected processor."
107 //==========================================================================
109 // Register Definitions
111 //==========================================================================
116 //----- Register Files------------------------------------------------------
118 extern __sfr __at (INDF_ADDR) INDF;
119 extern __sfr __at (TMR0_ADDR) TMR0;
120 extern __sfr __at (PCL_ADDR) PCL;
121 extern __sfr __at (STATUS_ADDR) STATUS;
122 extern __sfr __at (FSR_ADDR) FSR;
123 extern __sfr __at (PORTA_ADDR) PORTA;
124 extern __sfr __at (PORTB_ADDR) PORTB;
125 extern __sfr __at (PCLATH_ADDR) PCLATH;
126 extern __sfr __at (INTCON_ADDR) INTCON;
127 extern __sfr __at (PIR1_ADDR) PIR1;
128 extern __sfr __at (TMR1L_ADDR) TMR1L;
129 extern __sfr __at (TMR1H_ADDR) TMR1H;
130 extern __sfr __at (T1CON_ADDR) T1CON;
131 extern __sfr __at (TMR2_ADDR) TMR2;
132 extern __sfr __at (T2CON_ADDR) T2CON;
133 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
134 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
135 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
136 extern __sfr __at (RCSTA_ADDR) RCSTA;
137 extern __sfr __at (TXREG_ADDR) TXREG;
138 extern __sfr __at (RCREG_ADDR) RCREG;
139 extern __sfr __at (CMCON_ADDR) CMCON;
141 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
142 extern __sfr __at (TRISA_ADDR) TRISA;
143 extern __sfr __at (TRISB_ADDR) TRISB;
144 extern __sfr __at (PIE1_ADDR) PIE1;
145 extern __sfr __at (PCON_ADDR) PCON;
146 extern __sfr __at (PR2_ADDR) PR2;
147 extern __sfr __at (TXSTA_ADDR) TXSTA;
148 extern __sfr __at (SPBRG_ADDR) SPBRG;
149 extern __sfr __at (EEDATA_ADDR) EEDATA;
150 extern __sfr __at (EEADR_ADDR) EEADR;
151 extern __sfr __at (EECON1_ADDR) EECON1;
152 extern __sfr __at (EECON2_ADDR) EECON2;
153 extern __sfr __at (VRCON_ADDR) VRCON;
155 //==========================================================================
159 //==========================================================================
162 // __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E'
163 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E'
164 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F'
165 // __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF'
167 //==========================================================================
169 // Configuration Bits
171 //==========================================================================
173 #define _BODEN_ON 0x3FFF //Backwards compatability to 16F62X
174 #define _BODEN_OFF 0x3FBF //Backwards compatability to 16F62X
175 #define _BOREN_ON 0x3FFF
176 #define _BOREN_OFF 0x3FBF
177 #define _CP_ON 0x1FFF
178 #define _CP_OFF 0x3FFF
179 #define _DATA_CP_ON 0x3EFF
180 #define _DATA_CP_OFF 0x3FFF
181 #define _PWRTE_OFF 0x3FFF
182 #define _PWRTE_ON 0x3FF7
183 #define _WDT_ON 0x3FFF
184 #define _WDT_OFF 0x3FFB
185 #define _LVP_ON 0x3FFF
186 #define _LVP_OFF 0x3F7F
187 #define _MCLRE_ON 0x3FFF
188 #define _MCLRE_OFF 0x3FDF
189 #define _RC_OSC_CLKOUT 0x3FFF
190 #define _RC_OSC_NOCLKOUT 0x3FFE
191 #define _ER_OSC_CLKOUT 0x3FFF //Backwards compatability to 16F62X
192 #define _ER_OSC_NOCLKOUT 0x3FFE //Backwards compatability to 16F62X
193 #define _INTOSC_OSC_CLKOUT 0x3FFD
194 #define _INTOSC_OSC_NOCLKOUT 0x3FFC
195 #define _INTRC_OSC_CLKOUT 0x3FFD //Backwards compatability to 16F62X
196 #define _INTRC_OSC_NOCLKOUT 0x3FFC //Backwards compatability to 16F62X
197 #define _EXTCLK_OSC 0x3FEF
198 #define _HS_OSC 0x3FEE
199 #define _XT_OSC 0x3FED
200 #define _LP_OSC 0x3FEC
204 // ----- CCP1CON bits --------------------
207 unsigned char CCP1M0:1;
208 unsigned char CCP1M1:1;
209 unsigned char CCP1M2:1;
210 unsigned char CCP1M3:1;
211 unsigned char CCP1Y:1;
212 unsigned char CCP1X:1;
217 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
219 #ifndef NO_BIT_DEFINES
220 #define CCP1M0 CCP1CON_bits.CCP1M0
221 #define CCP1M1 CCP1CON_bits.CCP1M1
222 #define CCP1M2 CCP1CON_bits.CCP1M2
223 #define CCP1M3 CCP1CON_bits.CCP1M3
224 #define CCP1Y CCP1CON_bits.CCP1Y
225 #define CCP1X CCP1CON_bits.CCP1X
226 #endif /* NO_BIT_DEFINES */
228 // ----- CMCON bits --------------------
235 unsigned char C1INV:1;
236 unsigned char C2INV:1;
237 unsigned char C1OUT:1;
238 unsigned char C2OUT:1;
241 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
243 #ifndef NO_BIT_DEFINES
244 #define CM0 CMCON_bits.CM0
245 #define CM1 CMCON_bits.CM1
246 #define CM2 CMCON_bits.CM2
247 #define CIS CMCON_bits.CIS
248 #define C1INV CMCON_bits.C1INV
249 #define C2INV CMCON_bits.C2INV
250 #define C1OUT CMCON_bits.C1OUT
251 #define C2OUT CMCON_bits.C2OUT
252 #endif /* NO_BIT_DEFINES */
254 // ----- EECON1 bits --------------------
259 unsigned char WREN:1;
260 unsigned char WRERR:1;
267 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
269 #ifndef NO_BIT_DEFINES
270 #define RD EECON1_bits.RD
271 #define WR EECON1_bits.WR
272 #define WREN EECON1_bits.WREN
273 #define WRERR EECON1_bits.WRERR
274 #endif /* NO_BIT_DEFINES */
276 // ----- INTCON bits --------------------
279 unsigned char RBIF:1;
280 unsigned char INTF:1;
281 unsigned char T0IF:1;
282 unsigned char RBIE:1;
283 unsigned char INTE:1;
284 unsigned char T0IE:1;
285 unsigned char PEIE:1;
289 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
291 #ifndef NO_BIT_DEFINES
292 #define RBIF INTCON_bits.RBIF
293 #define INTF INTCON_bits.INTF
294 #define T0IF INTCON_bits.T0IF
295 #define RBIE INTCON_bits.RBIE
296 #define INTE INTCON_bits.INTE
297 #define T0IE INTCON_bits.T0IE
298 #define PEIE INTCON_bits.PEIE
299 #define GIE INTCON_bits.GIE
300 #endif /* NO_BIT_DEFINES */
302 // ----- OPTION_REG bits --------------------
309 unsigned char T0SE:1;
310 unsigned char T0CS:1;
311 unsigned char INTEDG:1;
312 unsigned char NOT_RBPU:1;
314 } __OPTION_REG_bits_t;
315 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
317 #ifndef NO_BIT_DEFINES
318 #define PS0 OPTION_REG_bits.PS0
319 #define PS1 OPTION_REG_bits.PS1
320 #define PS2 OPTION_REG_bits.PS2
321 #define PSA OPTION_REG_bits.PSA
322 #define T0SE OPTION_REG_bits.T0SE
323 #define T0CS OPTION_REG_bits.T0CS
324 #define INTEDG OPTION_REG_bits.INTEDG
325 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
326 #endif /* NO_BIT_DEFINES */
328 // ----- PCON bits --------------------
331 unsigned char NOT_BO:1;
332 unsigned char NOT_POR:1;
334 unsigned char OSCF:1;
341 unsigned char NOT_BOR:1;
351 unsigned char NOT_BOD:1;
361 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
363 #ifndef NO_BIT_DEFINES
364 #define NOT_BO PCON_bits.NOT_BO
365 #define NOT_BOR PCON_bits.NOT_BOR
366 #define NOT_BOD PCON_bits.NOT_BOD
367 #define NOT_POR PCON_bits.NOT_POR
368 #define OSCF PCON_bits.OSCF
369 #endif /* NO_BIT_DEFINES */
371 // ----- PIE1 bits --------------------
374 unsigned char TMR1IE:1;
375 unsigned char TMR2IE:1;
376 unsigned char CCP1IE:1;
378 unsigned char TXIE:1;
379 unsigned char RCIE:1;
380 unsigned char CMIE:1;
381 unsigned char EEIE:1;
384 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
386 #ifndef NO_BIT_DEFINES
387 #define TMR1IE PIE1_bits.TMR1IE
388 #define TMR2IE PIE1_bits.TMR2IE
389 #define CCP1IE PIE1_bits.CCP1IE
390 #define TXIE PIE1_bits.TXIE
391 #define RCIE PIE1_bits.RCIE
392 #define CMIE PIE1_bits.CMIE
393 #define EEIE PIE1_bits.EEIE
394 #endif /* NO_BIT_DEFINES */
396 // ----- PIR1 bits --------------------
399 unsigned char TMR1IF:1;
400 unsigned char TMR2IF:1;
401 unsigned char CCP1IF:1;
403 unsigned char TXIF:1;
404 unsigned char RCIF:1;
405 unsigned char CMIF:1;
406 unsigned char EEIF:1;
409 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
411 #ifndef NO_BIT_DEFINES
412 #define TMR1IF PIR1_bits.TMR1IF
413 #define TMR2IF PIR1_bits.TMR2IF
414 #define CCP1IF PIR1_bits.CCP1IF
415 #define TXIF PIR1_bits.TXIF
416 #define RCIF PIR1_bits.RCIF
417 #define CMIF PIR1_bits.CMIF
418 #define EEIF PIR1_bits.EEIF
419 #endif /* NO_BIT_DEFINES */
421 // ----- PORTA bits --------------------
434 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
436 #ifndef NO_BIT_DEFINES
437 #define RA0 PORTA_bits.RA0
438 #define RA1 PORTA_bits.RA1
439 #define RA2 PORTA_bits.RA2
440 #define RA3 PORTA_bits.RA3
441 #define RA4 PORTA_bits.RA4
442 #define RA5 PORTA_bits.RA5
443 #define RA6 PORTA_bits.RA6
444 #define RA7 PORTA_bits.RA7
445 #endif /* NO_BIT_DEFINES */
447 // ----- PORTB bits --------------------
460 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
462 #ifndef NO_BIT_DEFINES
463 #define RB0 PORTB_bits.RB0
464 #define RB1 PORTB_bits.RB1
465 #define RB2 PORTB_bits.RB2
466 #define RB3 PORTB_bits.RB3
467 #define RB4 PORTB_bits.RB4
468 #define RB5 PORTB_bits.RB5
469 #define RB6 PORTB_bits.RB6
470 #define RB7 PORTB_bits.RB7
471 #endif /* NO_BIT_DEFINES */
473 // ----- RCSTA bits --------------------
476 unsigned char RX9D:1;
477 unsigned char OERR:1;
478 unsigned char FERR:1;
479 unsigned char ADEN:1;
480 unsigned char CREN:1;
481 unsigned char SREN:1;
483 unsigned char SPEN:1;
486 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
488 #ifndef NO_BIT_DEFINES
489 #define RX9D RCSTA_bits.RX9D
490 #define OERR RCSTA_bits.OERR
491 #define FERR RCSTA_bits.FERR
492 #define ADEN RCSTA_bits.ADEN
493 #define CREN RCSTA_bits.CREN
494 #define SREN RCSTA_bits.SREN
495 #define RX9 RCSTA_bits.RX9
496 #define SPEN RCSTA_bits.SPEN
497 #endif /* NO_BIT_DEFINES */
499 // ----- STATUS bits --------------------
505 unsigned char NOT_PD:1;
506 unsigned char NOT_TO:1;
512 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
514 #ifndef NO_BIT_DEFINES
515 #define C STATUS_bits.C
516 #define DC STATUS_bits.DC
517 #define Z STATUS_bits.Z
518 #define NOT_PD STATUS_bits.NOT_PD
519 #define NOT_TO STATUS_bits.NOT_TO
520 #define RP0 STATUS_bits.RP0
521 #define RP1 STATUS_bits.RP1
522 #define IRP STATUS_bits.IRP
523 #endif /* NO_BIT_DEFINES */
525 // ----- T1CON bits --------------------
528 unsigned char TMR1ON:1;
529 unsigned char TMR1CS:1;
530 unsigned char NOT_T1SYNC:1;
531 unsigned char T1OSCEN:1;
532 unsigned char T1CKPS0:1;
533 unsigned char T1CKPS1:1;
538 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
540 #ifndef NO_BIT_DEFINES
541 #define TMR1ON T1CON_bits.TMR1ON
542 #define TMR1CS T1CON_bits.TMR1CS
543 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
544 #define T1OSCEN T1CON_bits.T1OSCEN
545 #define T1CKPS0 T1CON_bits.T1CKPS0
546 #define T1CKPS1 T1CON_bits.T1CKPS1
547 #endif /* NO_BIT_DEFINES */
549 // ----- T2CON bits --------------------
552 unsigned char T2CKPS0:1;
553 unsigned char T2CKPS1:1;
554 unsigned char TMR2ON:1;
555 unsigned char TOUTPS0:1;
556 unsigned char TOUTPS1:1;
557 unsigned char TOUTPS2:1;
558 unsigned char TOUTPS3:1;
562 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
564 #ifndef NO_BIT_DEFINES
565 #define T2CKPS0 T2CON_bits.T2CKPS0
566 #define T2CKPS1 T2CON_bits.T2CKPS1
567 #define TMR2ON T2CON_bits.TMR2ON
568 #define TOUTPS0 T2CON_bits.TOUTPS0
569 #define TOUTPS1 T2CON_bits.TOUTPS1
570 #define TOUTPS2 T2CON_bits.TOUTPS2
571 #define TOUTPS3 T2CON_bits.TOUTPS3
572 #endif /* NO_BIT_DEFINES */
574 // ----- TRISA bits --------------------
577 unsigned char TRISA0:1;
578 unsigned char TRISA1:1;
579 unsigned char TRISA2:1;
580 unsigned char TRISA3:1;
581 unsigned char TRISA4:1;
582 unsigned char TRISA5:1;
583 unsigned char TRISA6:1;
584 unsigned char TRISA7:1;
587 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
589 #ifndef NO_BIT_DEFINES
590 #define TRISA0 TRISA_bits.TRISA0
591 #define TRISA1 TRISA_bits.TRISA1
592 #define TRISA2 TRISA_bits.TRISA2
593 #define TRISA3 TRISA_bits.TRISA3
594 #define TRISA4 TRISA_bits.TRISA4
595 #define TRISA5 TRISA_bits.TRISA5
596 #define TRISA6 TRISA_bits.TRISA6
597 #define TRISA7 TRISA_bits.TRISA7
598 #endif /* NO_BIT_DEFINES */
600 // ----- TRISB bits --------------------
603 unsigned char TRISB0:1;
604 unsigned char TRISB1:1;
605 unsigned char TRISB2:1;
606 unsigned char TRISB3:1;
607 unsigned char TRISB4:1;
608 unsigned char TRISB5:1;
609 unsigned char TRISB6:1;
610 unsigned char TRISB7:1;
613 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
615 #ifndef NO_BIT_DEFINES
616 #define TRISB0 TRISB_bits.TRISB0
617 #define TRISB1 TRISB_bits.TRISB1
618 #define TRISB2 TRISB_bits.TRISB2
619 #define TRISB3 TRISB_bits.TRISB3
620 #define TRISB4 TRISB_bits.TRISB4
621 #define TRISB5 TRISB_bits.TRISB5
622 #define TRISB6 TRISB_bits.TRISB6
623 #define TRISB7 TRISB_bits.TRISB7
624 #endif /* NO_BIT_DEFINES */
626 // ----- TXSTA bits --------------------
629 unsigned char TX9D:1;
630 unsigned char TRMT:1;
631 unsigned char BRGH:1;
633 unsigned char SYNC:1;
634 unsigned char TXEN:1;
636 unsigned char CSRC:1;
639 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
641 #ifndef NO_BIT_DEFINES
642 #define TX9D TXSTA_bits.TX9D
643 #define TRMT TXSTA_bits.TRMT
644 #define BRGH TXSTA_bits.BRGH
645 #define SYNC TXSTA_bits.SYNC
646 #define TXEN TXSTA_bits.TXEN
647 #define TX9 TXSTA_bits.TX9
648 #define CSRC TXSTA_bits.CSRC
649 #endif /* NO_BIT_DEFINES */
651 // ----- VRCON bits --------------------
660 unsigned char VROE:1;
661 unsigned char VREN:1;
664 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
666 #ifndef NO_BIT_DEFINES
667 #define VR0 VRCON_bits.VR0
668 #define VR1 VRCON_bits.VR1
669 #define VR2 VRCON_bits.VR2
670 #define VR3 VRCON_bits.VR3
671 #define VRR VRCON_bits.VRR
672 #define VROE VRCON_bits.VROE
673 #define VREN VRCON_bits.VREN
674 #endif /* NO_BIT_DEFINES */