2 // Register Declarations for Microchip 16F627A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define TMR2_ADDR 0x0011
42 #define T2CON_ADDR 0x0012
43 #define CCPR1L_ADDR 0x0015
44 #define CCPR1H_ADDR 0x0016
45 #define CCP1CON_ADDR 0x0017
46 #define RCSTA_ADDR 0x0018
47 #define TXREG_ADDR 0x0019
48 #define RCREG_ADDR 0x001A
49 #define CMCON_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define PIE1_ADDR 0x008C
54 #define PCON_ADDR 0x008E
55 #define PR2_ADDR 0x0092
56 #define TXSTA_ADDR 0x0098
57 #define SPBRG_ADDR 0x0099
58 #define EEDATA_ADDR 0x009A
59 #define EEADR_ADDR 0x009B
60 #define EECON1_ADDR 0x009C
61 #define EECON2_ADDR 0x009D
62 #define VRCON_ADDR 0x009F
65 // Memory organization.
68 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
69 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
70 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
71 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
72 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
73 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
74 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
75 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
76 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
77 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
78 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
79 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
80 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
81 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
82 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
83 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
84 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
85 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
86 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
87 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
88 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
89 #pragma memmap CMCON_ADDR CMCON_ADDR SFR 0x000 // CMCON
90 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
91 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
92 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
93 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
94 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
95 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
96 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
97 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
98 #pragma memmap EEDATA_ADDR EEDATA_ADDR SFR 0x000 // EEDATA
99 #pragma memmap EEADR_ADDR EEADR_ADDR SFR 0x000 // EEADR
100 #pragma memmap EECON1_ADDR EECON1_ADDR SFR 0x000 // EECON1
101 #pragma memmap EECON2_ADDR EECON2_ADDR SFR 0x000 // EECON2
102 #pragma memmap VRCON_ADDR VRCON_ADDR SFR 0x000 // VRCON
106 // P16F627A.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
109 // This header file defines configurations, registers, and other useful bits of
110 // information for the PIC16F627A microcontroller. These names are taken to match
111 // the data sheets as closely as possible.
113 // Note that the processor must be selected before this file is
114 // included. The processor may be selected the following ways:
116 // 1. Command line switch:
117 // C:\ MPASM MYFILE.ASM /PIC16F627A
118 // 2. LIST directive in the source file
120 // 3. Processor Type entry in the MPASM full-screen interface
122 //==========================================================================
126 //==========================================================================
129 //1.01 14 Nov 2002 Updated to reflect BOD terminology changed to BOR
130 //1.00 22 Aug 2002 Initial Release
132 //==========================================================================
136 //==========================================================================
139 // MESSG "Processor-header file mismatch. Verify selected processor."
142 //==========================================================================
144 // Register Definitions
146 //==========================================================================
151 //----- Register Files------------------------------------------------------
153 extern data __at (INDF_ADDR) volatile char INDF;
154 extern sfr __at (TMR0_ADDR) TMR0;
155 extern data __at (PCL_ADDR) volatile char PCL;
156 extern sfr __at (STATUS_ADDR) STATUS;
157 extern sfr __at (FSR_ADDR) FSR;
158 extern sfr __at (PORTA_ADDR) PORTA;
159 extern sfr __at (PORTB_ADDR) PORTB;
160 extern sfr __at (PCLATH_ADDR) PCLATH;
161 extern sfr __at (INTCON_ADDR) INTCON;
162 extern sfr __at (PIR1_ADDR) PIR1;
163 extern sfr __at (TMR1L_ADDR) TMR1L;
164 extern sfr __at (TMR1H_ADDR) TMR1H;
165 extern sfr __at (T1CON_ADDR) T1CON;
166 extern sfr __at (TMR2_ADDR) TMR2;
167 extern sfr __at (T2CON_ADDR) T2CON;
168 extern sfr __at (CCPR1L_ADDR) CCPR1L;
169 extern sfr __at (CCPR1H_ADDR) CCPR1H;
170 extern sfr __at (CCP1CON_ADDR) CCP1CON;
171 extern sfr __at (RCSTA_ADDR) RCSTA;
172 extern sfr __at (TXREG_ADDR) TXREG;
173 extern sfr __at (RCREG_ADDR) RCREG;
174 extern sfr __at (CMCON_ADDR) CMCON;
176 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
177 extern sfr __at (TRISA_ADDR) TRISA;
178 extern sfr __at (TRISB_ADDR) TRISB;
179 extern sfr __at (PIE1_ADDR) PIE1;
180 extern sfr __at (PCON_ADDR) PCON;
181 extern sfr __at (PR2_ADDR) PR2;
182 extern sfr __at (TXSTA_ADDR) TXSTA;
183 extern sfr __at (SPBRG_ADDR) SPBRG;
184 extern sfr __at (EEDATA_ADDR) EEDATA;
185 extern sfr __at (EEADR_ADDR) EEADR;
186 extern sfr __at (EECON1_ADDR) EECON1;
187 extern sfr __at (EECON2_ADDR) EECON2;
188 extern sfr __at (VRCON_ADDR) VRCON;
190 //----- STATUS Bits --------------------------------------------------------
193 //----- INTCON Bits --------------------------------------------------------
196 //----- PIR1 Bits ----------------------------------------------------------
199 //----- T1CON Bits ---------------------------------------------------------
201 //----- T2CON Bits ---------------------------------------------------------
203 //----- CCP1CON Bits ---------------------------------------------------------
205 //----- RCSTA Bits ---------------------------------------------------------
207 //----- CMCON Bits ---------------------------------------------------------
210 //----- OPTION Bits --------------------------------------------------------
213 //----- PIE1 Bits ----------------------------------------------------------
216 //----- PCON Bits ----------------------------------------------------------
219 //----- TXSTA Bits ----------------------------------------------------------
221 //----- EECON1 Bits ---------------------------------------------------------
223 //----- VRCON Bits ---------------------------------------------------------
226 //==========================================================================
230 //==========================================================================
233 // __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E'
234 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E'
235 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F'
236 // __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF'
238 //==========================================================================
240 // Configuration Bits
242 //==========================================================================
244 #define _BODEN_ON 0x3FFF //Backwards compatability to 16F62X
245 #define _BODEN_OFF 0x3FBF //Backwards compatability to 16F62X
246 #define _BOREN_ON 0x3FFF
247 #define _BOREN_OFF 0x3FBF
248 #define _CP_ON 0x1FFF
249 #define _CP_OFF 0x3FFF
250 #define _DATA_CP_ON 0x3EFF
251 #define _DATA_CP_OFF 0x3FFF
252 #define _PWRTE_OFF 0x3FFF
253 #define _PWRTE_ON 0x3FF7
254 #define _WDT_ON 0x3FFF
255 #define _WDT_OFF 0x3FFB
256 #define _LVP_ON 0x3FFF
257 #define _LVP_OFF 0x3F7F
258 #define _MCLRE_ON 0x3FFF
259 #define _MCLRE_OFF 0x3FDF
260 #define _RC_OSC_CLKOUT 0x3FFF
261 #define _RC_OSC_NOCLKOUT 0x3FFE
262 #define _ER_OSC_CLKOUT 0x3FFF //Backwards compatability to 16F62X
263 #define _ER_OSC_NOCLKOUT 0x3FFE //Backwards compatability to 16F62X
264 #define _INTOSC_OSC_CLKOUT 0x3FFD
265 #define _INTOSC_OSC_NOCLKOUT 0x3FFC
266 #define _INTRC_OSC_CLKOUT 0x3FFD //Backwards compatability to 16F62X
267 #define _INTRC_OSC_NOCLKOUT 0x3FFC //Backwards compatability to 16F62X
268 #define _EXTCLK_OSC 0x3FEF
269 #define _HS_OSC 0x3FEE
270 #define _XT_OSC 0x3FED
271 #define _LP_OSC 0x3FEC
275 // ----- CCP1CON bits --------------------
278 unsigned char CCP1M0:1;
279 unsigned char CCP1M1:1;
280 unsigned char CCP1M2:1;
281 unsigned char CCP1M3:1;
282 unsigned char CCP1Y:1;
283 unsigned char CCP1X:1;
288 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
290 #define CCP1M0 CCP1CON_bits.CCP1M0
291 #define CCP1M1 CCP1CON_bits.CCP1M1
292 #define CCP1M2 CCP1CON_bits.CCP1M2
293 #define CCP1M3 CCP1CON_bits.CCP1M3
294 #define CCP1Y CCP1CON_bits.CCP1Y
295 #define CCP1X CCP1CON_bits.CCP1X
297 // ----- CMCON bits --------------------
304 unsigned char C1INV:1;
305 unsigned char C2INV:1;
306 unsigned char C1OUT:1;
307 unsigned char C2OUT:1;
310 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
312 #define CM0 CMCON_bits.CM0
313 #define CM1 CMCON_bits.CM1
314 #define CM2 CMCON_bits.CM2
315 #define CIS CMCON_bits.CIS
316 #define C1INV CMCON_bits.C1INV
317 #define C2INV CMCON_bits.C2INV
318 #define C1OUT CMCON_bits.C1OUT
319 #define C2OUT CMCON_bits.C2OUT
321 // ----- EECON1 bits --------------------
326 unsigned char WREN:1;
327 unsigned char WRERR:1;
334 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
336 #define RD EECON1_bits.RD
337 #define WR EECON1_bits.WR
338 #define WREN EECON1_bits.WREN
339 #define WRERR EECON1_bits.WRERR
341 // ----- INTCON bits --------------------
344 unsigned char RBIF:1;
345 unsigned char INTF:1;
346 unsigned char T0IF:1;
347 unsigned char RBIE:1;
348 unsigned char INTE:1;
349 unsigned char T0IE:1;
350 unsigned char PEIE:1;
354 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
356 #define RBIF INTCON_bits.RBIF
357 #define INTF INTCON_bits.INTF
358 #define T0IF INTCON_bits.T0IF
359 #define RBIE INTCON_bits.RBIE
360 #define INTE INTCON_bits.INTE
361 #define T0IE INTCON_bits.T0IE
362 #define PEIE INTCON_bits.PEIE
363 #define GIE INTCON_bits.GIE
365 // ----- OPTION_REG bits --------------------
372 unsigned char T0SE:1;
373 unsigned char T0CS:1;
374 unsigned char INTEDG:1;
375 unsigned char NOT_RBPU:1;
377 } __OPTION_REG_bits_t;
378 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
380 #define PS0 OPTION_REG_bits.PS0
381 #define PS1 OPTION_REG_bits.PS1
382 #define PS2 OPTION_REG_bits.PS2
383 #define PSA OPTION_REG_bits.PSA
384 #define T0SE OPTION_REG_bits.T0SE
385 #define T0CS OPTION_REG_bits.T0CS
386 #define INTEDG OPTION_REG_bits.INTEDG
387 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
389 // ----- PCON bits --------------------
392 unsigned char NOT_BO:1;
393 unsigned char NOT_POR:1;
395 unsigned char OSCF:1;
402 unsigned char NOT_BOR:1;
412 unsigned char NOT_BOD:1;
422 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
424 #define NOT_BO PCON_bits.NOT_BO
425 #define NOT_BOR PCON_bits.NOT_BOR
426 #define NOT_BOD PCON_bits.NOT_BOD
427 #define NOT_POR PCON_bits.NOT_POR
428 #define OSCF PCON_bits.OSCF
430 // ----- PIE1 bits --------------------
433 unsigned char TMR1IE:1;
434 unsigned char TMR2IE:1;
435 unsigned char CCP1IE:1;
437 unsigned char TXIE:1;
438 unsigned char RCIE:1;
439 unsigned char CMIE:1;
440 unsigned char EEIE:1;
443 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
445 #define TMR1IE PIE1_bits.TMR1IE
446 #define TMR2IE PIE1_bits.TMR2IE
447 #define CCP1IE PIE1_bits.CCP1IE
448 #define TXIE PIE1_bits.TXIE
449 #define RCIE PIE1_bits.RCIE
450 #define CMIE PIE1_bits.CMIE
451 #define EEIE PIE1_bits.EEIE
453 // ----- PIR1 bits --------------------
456 unsigned char TMR1IF:1;
457 unsigned char TMR2IF:1;
458 unsigned char CCP1IF:1;
460 unsigned char TXIF:1;
461 unsigned char RCIF:1;
462 unsigned char CMIF:1;
463 unsigned char EEIF:1;
466 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
468 #define TMR1IF PIR1_bits.TMR1IF
469 #define TMR2IF PIR1_bits.TMR2IF
470 #define CCP1IF PIR1_bits.CCP1IF
471 #define TXIF PIR1_bits.TXIF
472 #define RCIF PIR1_bits.RCIF
473 #define CMIF PIR1_bits.CMIF
474 #define EEIF PIR1_bits.EEIF
476 // ----- RCSTA bits --------------------
479 unsigned char RX9D:1;
480 unsigned char OERR:1;
481 unsigned char FERR:1;
482 unsigned char ADEN:1;
483 unsigned char CREN:1;
484 unsigned char SREN:1;
486 unsigned char SPEN:1;
489 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
491 #define RX9D RCSTA_bits.RX9D
492 #define OERR RCSTA_bits.OERR
493 #define FERR RCSTA_bits.FERR
494 #define ADEN RCSTA_bits.ADEN
495 #define CREN RCSTA_bits.CREN
496 #define SREN RCSTA_bits.SREN
497 #define RX9 RCSTA_bits.RX9
498 #define SPEN RCSTA_bits.SPEN
500 // ----- STATUS bits --------------------
506 unsigned char NOT_PD:1;
507 unsigned char NOT_TO:1;
513 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
515 #define C STATUS_bits.C
516 #define DC STATUS_bits.DC
517 #define Z STATUS_bits.Z
518 #define NOT_PD STATUS_bits.NOT_PD
519 #define NOT_TO STATUS_bits.NOT_TO
520 #define RP0 STATUS_bits.RP0
521 #define RP1 STATUS_bits.RP1
522 #define IRP STATUS_bits.IRP
524 // ----- T1CON bits --------------------
527 unsigned char TMR1ON:1;
528 unsigned char TMR1CS:1;
529 unsigned char NOT_T1SYNC:1;
530 unsigned char T1OSCEN:1;
531 unsigned char T1CKPS0:1;
532 unsigned char T1CKPS1:1;
537 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
539 #define TMR1ON T1CON_bits.TMR1ON
540 #define TMR1CS T1CON_bits.TMR1CS
541 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
542 #define T1OSCEN T1CON_bits.T1OSCEN
543 #define T1CKPS0 T1CON_bits.T1CKPS0
544 #define T1CKPS1 T1CON_bits.T1CKPS1
546 // ----- T2CON bits --------------------
549 unsigned char T2CKPS0:1;
550 unsigned char T2CKPS1:1;
551 unsigned char TMR2ON:1;
552 unsigned char TOUTPS0:1;
553 unsigned char TOUTPS1:1;
554 unsigned char TOUTPS2:1;
555 unsigned char TOUTPS3:1;
559 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
561 #define T2CKPS0 T2CON_bits.T2CKPS0
562 #define T2CKPS1 T2CON_bits.T2CKPS1
563 #define TMR2ON T2CON_bits.TMR2ON
564 #define TOUTPS0 T2CON_bits.TOUTPS0
565 #define TOUTPS1 T2CON_bits.TOUTPS1
566 #define TOUTPS2 T2CON_bits.TOUTPS2
567 #define TOUTPS3 T2CON_bits.TOUTPS3
569 // ----- TXSTA bits --------------------
572 unsigned char TX9D:1;
573 unsigned char TRMT:1;
574 unsigned char BRGH:1;
576 unsigned char SYNC:1;
577 unsigned char TXEN:1;
579 unsigned char CSRC:1;
582 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
584 #define TX9D TXSTA_bits.TX9D
585 #define TRMT TXSTA_bits.TRMT
586 #define BRGH TXSTA_bits.BRGH
587 #define SYNC TXSTA_bits.SYNC
588 #define TXEN TXSTA_bits.TXEN
589 #define TX9 TXSTA_bits.TX9
590 #define CSRC TXSTA_bits.CSRC
592 // ----- VRCON bits --------------------
601 unsigned char VROE:1;
602 unsigned char VREN:1;
605 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
607 #define VR0 VRCON_bits.VR0
608 #define VR1 VRCON_bits.VR1
609 #define VR2 VRCON_bits.VR2
610 #define VR3 VRCON_bits.VR3
611 #define VRR VRCON_bits.VRR
612 #define VROE VRCON_bits.VROE
613 #define VREN VRCON_bits.VREN