2 // Register Declarations for Microchip 16F627A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define TMR2_ADDR 0x0011
42 #define T2CON_ADDR 0x0012
43 #define CCPR1L_ADDR 0x0015
44 #define CCPR1H_ADDR 0x0016
45 #define CCP1CON_ADDR 0x0017
46 #define RCSTA_ADDR 0x0018
47 #define TXREG_ADDR 0x0019
48 #define RCREG_ADDR 0x001A
49 #define CMCON_ADDR 0x001F
50 #define OPTION_REG_ADDR 0x0081
51 #define TRISA_ADDR 0x0085
52 #define TRISB_ADDR 0x0086
53 #define PIE1_ADDR 0x008C
54 #define PCON_ADDR 0x008E
55 #define PR2_ADDR 0x0092
56 #define TXSTA_ADDR 0x0098
57 #define SPBRG_ADDR 0x0099
58 #define EEDATA_ADDR 0x009A
59 #define EEADR_ADDR 0x009B
60 #define EECON1_ADDR 0x009C
61 #define EECON2_ADDR 0x009D
62 #define VRCON_ADDR 0x009F
65 // Memory organization.
71 // P16F627A.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
74 // This header file defines configurations, registers, and other useful bits of
75 // information for the PIC16F627A microcontroller. These names are taken to match
76 // the data sheets as closely as possible.
78 // Note that the processor must be selected before this file is
79 // included. The processor may be selected the following ways:
81 // 1. Command line switch:
82 // C:\ MPASM MYFILE.ASM /PIC16F627A
83 // 2. LIST directive in the source file
85 // 3. Processor Type entry in the MPASM full-screen interface
87 //==========================================================================
91 //==========================================================================
94 //1.01 14 Nov 2002 Updated to reflect BOD terminology changed to BOR
95 //1.00 22 Aug 2002 Initial Release
97 //==========================================================================
101 //==========================================================================
104 // MESSG "Processor-header file mismatch. Verify selected processor."
107 //==========================================================================
109 // Register Definitions
111 //==========================================================================
116 //----- Register Files------------------------------------------------------
118 extern __sfr __at (INDF_ADDR) INDF;
119 extern __sfr __at (TMR0_ADDR) TMR0;
120 extern __sfr __at (PCL_ADDR) PCL;
121 extern __sfr __at (STATUS_ADDR) STATUS;
122 extern __sfr __at (FSR_ADDR) FSR;
123 extern __sfr __at (PORTA_ADDR) PORTA;
124 extern __sfr __at (PORTB_ADDR) PORTB;
125 extern __sfr __at (PCLATH_ADDR) PCLATH;
126 extern __sfr __at (INTCON_ADDR) INTCON;
127 extern __sfr __at (PIR1_ADDR) PIR1;
128 extern __sfr __at (TMR1L_ADDR) TMR1L;
129 extern __sfr __at (TMR1H_ADDR) TMR1H;
130 extern __sfr __at (T1CON_ADDR) T1CON;
131 extern __sfr __at (TMR2_ADDR) TMR2;
132 extern __sfr __at (T2CON_ADDR) T2CON;
133 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
134 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
135 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
136 extern __sfr __at (RCSTA_ADDR) RCSTA;
137 extern __sfr __at (TXREG_ADDR) TXREG;
138 extern __sfr __at (RCREG_ADDR) RCREG;
139 extern __sfr __at (CMCON_ADDR) CMCON;
141 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
142 extern __sfr __at (TRISA_ADDR) TRISA;
143 extern __sfr __at (TRISB_ADDR) TRISB;
144 extern __sfr __at (PIE1_ADDR) PIE1;
145 extern __sfr __at (PCON_ADDR) PCON;
146 extern __sfr __at (PR2_ADDR) PR2;
147 extern __sfr __at (TXSTA_ADDR) TXSTA;
148 extern __sfr __at (SPBRG_ADDR) SPBRG;
149 extern __sfr __at (EEDATA_ADDR) EEDATA;
150 extern __sfr __at (EEADR_ADDR) EEADR;
151 extern __sfr __at (EECON1_ADDR) EECON1;
152 extern __sfr __at (EECON2_ADDR) EECON2;
153 extern __sfr __at (VRCON_ADDR) VRCON;
155 //----- STATUS Bits --------------------------------------------------------
158 //----- INTCON Bits --------------------------------------------------------
161 //----- PIR1 Bits ----------------------------------------------------------
164 //----- T1CON Bits ---------------------------------------------------------
166 //----- T2CON Bits ---------------------------------------------------------
168 //----- CCP1CON Bits ---------------------------------------------------------
170 //----- RCSTA Bits ---------------------------------------------------------
172 //----- CMCON Bits ---------------------------------------------------------
175 //----- OPTION Bits --------------------------------------------------------
178 //----- PIE1 Bits ----------------------------------------------------------
181 //----- PCON Bits ----------------------------------------------------------
184 //----- TXSTA Bits ----------------------------------------------------------
186 //----- EECON1 Bits ---------------------------------------------------------
188 //----- VRCON Bits ---------------------------------------------------------
191 //==========================================================================
195 //==========================================================================
198 // __BADRAM H'07'-H'09', H'0D', H'13'-H'14', H'1B'-H'1E'
199 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'91', H'93'-H'97', H'9E'
200 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F', H'150'-H'16F'
201 // __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF'
203 //==========================================================================
205 // Configuration Bits
207 //==========================================================================
209 #define _BODEN_ON 0x3FFF //Backwards compatability to 16F62X
210 #define _BODEN_OFF 0x3FBF //Backwards compatability to 16F62X
211 #define _BOREN_ON 0x3FFF
212 #define _BOREN_OFF 0x3FBF
213 #define _CP_ON 0x1FFF
214 #define _CP_OFF 0x3FFF
215 #define _DATA_CP_ON 0x3EFF
216 #define _DATA_CP_OFF 0x3FFF
217 #define _PWRTE_OFF 0x3FFF
218 #define _PWRTE_ON 0x3FF7
219 #define _WDT_ON 0x3FFF
220 #define _WDT_OFF 0x3FFB
221 #define _LVP_ON 0x3FFF
222 #define _LVP_OFF 0x3F7F
223 #define _MCLRE_ON 0x3FFF
224 #define _MCLRE_OFF 0x3FDF
225 #define _RC_OSC_CLKOUT 0x3FFF
226 #define _RC_OSC_NOCLKOUT 0x3FFE
227 #define _ER_OSC_CLKOUT 0x3FFF //Backwards compatability to 16F62X
228 #define _ER_OSC_NOCLKOUT 0x3FFE //Backwards compatability to 16F62X
229 #define _INTOSC_OSC_CLKOUT 0x3FFD
230 #define _INTOSC_OSC_NOCLKOUT 0x3FFC
231 #define _INTRC_OSC_CLKOUT 0x3FFD //Backwards compatability to 16F62X
232 #define _INTRC_OSC_NOCLKOUT 0x3FFC //Backwards compatability to 16F62X
233 #define _EXTCLK_OSC 0x3FEF
234 #define _HS_OSC 0x3FEE
235 #define _XT_OSC 0x3FED
236 #define _LP_OSC 0x3FEC
240 // ----- CCP1CON bits --------------------
243 unsigned char CCP1M0:1;
244 unsigned char CCP1M1:1;
245 unsigned char CCP1M2:1;
246 unsigned char CCP1M3:1;
247 unsigned char CCP1Y:1;
248 unsigned char CCP1X:1;
253 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
255 #ifndef NO_BIT_DEFINES
256 #define CCP1M0 CCP1CON_bits.CCP1M0
257 #define CCP1M1 CCP1CON_bits.CCP1M1
258 #define CCP1M2 CCP1CON_bits.CCP1M2
259 #define CCP1M3 CCP1CON_bits.CCP1M3
260 #define CCP1Y CCP1CON_bits.CCP1Y
261 #define CCP1X CCP1CON_bits.CCP1X
262 #endif /* NO_BIT_DEFINES */
264 // ----- CMCON bits --------------------
271 unsigned char C1INV:1;
272 unsigned char C2INV:1;
273 unsigned char C1OUT:1;
274 unsigned char C2OUT:1;
277 extern volatile __CMCON_bits_t __at(CMCON_ADDR) CMCON_bits;
279 #ifndef NO_BIT_DEFINES
280 #define CM0 CMCON_bits.CM0
281 #define CM1 CMCON_bits.CM1
282 #define CM2 CMCON_bits.CM2
283 #define CIS CMCON_bits.CIS
284 #define C1INV CMCON_bits.C1INV
285 #define C2INV CMCON_bits.C2INV
286 #define C1OUT CMCON_bits.C1OUT
287 #define C2OUT CMCON_bits.C2OUT
288 #endif /* NO_BIT_DEFINES */
290 // ----- EECON1 bits --------------------
295 unsigned char WREN:1;
296 unsigned char WRERR:1;
303 extern volatile __EECON1_bits_t __at(EECON1_ADDR) EECON1_bits;
305 #ifndef NO_BIT_DEFINES
306 #define RD EECON1_bits.RD
307 #define WR EECON1_bits.WR
308 #define WREN EECON1_bits.WREN
309 #define WRERR EECON1_bits.WRERR
310 #endif /* NO_BIT_DEFINES */
312 // ----- INTCON bits --------------------
315 unsigned char RBIF:1;
316 unsigned char INTF:1;
317 unsigned char T0IF:1;
318 unsigned char RBIE:1;
319 unsigned char INTE:1;
320 unsigned char T0IE:1;
321 unsigned char PEIE:1;
325 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
327 #ifndef NO_BIT_DEFINES
328 #define RBIF INTCON_bits.RBIF
329 #define INTF INTCON_bits.INTF
330 #define T0IF INTCON_bits.T0IF
331 #define RBIE INTCON_bits.RBIE
332 #define INTE INTCON_bits.INTE
333 #define T0IE INTCON_bits.T0IE
334 #define PEIE INTCON_bits.PEIE
335 #define GIE INTCON_bits.GIE
336 #endif /* NO_BIT_DEFINES */
338 // ----- OPTION_REG bits --------------------
345 unsigned char T0SE:1;
346 unsigned char T0CS:1;
347 unsigned char INTEDG:1;
348 unsigned char NOT_RBPU:1;
350 } __OPTION_REG_bits_t;
351 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
353 #ifndef NO_BIT_DEFINES
354 #define PS0 OPTION_REG_bits.PS0
355 #define PS1 OPTION_REG_bits.PS1
356 #define PS2 OPTION_REG_bits.PS2
357 #define PSA OPTION_REG_bits.PSA
358 #define T0SE OPTION_REG_bits.T0SE
359 #define T0CS OPTION_REG_bits.T0CS
360 #define INTEDG OPTION_REG_bits.INTEDG
361 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
362 #endif /* NO_BIT_DEFINES */
364 // ----- PCON bits --------------------
367 unsigned char NOT_BO:1;
368 unsigned char NOT_POR:1;
370 unsigned char OSCF:1;
377 unsigned char NOT_BOR:1;
387 unsigned char NOT_BOD:1;
397 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
399 #ifndef NO_BIT_DEFINES
400 #define NOT_BO PCON_bits.NOT_BO
401 #define NOT_BOR PCON_bits.NOT_BOR
402 #define NOT_BOD PCON_bits.NOT_BOD
403 #define NOT_POR PCON_bits.NOT_POR
404 #define OSCF PCON_bits.OSCF
405 #endif /* NO_BIT_DEFINES */
407 // ----- PIE1 bits --------------------
410 unsigned char TMR1IE:1;
411 unsigned char TMR2IE:1;
412 unsigned char CCP1IE:1;
414 unsigned char TXIE:1;
415 unsigned char RCIE:1;
416 unsigned char CMIE:1;
417 unsigned char EEIE:1;
420 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
422 #ifndef NO_BIT_DEFINES
423 #define TMR1IE PIE1_bits.TMR1IE
424 #define TMR2IE PIE1_bits.TMR2IE
425 #define CCP1IE PIE1_bits.CCP1IE
426 #define TXIE PIE1_bits.TXIE
427 #define RCIE PIE1_bits.RCIE
428 #define CMIE PIE1_bits.CMIE
429 #define EEIE PIE1_bits.EEIE
430 #endif /* NO_BIT_DEFINES */
432 // ----- PIR1 bits --------------------
435 unsigned char TMR1IF:1;
436 unsigned char TMR2IF:1;
437 unsigned char CCP1IF:1;
439 unsigned char TXIF:1;
440 unsigned char RCIF:1;
441 unsigned char CMIF:1;
442 unsigned char EEIF:1;
445 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
447 #ifndef NO_BIT_DEFINES
448 #define TMR1IF PIR1_bits.TMR1IF
449 #define TMR2IF PIR1_bits.TMR2IF
450 #define CCP1IF PIR1_bits.CCP1IF
451 #define TXIF PIR1_bits.TXIF
452 #define RCIF PIR1_bits.RCIF
453 #define CMIF PIR1_bits.CMIF
454 #define EEIF PIR1_bits.EEIF
455 #endif /* NO_BIT_DEFINES */
457 // ----- PORTA bits --------------------
470 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
472 #ifndef NO_BIT_DEFINES
473 #define RA0 PORTA_bits.RA0
474 #define RA1 PORTA_bits.RA1
475 #define RA2 PORTA_bits.RA2
476 #define RA3 PORTA_bits.RA3
477 #define RA4 PORTA_bits.RA4
478 #define RA5 PORTA_bits.RA5
479 #endif /* NO_BIT_DEFINES */
481 // ----- PORTB bits --------------------
494 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
496 #ifndef NO_BIT_DEFINES
497 #define RB0 PORTB_bits.RB0
498 #define RB1 PORTB_bits.RB1
499 #define RB2 PORTB_bits.RB2
500 #define RB3 PORTB_bits.RB3
501 #define RB4 PORTB_bits.RB4
502 #define RB5 PORTB_bits.RB5
503 #define RB6 PORTB_bits.RB6
504 #define RB7 PORTB_bits.RB7
505 #endif /* NO_BIT_DEFINES */
507 // ----- RCSTA bits --------------------
510 unsigned char RX9D:1;
511 unsigned char OERR:1;
512 unsigned char FERR:1;
513 unsigned char ADEN:1;
514 unsigned char CREN:1;
515 unsigned char SREN:1;
517 unsigned char SPEN:1;
520 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
522 #ifndef NO_BIT_DEFINES
523 #define RX9D RCSTA_bits.RX9D
524 #define OERR RCSTA_bits.OERR
525 #define FERR RCSTA_bits.FERR
526 #define ADEN RCSTA_bits.ADEN
527 #define CREN RCSTA_bits.CREN
528 #define SREN RCSTA_bits.SREN
529 #define RX9 RCSTA_bits.RX9
530 #define SPEN RCSTA_bits.SPEN
531 #endif /* NO_BIT_DEFINES */
533 // ----- STATUS bits --------------------
539 unsigned char NOT_PD:1;
540 unsigned char NOT_TO:1;
546 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
548 #ifndef NO_BIT_DEFINES
549 #define C STATUS_bits.C
550 #define DC STATUS_bits.DC
551 #define Z STATUS_bits.Z
552 #define NOT_PD STATUS_bits.NOT_PD
553 #define NOT_TO STATUS_bits.NOT_TO
554 #define RP0 STATUS_bits.RP0
555 #define RP1 STATUS_bits.RP1
556 #define IRP STATUS_bits.IRP
557 #endif /* NO_BIT_DEFINES */
559 // ----- T1CON bits --------------------
562 unsigned char TMR1ON:1;
563 unsigned char TMR1CS:1;
564 unsigned char NOT_T1SYNC:1;
565 unsigned char T1OSCEN:1;
566 unsigned char T1CKPS0:1;
567 unsigned char T1CKPS1:1;
572 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
574 #ifndef NO_BIT_DEFINES
575 #define TMR1ON T1CON_bits.TMR1ON
576 #define TMR1CS T1CON_bits.TMR1CS
577 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
578 #define T1OSCEN T1CON_bits.T1OSCEN
579 #define T1CKPS0 T1CON_bits.T1CKPS0
580 #define T1CKPS1 T1CON_bits.T1CKPS1
581 #endif /* NO_BIT_DEFINES */
583 // ----- T2CON bits --------------------
586 unsigned char T2CKPS0:1;
587 unsigned char T2CKPS1:1;
588 unsigned char TMR2ON:1;
589 unsigned char TOUTPS0:1;
590 unsigned char TOUTPS1:1;
591 unsigned char TOUTPS2:1;
592 unsigned char TOUTPS3:1;
596 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
598 #ifndef NO_BIT_DEFINES
599 #define T2CKPS0 T2CON_bits.T2CKPS0
600 #define T2CKPS1 T2CON_bits.T2CKPS1
601 #define TMR2ON T2CON_bits.TMR2ON
602 #define TOUTPS0 T2CON_bits.TOUTPS0
603 #define TOUTPS1 T2CON_bits.TOUTPS1
604 #define TOUTPS2 T2CON_bits.TOUTPS2
605 #define TOUTPS3 T2CON_bits.TOUTPS3
606 #endif /* NO_BIT_DEFINES */
608 // ----- TRISA bits --------------------
611 unsigned char TRISA0:1;
612 unsigned char TRISA1:1;
613 unsigned char TRISA2:1;
614 unsigned char TRISA3:1;
615 unsigned char TRISA4:1;
616 unsigned char TRISA5:1;
621 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
623 #ifndef NO_BIT_DEFINES
624 #define TRISA0 TRISA_bits.TRISA0
625 #define TRISA1 TRISA_bits.TRISA1
626 #define TRISA2 TRISA_bits.TRISA2
627 #define TRISA3 TRISA_bits.TRISA3
628 #define TRISA4 TRISA_bits.TRISA4
629 #define TRISA5 TRISA_bits.TRISA5
630 #endif /* NO_BIT_DEFINES */
632 // ----- TRISB bits --------------------
635 unsigned char TRISB0:1;
636 unsigned char TRISB1:1;
637 unsigned char TRISB2:1;
638 unsigned char TRISB3:1;
639 unsigned char TRISB4:1;
640 unsigned char TRISB5:1;
641 unsigned char TRISB6:1;
642 unsigned char TRISB7:1;
645 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
647 #ifndef NO_BIT_DEFINES
648 #define TRISB0 TRISB_bits.TRISB0
649 #define TRISB1 TRISB_bits.TRISB1
650 #define TRISB2 TRISB_bits.TRISB2
651 #define TRISB3 TRISB_bits.TRISB3
652 #define TRISB4 TRISB_bits.TRISB4
653 #define TRISB5 TRISB_bits.TRISB5
654 #define TRISB6 TRISB_bits.TRISB6
655 #define TRISB7 TRISB_bits.TRISB7
656 #endif /* NO_BIT_DEFINES */
658 // ----- TXSTA bits --------------------
661 unsigned char TX9D:1;
662 unsigned char TRMT:1;
663 unsigned char BRGH:1;
665 unsigned char SYNC:1;
666 unsigned char TXEN:1;
668 unsigned char CSRC:1;
671 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
673 #ifndef NO_BIT_DEFINES
674 #define TX9D TXSTA_bits.TX9D
675 #define TRMT TXSTA_bits.TRMT
676 #define BRGH TXSTA_bits.BRGH
677 #define SYNC TXSTA_bits.SYNC
678 #define TXEN TXSTA_bits.TXEN
679 #define TX9 TXSTA_bits.TX9
680 #define CSRC TXSTA_bits.CSRC
681 #endif /* NO_BIT_DEFINES */
683 // ----- VRCON bits --------------------
692 unsigned char VROE:1;
693 unsigned char VREN:1;
696 extern volatile __VRCON_bits_t __at(VRCON_ADDR) VRCON_bits;
698 #ifndef NO_BIT_DEFINES
699 #define VR0 VRCON_bits.VR0
700 #define VR1 VRCON_bits.VR1
701 #define VR2 VRCON_bits.VR2
702 #define VR3 VRCON_bits.VR3
703 #define VRR VRCON_bits.VRR
704 #define VROE VRCON_bits.VROE
705 #define VREN VRCON_bits.VREN
706 #endif /* NO_BIT_DEFINES */