2 // Register Declarations for Microchip 16F505 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define OSCCAL_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define OPTION_REG_ADDR 0x0081
39 // Memory organization.
42 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
43 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
44 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
45 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
46 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
47 #pragma memmap OSCCAL_ADDR OSCCAL_ADDR SFR 0x000 // OSCCAL
48 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
49 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
50 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
54 // P16F505.INC Standard Header File, Version 1.10 Microchip Technology, Inc.
57 // This header file defines configurations, registers, and other useful bits of
58 // information for the PIC16F505 microcontroller. These names are taken to match
59 // the data sheets as closely as possible.
61 // Note that the processor must be selected before this file is
62 // included. The processor may be selected the following ways:
64 // 1. Command line switch:
65 // C:\ MPASM MYFILE.ASM /P16F505
66 // 2. LIST directive in the source file
68 // 3. Processor Type entry in the MPASM full-screen interface
70 //==========================================================================
74 //==========================================================================
78 //1.00 12/09/03 Initial Release
79 //1.01 04/14/04 Update for EC osc mode
82 //==========================================================================
86 //==========================================================================
89 // MESSG "Processor-header file mismatch. Verify selected processor."
92 //==========================================================================
94 // Register Definitions
96 //==========================================================================
101 //----- Register Files -----------------------------------------------------
103 extern __data __at (INDF_ADDR) volatile char INDF;
104 extern __sfr __at (TMR0_ADDR) TMR0;
105 extern __data __at (PCL_ADDR) volatile char PCL;
106 extern __sfr __at (STATUS_ADDR) STATUS;
107 extern __sfr __at (FSR_ADDR) FSR;
108 extern __sfr __at (OSCCAL_ADDR) OSCCAL;
109 extern __sfr __at (PORTB_ADDR) PORTB;
110 extern __sfr __at (PORTC_ADDR) PORTC;
111 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG; // not verified
113 //----- STATUS Bits --------------------------------------------------------
116 //----- OPTION Bits --------------------------------------------------------
119 //----- OSCCAL Bits --------------------------------------------------------
122 //==========================================================================
126 //==========================================================================
130 //==========================================================================
132 // Configuration Bits
134 //==========================================================================
136 #define _MCLRE_ON 0x0FFF
137 #define _MCLRE_OFF 0x0FDF
138 #define _CP_ON 0x002F
139 #define _CP_OFF 0x0FFF
140 #define _WDT_ON 0x0FFF
141 #define _WDT_OFF 0x0FF7
142 #define _LP_OSC 0x0FF8
143 #define _XT_OSC 0x0FF9
144 #define _HS_OSC 0x0FFA
145 #define _EC_RB4EN 0x0FFB
146 #define _IntRC_OSC_RB4EN 0x0FFC
147 #define _IntRC_OSC_CLKOUTEN 0x0FFD
148 #define _ExtRC_OSC_RB4EN 0x0FFE
149 #define _ExtRC_OSC_CLKOUTEN 0x0FFF
153 // ----- OPTION_REG bits --------------------
160 unsigned char T0SE:1;
161 unsigned char T0CS:1;
162 unsigned char NOT_RBPU:1;
163 unsigned char NOT_RBWU:1;
165 } __OPTION_REG_bits_t;
166 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
168 #define PS0 OPTION_REG_bits.PS0
169 #define PS1 OPTION_REG_bits.PS1
170 #define PS2 OPTION_REG_bits.PS2
171 #define PSA OPTION_REG_bits.PSA
172 #define T0SE OPTION_REG_bits.T0SE
173 #define T0CS OPTION_REG_bits.T0CS
174 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
175 #define NOT_RBWU OPTION_REG_bits.NOT_RBWU
177 // ----- OSCCAL bits --------------------
181 unsigned char CAL0:1;
182 unsigned char CAL1:1;
183 unsigned char CAL2:1;
184 unsigned char CAL3:1;
185 unsigned char CAL4:1;
186 unsigned char CAL5:1;
187 unsigned char CAL6:1;
190 extern volatile __OSCCAL_bits_t __at(OSCCAL_ADDR) OSCCAL_bits;
192 #define CAL0 OSCCAL_bits.CAL0
193 #define CAL1 OSCCAL_bits.CAL1
194 #define CAL2 OSCCAL_bits.CAL2
195 #define CAL3 OSCCAL_bits.CAL3
196 #define CAL4 OSCCAL_bits.CAL4
197 #define CAL5 OSCCAL_bits.CAL5
198 #define CAL6 OSCCAL_bits.CAL6
200 // ----- STATUS bits --------------------
206 unsigned char NOT_PD:1;
207 unsigned char NOT_TO:1;
210 unsigned char RBWUF:1;
213 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
215 #define C STATUS_bits.C
216 #define DC STATUS_bits.DC
217 #define Z STATUS_bits.Z
218 #define NOT_PD STATUS_bits.NOT_PD
219 #define NOT_TO STATUS_bits.NOT_TO
220 #define PA0 STATUS_bits.PA0
221 #define RBWUF STATUS_bits.RBWUF