2 // Register Declarations for Microchip 16C926 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define TMR1L_ADDR 0x000E
42 #define TMR1H_ADDR 0x000F
43 #define T1CON_ADDR 0x0010
44 #define TMR2_ADDR 0x0011
45 #define T2CON_ADDR 0x0012
46 #define SSPBUF_ADDR 0x0013
47 #define SSPCON_ADDR 0x0014
48 #define CCPR1L_ADDR 0x0015
49 #define CCPR1H_ADDR 0x0016
50 #define CCP1CON_ADDR 0x0017
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISB_ADDR 0x0086
56 #define TRISC_ADDR 0x0087
57 #define TRISD_ADDR 0x0088
58 #define TRISE_ADDR 0x0089
59 #define PIE1_ADDR 0x008C
60 #define PCON_ADDR 0x008E
61 #define PR2_ADDR 0x0092
62 #define SSPADD_ADDR 0x0093
63 #define SSPSTAT_ADDR 0x0094
64 #define ADRESL_ADDR 0x009E
65 #define ADCON1_ADDR 0x009F
66 #define PORTF_ADDR 0x0107
67 #define PORTG_ADDR 0x0108
68 #define PMCON1_ADDR 0x010C
69 #define LCDSE_ADDR 0x010D
70 #define LCDPS_ADDR 0x010E
71 #define LCDCON_ADDR 0x010F
72 #define LCDD00_ADDR 0x0110
73 #define LCDD01_ADDR 0x0111
74 #define LCDD02_ADDR 0x0112
75 #define LCDD03_ADDR 0x0113
76 #define LCDD04_ADDR 0x0114
77 #define LCDD05_ADDR 0x0115
78 #define LCDD06_ADDR 0x0116
79 #define LCDD07_ADDR 0x0117
80 #define LCDD08_ADDR 0x0118
81 #define LCDD09_ADDR 0x0119
82 #define LCDD10_ADDR 0x011A
83 #define LCDD11_ADDR 0x011B
84 #define LCDD12_ADDR 0x011C
85 #define LCDD13_ADDR 0x011D
86 #define LCDD14_ADDR 0x011E
87 #define LCDD15_ADDR 0x011F
88 #define TRISF_ADDR 0x0187
89 #define TRISG_ADDR 0x0188
90 #define PMDATA_ADDR 0x018C
91 #define PMDATH_ADDR 0x018D
92 #define PMADR_ADDR 0x018E
93 #define PMADRH_ADDR 0x018F
96 // Memory organization.
102 // P16C926.INC Standard Header File, Version 1.02 Microchip Technology, Inc.
105 // This header file defines configurations, registers, and other useful bits of
106 // information for the PIC16C926 microcontroller. These names are taken to match
107 // the data sheets as closely as possible.
109 // Note that the processor must be selected before this file is
110 // included. The processor may be selected the following ways:
112 // 1. Command line switch:
113 // C:\ MPASM MYFILE.ASM /PIC16C926
114 // 2. LIST directive in the source file
116 // 3. Processor Type entry in the MPASM full-screen interface
118 //==========================================================================
122 //==========================================================================
126 //1.00 10/11/00 Initial Release
127 //1.01 02/27/01 Changes to reflect design changes to data memory map:
128 // 1.) Locations of PMDATA and PMCON1 swapped.
129 // 2.) Locations of PMDATH and PMADR swapped.
130 //1.02 03/02/01 PORTF, PORTG, TRISF, and TRISG addresses corrected.
131 //1.03 03/06/01 RD bit in PMCON1 defined.
132 //1.04 03/12/01 Locations of PMDATH and PMADR restored to before v1.01.
133 //1.05 10/19/01 Locations of PMDATH and PMADR restored to before v1.04.
134 //1.06 06/03/01 Values for _CP_ALL, _CP_75, _CP_50, and _BODEN_OFF corrected.
136 //==========================================================================
140 //==========================================================================
143 // MESSG "Processor-header file mismatch. Verify selected processor."
146 //==========================================================================
148 // Register Definitions
150 //==========================================================================
155 //----- Register Files------------------------------------------------------
157 extern __data __at (INDF_ADDR) volatile char INDF;
158 extern __sfr __at (TMR0_ADDR) TMR0;
159 extern __data __at (PCL_ADDR) volatile char PCL;
160 extern __sfr __at (STATUS_ADDR) STATUS;
161 extern __sfr __at (FSR_ADDR) FSR;
162 extern __sfr __at (PORTA_ADDR) PORTA;
163 extern __sfr __at (PORTB_ADDR) PORTB;
164 extern __sfr __at (PORTC_ADDR) PORTC;
165 extern __sfr __at (PORTD_ADDR) PORTD;
166 extern __sfr __at (PORTE_ADDR) PORTE;
167 extern __sfr __at (PCLATH_ADDR) PCLATH;
168 extern __sfr __at (INTCON_ADDR) INTCON;
169 extern __sfr __at (PIR1_ADDR) PIR1;
170 extern __sfr __at (TMR1L_ADDR) TMR1L;
171 extern __sfr __at (TMR1H_ADDR) TMR1H;
172 extern __sfr __at (T1CON_ADDR) T1CON;
173 extern __sfr __at (TMR2_ADDR) TMR2;
174 extern __sfr __at (T2CON_ADDR) T2CON;
175 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
176 extern __sfr __at (SSPCON_ADDR) SSPCON;
177 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
178 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
179 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
180 extern __sfr __at (ADRESH_ADDR) ADRESH;
181 extern __sfr __at (ADCON0_ADDR) ADCON0;
183 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
184 extern __sfr __at (TRISA_ADDR) TRISA;
185 extern __sfr __at (TRISB_ADDR) TRISB;
186 extern __sfr __at (TRISC_ADDR) TRISC;
187 extern __sfr __at (TRISD_ADDR) TRISD;
188 extern __sfr __at (TRISE_ADDR) TRISE;
189 extern __sfr __at (PIE1_ADDR) PIE1;
190 extern __sfr __at (PCON_ADDR) PCON;
191 extern __sfr __at (PR2_ADDR) PR2;
192 extern __sfr __at (SSPADD_ADDR) SSPADD;
193 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
194 extern __sfr __at (ADRESL_ADDR) ADRESL;
195 extern __sfr __at (ADCON1_ADDR) ADCON1;
197 extern __sfr __at (PORTF_ADDR) PORTF;
198 extern __sfr __at (PORTG_ADDR) PORTG;
199 extern __sfr __at (PMCON1_ADDR) PMCON1;
200 extern __sfr __at (LCDSE_ADDR) LCDSE;
201 extern __sfr __at (LCDPS_ADDR) LCDPS;
202 extern __sfr __at (LCDCON_ADDR) LCDCON;
203 extern __sfr __at (LCDD00_ADDR) LCDD00;
204 extern __sfr __at (LCDD01_ADDR) LCDD01;
205 extern __sfr __at (LCDD02_ADDR) LCDD02;
206 extern __sfr __at (LCDD03_ADDR) LCDD03;
207 extern __sfr __at (LCDD04_ADDR) LCDD04;
208 extern __sfr __at (LCDD05_ADDR) LCDD05;
209 extern __sfr __at (LCDD06_ADDR) LCDD06;
210 extern __sfr __at (LCDD07_ADDR) LCDD07;
211 extern __sfr __at (LCDD08_ADDR) LCDD08;
212 extern __sfr __at (LCDD09_ADDR) LCDD09;
213 extern __sfr __at (LCDD10_ADDR) LCDD10;
214 extern __sfr __at (LCDD11_ADDR) LCDD11;
215 extern __sfr __at (LCDD12_ADDR) LCDD12;
216 extern __sfr __at (LCDD13_ADDR) LCDD13;
217 extern __sfr __at (LCDD14_ADDR) LCDD14;
218 extern __sfr __at (LCDD15_ADDR) LCDD15;
220 extern __sfr __at (TRISF_ADDR) TRISF;
221 extern __sfr __at (TRISG_ADDR) TRISG;
222 extern __sfr __at (PMDATA_ADDR) PMDATA;
223 extern __sfr __at (PMDATH_ADDR) PMDATH;
224 extern __sfr __at (PMADR_ADDR) PMADR;
225 extern __sfr __at (PMADRH_ADDR) PMADRH;
228 //----- STATUS Bits --------------------------------------------------------
231 //----- INTCON Bits --------------------------------------------------------
234 //----- PIR1 Bits ----------------------------------------------------------
237 //----- T1CON Bits ---------------------------------------------------------
240 //----- T2CON Bits ---------------------------------------------------------
243 //----- SSPCON Bits --------------------------------------------------------
246 //----- CCP1CON Bits -------------------------------------------------------
249 //----- ADCON0 Bits --------------------------------------------------------
252 //----- ADCON1 Bits --------------------------------------------------------
256 //----- OPTION Bits --------------------------------------------------------
259 //----- TRISE Bits ---------------------------------------------------------
262 //----- PIE1 Bits ----------------------------------------------------------
265 //----- PCON Bits ----------------------------------------------------------
268 //----- SSPSTAT Bits -------------------------------------------------------
271 //----- LCDSE Bits ---------------------------------------------------------
274 //----- LCDPS Bits ---------------------------------------------------------
277 //----- LCDCON Bits --------------------------------------------------------
280 //----- PMCON1 Bits --------------------------------------------------------
282 //==========================================================================
286 //==========================================================================
289 // __BADRAM H'0D', H'18'-H'1D'
290 // __BADRAM H'8D', H'8F'-H'91', H'95'-H'9D'
291 // __BADRAM H'105', H'109'
292 // __BADRAM H'185', H'189', H'190'-H'19F'
294 //==========================================================================
296 // Configuration Bits
298 //==========================================================================
300 #define _CP_ALL 0x3FCF
301 #define _CP_75 0x3FDF
302 #define _CP_50 0x3FEF
303 #define _CP_OFF 0x3FFF
304 #define _BODEN_OFF 0x3FBF
305 #define _BODEN_ON 0x3FFF
306 #define _PWRTE_OFF 0x3FFF
307 #define _PWRTE_ON 0x3FF7
308 #define _WDT_ON 0x3FFF
309 #define _WDT_OFF 0x3FFB
310 #define _LP_OSC 0x3FFC
311 #define _XT_OSC 0x3FFD
312 #define _HS_OSC 0x3FFE
313 #define _RC_OSC 0x3FFF
317 // ----- ADCON0 bits --------------------
320 unsigned char ADON:1;
323 unsigned char CHS0:1;
324 unsigned char CHS1:1;
325 unsigned char CHS2:1;
326 unsigned char ADCS0:1;
327 unsigned char ADCS1:1;
332 unsigned char NOT_DONE:1;
342 unsigned char GO_DONE:1;
350 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
352 #define ADON ADCON0_bits.ADON
353 #define GO ADCON0_bits.GO
354 #define NOT_DONE ADCON0_bits.NOT_DONE
355 #define GO_DONE ADCON0_bits.GO_DONE
356 #define CHS0 ADCON0_bits.CHS0
357 #define CHS1 ADCON0_bits.CHS1
358 #define CHS2 ADCON0_bits.CHS2
359 #define ADCS0 ADCON0_bits.ADCS0
360 #define ADCS1 ADCON0_bits.ADCS1
362 // ----- ADCON1 bits --------------------
365 unsigned char PCFG0:1;
366 unsigned char PCFG1:1;
367 unsigned char PCFG2:1;
368 unsigned char PCFG3:1;
372 unsigned char ADFM:1;
375 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
377 #define PCFG0 ADCON1_bits.PCFG0
378 #define PCFG1 ADCON1_bits.PCFG1
379 #define PCFG2 ADCON1_bits.PCFG2
380 #define PCFG3 ADCON1_bits.PCFG3
381 #define ADFM ADCON1_bits.ADFM
383 // ----- CCP1CON bits --------------------
386 unsigned char CCP1M0:1;
387 unsigned char CCP1M1:1;
388 unsigned char CCP1M2:1;
389 unsigned char CCP1M3:1;
390 unsigned char CCP1Y:1;
391 unsigned char CCP1X:1;
396 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
398 #define CCP1M0 CCP1CON_bits.CCP1M0
399 #define CCP1M1 CCP1CON_bits.CCP1M1
400 #define CCP1M2 CCP1CON_bits.CCP1M2
401 #define CCP1M3 CCP1CON_bits.CCP1M3
402 #define CCP1Y CCP1CON_bits.CCP1Y
403 #define CCP1X CCP1CON_bits.CCP1X
405 // ----- INTCON bits --------------------
408 unsigned char RBIF:1;
409 unsigned char INTF:1;
410 unsigned char T0IF:1;
411 unsigned char RBIE:1;
412 unsigned char INTE:1;
413 unsigned char T0IE:1;
414 unsigned char PEIE:1;
418 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
420 #define RBIF INTCON_bits.RBIF
421 #define INTF INTCON_bits.INTF
422 #define T0IF INTCON_bits.T0IF
423 #define RBIE INTCON_bits.RBIE
424 #define INTE INTCON_bits.INTE
425 #define T0IE INTCON_bits.T0IE
426 #define PEIE INTCON_bits.PEIE
427 #define GIE INTCON_bits.GIE
429 // ----- LCDCON bits --------------------
432 unsigned char LMUX0:1;
433 unsigned char LMUX1:1;
436 unsigned char BIAS:1;
437 unsigned char WERR:1;
438 unsigned char SLPEN:1;
439 unsigned char LCDEN:1;
442 extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits;
444 #define LMUX0 LCDCON_bits.LMUX0
445 #define LMUX1 LCDCON_bits.LMUX1
446 #define CS0 LCDCON_bits.CS0
447 #define CS1 LCDCON_bits.CS1
448 #define BIAS LCDCON_bits.BIAS
449 #define WERR LCDCON_bits.WERR
450 #define SLPEN LCDCON_bits.SLPEN
451 #define LCDEN LCDCON_bits.LCDEN
453 // ----- LCDPS bits --------------------
466 extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits;
468 #define LP0 LCDPS_bits.LP0
469 #define LP1 LCDPS_bits.LP1
470 #define LP2 LCDPS_bits.LP2
471 #define LP3 LCDPS_bits.LP3
473 // ----- LCDSE bits --------------------
479 unsigned char SE12:1;
480 unsigned char SE16:1;
481 unsigned char SE20:1;
482 unsigned char SE27:1;
483 unsigned char SE29:1;
486 extern volatile __LCDSE_bits_t __at(LCDSE_ADDR) LCDSE_bits;
488 #define SE0 LCDSE_bits.SE0
489 #define SE5 LCDSE_bits.SE5
490 #define SE9 LCDSE_bits.SE9
491 #define SE12 LCDSE_bits.SE12
492 #define SE16 LCDSE_bits.SE16
493 #define SE20 LCDSE_bits.SE20
494 #define SE27 LCDSE_bits.SE27
495 #define SE29 LCDSE_bits.SE29
497 // ----- OPTION_REG bits --------------------
504 unsigned char T0SE:1;
505 unsigned char T0CS:1;
506 unsigned char INTEDG:1;
507 unsigned char NOT_RBPU:1;
509 } __OPTION_REG_bits_t;
510 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
512 #define PS0 OPTION_REG_bits.PS0
513 #define PS1 OPTION_REG_bits.PS1
514 #define PS2 OPTION_REG_bits.PS2
515 #define PSA OPTION_REG_bits.PSA
516 #define T0SE OPTION_REG_bits.T0SE
517 #define T0CS OPTION_REG_bits.T0CS
518 #define INTEDG OPTION_REG_bits.INTEDG
519 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
521 // ----- PCON bits --------------------
524 unsigned char NOT_BOR:1;
525 unsigned char NOT_POR:1;
534 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
536 #define NOT_BOR PCON_bits.NOT_BOR
537 #define NOT_POR PCON_bits.NOT_POR
539 // ----- PIE1 bits --------------------
542 unsigned char TMR1IE:1;
543 unsigned char TMR2IE:1;
544 unsigned char CCP1IE:1;
545 unsigned char SSPIE:1;
548 unsigned char ADIE:1;
549 unsigned char LCDIE:1;
552 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
554 #define TMR1IE PIE1_bits.TMR1IE
555 #define TMR2IE PIE1_bits.TMR2IE
556 #define CCP1IE PIE1_bits.CCP1IE
557 #define SSPIE PIE1_bits.SSPIE
558 #define ADIE PIE1_bits.ADIE
559 #define LCDIE PIE1_bits.LCDIE
561 // ----- PIR1 bits --------------------
564 unsigned char TMR1IF:1;
565 unsigned char TMR2IF:1;
566 unsigned char CCP1IF:1;
567 unsigned char SSPIF:1;
570 unsigned char ADIF:1;
571 unsigned char LCDIF:1;
574 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
576 #define TMR1IF PIR1_bits.TMR1IF
577 #define TMR2IF PIR1_bits.TMR2IF
578 #define CCP1IF PIR1_bits.CCP1IF
579 #define SSPIF PIR1_bits.SSPIF
580 #define ADIF PIR1_bits.ADIF
581 #define LCDIF PIR1_bits.LCDIF
583 // ----- PMCON1 bits --------------------
596 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
598 #define RD PMCON1_bits.RD
600 // ----- SSPCON bits --------------------
603 unsigned char SSPM0:1;
604 unsigned char SSPM1:1;
605 unsigned char SSPM2:1;
606 unsigned char SSPM3:1;
608 unsigned char SSPEN:1;
609 unsigned char SSPOV:1;
610 unsigned char WCOL:1;
613 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
615 #define SSPM0 SSPCON_bits.SSPM0
616 #define SSPM1 SSPCON_bits.SSPM1
617 #define SSPM2 SSPCON_bits.SSPM2
618 #define SSPM3 SSPCON_bits.SSPM3
619 #define CKP SSPCON_bits.CKP
620 #define SSPEN SSPCON_bits.SSPEN
621 #define SSPOV SSPCON_bits.SSPOV
622 #define WCOL SSPCON_bits.WCOL
624 // ----- SSPSTAT bits --------------------
639 unsigned char I2C_READ:1;
640 unsigned char I2C_START:1;
641 unsigned char I2C_STOP:1;
642 unsigned char I2C_DATA:1;
649 unsigned char NOT_W:1;
652 unsigned char NOT_A:1;
659 unsigned char NOT_WRITE:1;
662 unsigned char NOT_ADDRESS:1;
679 unsigned char READ_WRITE:1;
682 unsigned char DATA_ADDRESS:1;
687 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
689 #define BF SSPSTAT_bits.BF
690 #define UA SSPSTAT_bits.UA
691 #define R SSPSTAT_bits.R
692 #define I2C_READ SSPSTAT_bits.I2C_READ
693 #define NOT_W SSPSTAT_bits.NOT_W
694 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
695 #define R_W SSPSTAT_bits.R_W
696 #define READ_WRITE SSPSTAT_bits.READ_WRITE
697 #define S SSPSTAT_bits.S
698 #define I2C_START SSPSTAT_bits.I2C_START
699 #define P SSPSTAT_bits.P
700 #define I2C_STOP SSPSTAT_bits.I2C_STOP
701 #define D SSPSTAT_bits.D
702 #define I2C_DATA SSPSTAT_bits.I2C_DATA
703 #define NOT_A SSPSTAT_bits.NOT_A
704 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
705 #define D_A SSPSTAT_bits.D_A
706 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
707 #define CKE SSPSTAT_bits.CKE
708 #define SMP SSPSTAT_bits.SMP
710 // ----- STATUS bits --------------------
716 unsigned char NOT_PD:1;
717 unsigned char NOT_TO:1;
723 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
725 #define C STATUS_bits.C
726 #define DC STATUS_bits.DC
727 #define Z STATUS_bits.Z
728 #define NOT_PD STATUS_bits.NOT_PD
729 #define NOT_TO STATUS_bits.NOT_TO
730 #define RP0 STATUS_bits.RP0
731 #define RP1 STATUS_bits.RP1
732 #define IRP STATUS_bits.IRP
734 // ----- T1CON bits --------------------
737 unsigned char TMR1ON:1;
738 unsigned char TMR1CS:1;
739 unsigned char NOT_T1SYNC:1;
740 unsigned char T1OSCEN:1;
741 unsigned char T1CKPS0:1;
742 unsigned char T1CKPS1:1;
749 unsigned char T1INSYNC:1;
757 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
759 #define TMR1ON T1CON_bits.TMR1ON
760 #define TMR1CS T1CON_bits.TMR1CS
761 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
762 #define T1INSYNC T1CON_bits.T1INSYNC
763 #define T1OSCEN T1CON_bits.T1OSCEN
764 #define T1CKPS0 T1CON_bits.T1CKPS0
765 #define T1CKPS1 T1CON_bits.T1CKPS1
767 // ----- T2CON bits --------------------
770 unsigned char T2CKPS0:1;
771 unsigned char T2CKPS1:1;
772 unsigned char TMR2ON:1;
773 unsigned char TOUTPS0:1;
774 unsigned char TOUTPS1:1;
775 unsigned char TOUTPS2:1;
776 unsigned char TOUTPS3:1;
780 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
782 #define T2CKPS0 T2CON_bits.T2CKPS0
783 #define T2CKPS1 T2CON_bits.T2CKPS1
784 #define TMR2ON T2CON_bits.TMR2ON
785 #define TOUTPS0 T2CON_bits.TOUTPS0
786 #define TOUTPS1 T2CON_bits.TOUTPS1
787 #define TOUTPS2 T2CON_bits.TOUTPS2
788 #define TOUTPS3 T2CON_bits.TOUTPS3
790 // ----- TRISE bits --------------------
793 unsigned char TRISE0:1;
794 unsigned char TRISE1:1;
795 unsigned char TRISE2:1;
797 unsigned char PSPMODE:1;
798 unsigned char IBOV:1;
803 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
805 #define TRISE0 TRISE_bits.TRISE0
806 #define TRISE1 TRISE_bits.TRISE1
807 #define TRISE2 TRISE_bits.TRISE2
808 #define PSPMODE TRISE_bits.PSPMODE
809 #define IBOV TRISE_bits.IBOV
810 #define OBF TRISE_bits.OBF
811 #define IBF TRISE_bits.IBF