2 // Register Declarations for Microchip 16C926 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define TMR1L_ADDR 0x000E
42 #define TMR1H_ADDR 0x000F
43 #define T1CON_ADDR 0x0010
44 #define TMR2_ADDR 0x0011
45 #define T2CON_ADDR 0x0012
46 #define SSPBUF_ADDR 0x0013
47 #define SSPCON_ADDR 0x0014
48 #define CCPR1L_ADDR 0x0015
49 #define CCPR1H_ADDR 0x0016
50 #define CCP1CON_ADDR 0x0017
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISB_ADDR 0x0086
56 #define TRISC_ADDR 0x0087
57 #define TRISD_ADDR 0x0088
58 #define TRISE_ADDR 0x0089
59 #define PIE1_ADDR 0x008C
60 #define PCON_ADDR 0x008E
61 #define PR2_ADDR 0x0092
62 #define SSPADD_ADDR 0x0093
63 #define SSPSTAT_ADDR 0x0094
64 #define ADRESL_ADDR 0x009E
65 #define ADCON1_ADDR 0x009F
66 #define PORTF_ADDR 0x0107
67 #define PORTG_ADDR 0x0108
68 #define PMCON1_ADDR 0x010C
69 #define LCDSE_ADDR 0x010D
70 #define LCDPS_ADDR 0x010E
71 #define LCDCON_ADDR 0x010F
72 #define LCDD00_ADDR 0x0110
73 #define LCDD01_ADDR 0x0111
74 #define LCDD02_ADDR 0x0112
75 #define LCDD03_ADDR 0x0113
76 #define LCDD04_ADDR 0x0114
77 #define LCDD05_ADDR 0x0115
78 #define LCDD06_ADDR 0x0116
79 #define LCDD07_ADDR 0x0117
80 #define LCDD08_ADDR 0x0118
81 #define LCDD09_ADDR 0x0119
82 #define LCDD10_ADDR 0x011A
83 #define LCDD11_ADDR 0x011B
84 #define LCDD12_ADDR 0x011C
85 #define LCDD13_ADDR 0x011D
86 #define LCDD14_ADDR 0x011E
87 #define LCDD15_ADDR 0x011F
88 #define TRISF_ADDR 0x0187
89 #define TRISG_ADDR 0x0188
90 #define PMDATA_ADDR 0x018C
91 #define PMDATH_ADDR 0x018D
92 #define PMADR_ADDR 0x018E
93 #define PMADRH_ADDR 0x018F
96 // Memory organization.
102 // P16C926.INC Standard Header File, Version 1.02 Microchip Technology, Inc.
105 // This header file defines configurations, registers, and other useful bits of
106 // information for the PIC16C926 microcontroller. These names are taken to match
107 // the data sheets as closely as possible.
109 // Note that the processor must be selected before this file is
110 // included. The processor may be selected the following ways:
112 // 1. Command line switch:
113 // C:\ MPASM MYFILE.ASM /PIC16C926
114 // 2. LIST directive in the source file
116 // 3. Processor Type entry in the MPASM full-screen interface
118 //==========================================================================
122 //==========================================================================
126 //1.00 10/11/00 Initial Release
127 //1.01 02/27/01 Changes to reflect design changes to data memory map:
128 // 1.) Locations of PMDATA and PMCON1 swapped.
129 // 2.) Locations of PMDATH and PMADR swapped.
130 //1.02 03/02/01 PORTF, PORTG, TRISF, and TRISG addresses corrected.
131 //1.03 03/06/01 RD bit in PMCON1 defined.
132 //1.04 03/12/01 Locations of PMDATH and PMADR restored to before v1.01.
133 //1.05 10/19/01 Locations of PMDATH and PMADR restored to before v1.04.
134 //1.06 06/03/01 Values for _CP_ALL, _CP_75, _CP_50, and _BODEN_OFF corrected.
136 //==========================================================================
140 //==========================================================================
143 // MESSG "Processor-header file mismatch. Verify selected processor."
146 //==========================================================================
148 // Register Definitions
150 //==========================================================================
155 //----- Register Files------------------------------------------------------
157 extern __data __at (INDF_ADDR) volatile char INDF;
158 extern __sfr __at (TMR0_ADDR) TMR0;
159 extern __data __at (PCL_ADDR) volatile char PCL;
160 extern __sfr __at (STATUS_ADDR) STATUS;
161 extern __sfr __at (FSR_ADDR) FSR;
162 extern __sfr __at (PORTA_ADDR) PORTA;
163 extern __sfr __at (PORTB_ADDR) PORTB;
164 extern __sfr __at (PORTC_ADDR) PORTC;
165 extern __sfr __at (PORTD_ADDR) PORTD;
166 extern __sfr __at (PORTE_ADDR) PORTE;
167 extern __sfr __at (PCLATH_ADDR) PCLATH;
168 extern __sfr __at (INTCON_ADDR) INTCON;
169 extern __sfr __at (PIR1_ADDR) PIR1;
170 extern __sfr __at (TMR1L_ADDR) TMR1L;
171 extern __sfr __at (TMR1H_ADDR) TMR1H;
172 extern __sfr __at (T1CON_ADDR) T1CON;
173 extern __sfr __at (TMR2_ADDR) TMR2;
174 extern __sfr __at (T2CON_ADDR) T2CON;
175 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
176 extern __sfr __at (SSPCON_ADDR) SSPCON;
177 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
178 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
179 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
180 extern __sfr __at (ADRESH_ADDR) ADRESH;
181 extern __sfr __at (ADCON0_ADDR) ADCON0;
183 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
184 extern __sfr __at (TRISA_ADDR) TRISA;
185 extern __sfr __at (TRISB_ADDR) TRISB;
186 extern __sfr __at (TRISC_ADDR) TRISC;
187 extern __sfr __at (TRISD_ADDR) TRISD;
188 extern __sfr __at (TRISE_ADDR) TRISE;
189 extern __sfr __at (PIE1_ADDR) PIE1;
190 extern __sfr __at (PCON_ADDR) PCON;
191 extern __sfr __at (PR2_ADDR) PR2;
192 extern __sfr __at (SSPADD_ADDR) SSPADD;
193 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
194 extern __sfr __at (ADRESL_ADDR) ADRESL;
195 extern __sfr __at (ADCON1_ADDR) ADCON1;
197 extern __sfr __at (PORTF_ADDR) PORTF;
198 extern __sfr __at (PORTG_ADDR) PORTG;
199 extern __sfr __at (PMCON1_ADDR) PMCON1;
200 extern __sfr __at (LCDSE_ADDR) LCDSE;
201 extern __sfr __at (LCDPS_ADDR) LCDPS;
202 extern __sfr __at (LCDCON_ADDR) LCDCON;
203 extern __sfr __at (LCDD00_ADDR) LCDD00;
204 extern __sfr __at (LCDD01_ADDR) LCDD01;
205 extern __sfr __at (LCDD02_ADDR) LCDD02;
206 extern __sfr __at (LCDD03_ADDR) LCDD03;
207 extern __sfr __at (LCDD04_ADDR) LCDD04;
208 extern __sfr __at (LCDD05_ADDR) LCDD05;
209 extern __sfr __at (LCDD06_ADDR) LCDD06;
210 extern __sfr __at (LCDD07_ADDR) LCDD07;
211 extern __sfr __at (LCDD08_ADDR) LCDD08;
212 extern __sfr __at (LCDD09_ADDR) LCDD09;
213 extern __sfr __at (LCDD10_ADDR) LCDD10;
214 extern __sfr __at (LCDD11_ADDR) LCDD11;
215 extern __sfr __at (LCDD12_ADDR) LCDD12;
216 extern __sfr __at (LCDD13_ADDR) LCDD13;
217 extern __sfr __at (LCDD14_ADDR) LCDD14;
218 extern __sfr __at (LCDD15_ADDR) LCDD15;
220 extern __sfr __at (TRISF_ADDR) TRISF;
221 extern __sfr __at (TRISG_ADDR) TRISG;
222 extern __sfr __at (PMDATA_ADDR) PMDATA;
223 extern __sfr __at (PMDATH_ADDR) PMDATH;
224 extern __sfr __at (PMADR_ADDR) PMADR;
225 extern __sfr __at (PMADRH_ADDR) PMADRH;
228 //----- STATUS Bits --------------------------------------------------------
231 //----- INTCON Bits --------------------------------------------------------
234 //----- PIR1 Bits ----------------------------------------------------------
237 //----- T1CON Bits ---------------------------------------------------------
240 //----- T2CON Bits ---------------------------------------------------------
243 //----- SSPCON Bits --------------------------------------------------------
246 //----- CCP1CON Bits -------------------------------------------------------
249 //----- ADCON0 Bits --------------------------------------------------------
252 //----- ADCON1 Bits --------------------------------------------------------
256 //----- OPTION Bits --------------------------------------------------------
259 //----- TRISE Bits ---------------------------------------------------------
262 //----- PIE1 Bits ----------------------------------------------------------
265 //----- PCON Bits ----------------------------------------------------------
268 //----- SSPSTAT Bits -------------------------------------------------------
271 //----- ADCON1 Bits --------------------------------------------------------
274 //----- LCDSE Bits ---------------------------------------------------------
277 //----- LCDPS Bits ---------------------------------------------------------
280 //----- LCDCON Bits --------------------------------------------------------
283 //----- PMCON1 Bits --------------------------------------------------------
285 //==========================================================================
289 //==========================================================================
292 // __BADRAM H'0D', H'18'-H'1D'
293 // __BADRAM H'8D', H'8F'-H'91', H'95'-H'9D'
294 // __BADRAM H'105', H'109'
295 // __BADRAM H'185', H'189', H'190'-H'19F'
297 //==========================================================================
299 // Configuration Bits
301 //==========================================================================
303 #define _CP_ALL 0x3FCF
304 #define _CP_75 0x3FDF
305 #define _CP_50 0x3FEF
306 #define _CP_OFF 0x3FFF
307 #define _BODEN_OFF 0x3FBF
308 #define _BODEN_ON 0x3FFF
309 #define _PWRTE_OFF 0x3FFF
310 #define _PWRTE_ON 0x3FF7
311 #define _WDT_ON 0x3FFF
312 #define _WDT_OFF 0x3FFB
313 #define _LP_OSC 0x3FFC
314 #define _XT_OSC 0x3FFD
315 #define _HS_OSC 0x3FFE
316 #define _RC_OSC 0x3FFF
320 // ----- ADCON0 bits --------------------
323 unsigned char ADON:1;
326 unsigned char CHS0:1;
327 unsigned char CHS1:1;
328 unsigned char CHS2:1;
329 unsigned char ADCS0:1;
330 unsigned char ADCS1:1;
335 unsigned char NOT_DONE:1;
345 unsigned char GO_DONE:1;
353 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
355 #define ADON ADCON0_bits.ADON
356 #define GO ADCON0_bits.GO
357 #define NOT_DONE ADCON0_bits.NOT_DONE
358 #define GO_DONE ADCON0_bits.GO_DONE
359 #define CHS0 ADCON0_bits.CHS0
360 #define CHS1 ADCON0_bits.CHS1
361 #define CHS2 ADCON0_bits.CHS2
362 #define ADCS0 ADCON0_bits.ADCS0
363 #define ADCS1 ADCON0_bits.ADCS1
365 // ----- ADCON1 bits --------------------
368 unsigned char PCFG0:1;
369 unsigned char PCFG1:1;
370 unsigned char PCFG2:1;
371 unsigned char PCFG3:1;
375 unsigned char ADFM:1;
378 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
380 #define PCFG0 ADCON1_bits.PCFG0
381 #define PCFG1 ADCON1_bits.PCFG1
382 #define PCFG2 ADCON1_bits.PCFG2
383 #define PCFG3 ADCON1_bits.PCFG3
384 #define ADFM ADCON1_bits.ADFM
386 // ----- CCP1CON bits --------------------
389 unsigned char CCP1M0:1;
390 unsigned char CCP1M1:1;
391 unsigned char CCP1M2:1;
392 unsigned char CCP1M3:1;
393 unsigned char CCP1Y:1;
394 unsigned char CCP1X:1;
399 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
401 #define CCP1M0 CCP1CON_bits.CCP1M0
402 #define CCP1M1 CCP1CON_bits.CCP1M1
403 #define CCP1M2 CCP1CON_bits.CCP1M2
404 #define CCP1M3 CCP1CON_bits.CCP1M3
405 #define CCP1Y CCP1CON_bits.CCP1Y
406 #define CCP1X CCP1CON_bits.CCP1X
408 // ----- INTCON bits --------------------
411 unsigned char RBIF:1;
412 unsigned char INTF:1;
413 unsigned char T0IF:1;
414 unsigned char RBIE:1;
415 unsigned char INTE:1;
416 unsigned char T0IE:1;
417 unsigned char PEIE:1;
421 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
423 #define RBIF INTCON_bits.RBIF
424 #define INTF INTCON_bits.INTF
425 #define T0IF INTCON_bits.T0IF
426 #define RBIE INTCON_bits.RBIE
427 #define INTE INTCON_bits.INTE
428 #define T0IE INTCON_bits.T0IE
429 #define PEIE INTCON_bits.PEIE
430 #define GIE INTCON_bits.GIE
432 // ----- LCDCON bits --------------------
435 unsigned char LMUX0:1;
436 unsigned char LMUX1:1;
439 unsigned char BIAS:1;
440 unsigned char WERR:1;
441 unsigned char SLPEN:1;
442 unsigned char LCDEN:1;
445 extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits;
447 #define LMUX0 LCDCON_bits.LMUX0
448 #define LMUX1 LCDCON_bits.LMUX1
449 #define CS0 LCDCON_bits.CS0
450 #define CS1 LCDCON_bits.CS1
451 #define BIAS LCDCON_bits.BIAS
452 #define WERR LCDCON_bits.WERR
453 #define SLPEN LCDCON_bits.SLPEN
454 #define LCDEN LCDCON_bits.LCDEN
456 // ----- LCDPS bits --------------------
469 extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits;
471 #define LP0 LCDPS_bits.LP0
472 #define LP1 LCDPS_bits.LP1
473 #define LP2 LCDPS_bits.LP2
474 #define LP3 LCDPS_bits.LP3
476 // ----- LCDSE bits --------------------
482 unsigned char SE12:1;
483 unsigned char SE16:1;
484 unsigned char SE20:1;
485 unsigned char SE27:1;
486 unsigned char SE29:1;
489 extern volatile __LCDSE_bits_t __at(LCDSE_ADDR) LCDSE_bits;
491 #define SE0 LCDSE_bits.SE0
492 #define SE5 LCDSE_bits.SE5
493 #define SE9 LCDSE_bits.SE9
494 #define SE12 LCDSE_bits.SE12
495 #define SE16 LCDSE_bits.SE16
496 #define SE20 LCDSE_bits.SE20
497 #define SE27 LCDSE_bits.SE27
498 #define SE29 LCDSE_bits.SE29
500 // ----- OPTION_REG bits --------------------
507 unsigned char T0SE:1;
508 unsigned char T0CS:1;
509 unsigned char INTEDG:1;
510 unsigned char NOT_RBPU:1;
512 } __OPTION_REG_bits_t;
513 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
515 #define PS0 OPTION_REG_bits.PS0
516 #define PS1 OPTION_REG_bits.PS1
517 #define PS2 OPTION_REG_bits.PS2
518 #define PSA OPTION_REG_bits.PSA
519 #define T0SE OPTION_REG_bits.T0SE
520 #define T0CS OPTION_REG_bits.T0CS
521 #define INTEDG OPTION_REG_bits.INTEDG
522 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
524 // ----- PCON bits --------------------
527 unsigned char NOT_BOR:1;
528 unsigned char NOT_POR:1;
537 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
539 #define NOT_BOR PCON_bits.NOT_BOR
540 #define NOT_POR PCON_bits.NOT_POR
542 // ----- PIE1 bits --------------------
545 unsigned char TMR1IE:1;
546 unsigned char TMR2IE:1;
547 unsigned char CCP1IE:1;
548 unsigned char SSPIE:1;
551 unsigned char ADIE:1;
552 unsigned char LCDIE:1;
555 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
557 #define TMR1IE PIE1_bits.TMR1IE
558 #define TMR2IE PIE1_bits.TMR2IE
559 #define CCP1IE PIE1_bits.CCP1IE
560 #define SSPIE PIE1_bits.SSPIE
561 #define ADIE PIE1_bits.ADIE
562 #define LCDIE PIE1_bits.LCDIE
564 // ----- PIR1 bits --------------------
567 unsigned char TMR1IF:1;
568 unsigned char TMR2IF:1;
569 unsigned char CCP1IF:1;
570 unsigned char SSPIF:1;
573 unsigned char ADIF:1;
574 unsigned char LCDIF:1;
577 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
579 #define TMR1IF PIR1_bits.TMR1IF
580 #define TMR2IF PIR1_bits.TMR2IF
581 #define CCP1IF PIR1_bits.CCP1IF
582 #define SSPIF PIR1_bits.SSPIF
583 #define ADIF PIR1_bits.ADIF
584 #define LCDIF PIR1_bits.LCDIF
586 // ----- PMCON1 bits --------------------
599 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
601 #define RD PMCON1_bits.RD
603 // ----- PORTA bits --------------------
616 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
618 #define RA0 PORTA_bits.RA0
619 #define RA1 PORTA_bits.RA1
620 #define RA2 PORTA_bits.RA2
621 #define RA3 PORTA_bits.RA3
622 #define RA4 PORTA_bits.RA4
623 #define RA5 PORTA_bits.RA5
625 // ----- PORTB bits --------------------
638 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
640 #define RB0 PORTB_bits.RB0
641 #define RB1 PORTB_bits.RB1
642 #define RB2 PORTB_bits.RB2
643 #define RB3 PORTB_bits.RB3
644 #define RB4 PORTB_bits.RB4
645 #define RB5 PORTB_bits.RB5
646 #define RB6 PORTB_bits.RB6
647 #define RB7 PORTB_bits.RB7
649 // ----- PORTC bits --------------------
662 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
664 #define RC0 PORTC_bits.RC0
665 #define RC1 PORTC_bits.RC1
666 #define RC2 PORTC_bits.RC2
667 #define RC3 PORTC_bits.RC3
668 #define RC4 PORTC_bits.RC4
669 #define RC5 PORTC_bits.RC5
670 #define RC6 PORTC_bits.RC6
671 #define RC7 PORTC_bits.RC7
673 // ----- PORTD bits --------------------
686 extern volatile __PORTD_bits_t __at(PORTD_ADDR) PORTD_bits;
688 #define RD0 PORTD_bits.RD0
689 #define RD1 PORTD_bits.RD1
690 #define RD2 PORTD_bits.RD2
691 #define RD3 PORTD_bits.RD3
692 #define RD4 PORTD_bits.RD4
693 #define RD5 PORTD_bits.RD5
694 #define RD6 PORTD_bits.RD6
695 #define RD7 PORTD_bits.RD7
697 // ----- PORTE bits --------------------
710 extern volatile __PORTE_bits_t __at(PORTE_ADDR) PORTE_bits;
712 #define RE0 PORTE_bits.RE0
713 #define RE1 PORTE_bits.RE1
714 #define RE2 PORTE_bits.RE2
716 // ----- SSPCON bits --------------------
719 unsigned char SSPM0:1;
720 unsigned char SSPM1:1;
721 unsigned char SSPM2:1;
722 unsigned char SSPM3:1;
724 unsigned char SSPEN:1;
725 unsigned char SSPOV:1;
726 unsigned char WCOL:1;
729 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
731 #define SSPM0 SSPCON_bits.SSPM0
732 #define SSPM1 SSPCON_bits.SSPM1
733 #define SSPM2 SSPCON_bits.SSPM2
734 #define SSPM3 SSPCON_bits.SSPM3
735 #define CKP SSPCON_bits.CKP
736 #define SSPEN SSPCON_bits.SSPEN
737 #define SSPOV SSPCON_bits.SSPOV
738 #define WCOL SSPCON_bits.WCOL
740 // ----- SSPSTAT bits --------------------
755 unsigned char I2C_READ:1;
756 unsigned char I2C_START:1;
757 unsigned char I2C_STOP:1;
758 unsigned char I2C_DATA:1;
765 unsigned char NOT_W:1;
768 unsigned char NOT_A:1;
775 unsigned char NOT_WRITE:1;
778 unsigned char NOT_ADDRESS:1;
795 unsigned char READ_WRITE:1;
798 unsigned char DATA_ADDRESS:1;
803 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
805 #define BF SSPSTAT_bits.BF
806 #define UA SSPSTAT_bits.UA
807 #define R SSPSTAT_bits.R
808 #define I2C_READ SSPSTAT_bits.I2C_READ
809 #define NOT_W SSPSTAT_bits.NOT_W
810 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
811 #define R_W SSPSTAT_bits.R_W
812 #define READ_WRITE SSPSTAT_bits.READ_WRITE
813 #define S SSPSTAT_bits.S
814 #define I2C_START SSPSTAT_bits.I2C_START
815 #define P SSPSTAT_bits.P
816 #define I2C_STOP SSPSTAT_bits.I2C_STOP
817 #define D SSPSTAT_bits.D
818 #define I2C_DATA SSPSTAT_bits.I2C_DATA
819 #define NOT_A SSPSTAT_bits.NOT_A
820 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
821 #define D_A SSPSTAT_bits.D_A
822 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
823 #define CKE SSPSTAT_bits.CKE
824 #define SMP SSPSTAT_bits.SMP
826 // ----- STATUS bits --------------------
832 unsigned char NOT_PD:1;
833 unsigned char NOT_TO:1;
839 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
841 #define C STATUS_bits.C
842 #define DC STATUS_bits.DC
843 #define Z STATUS_bits.Z
844 #define NOT_PD STATUS_bits.NOT_PD
845 #define NOT_TO STATUS_bits.NOT_TO
846 #define RP0 STATUS_bits.RP0
847 #define RP1 STATUS_bits.RP1
848 #define IRP STATUS_bits.IRP
850 // ----- T1CON bits --------------------
853 unsigned char TMR1ON:1;
854 unsigned char TMR1CS:1;
855 unsigned char NOT_T1SYNC:1;
856 unsigned char T1OSCEN:1;
857 unsigned char T1CKPS0:1;
858 unsigned char T1CKPS1:1;
865 unsigned char T1INSYNC:1;
873 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
875 #define TMR1ON T1CON_bits.TMR1ON
876 #define TMR1CS T1CON_bits.TMR1CS
877 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
878 #define T1INSYNC T1CON_bits.T1INSYNC
879 #define T1OSCEN T1CON_bits.T1OSCEN
880 #define T1CKPS0 T1CON_bits.T1CKPS0
881 #define T1CKPS1 T1CON_bits.T1CKPS1
883 // ----- T2CON bits --------------------
886 unsigned char T2CKPS0:1;
887 unsigned char T2CKPS1:1;
888 unsigned char TMR2ON:1;
889 unsigned char TOUTPS0:1;
890 unsigned char TOUTPS1:1;
891 unsigned char TOUTPS2:1;
892 unsigned char TOUTPS3:1;
896 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
898 #define T2CKPS0 T2CON_bits.T2CKPS0
899 #define T2CKPS1 T2CON_bits.T2CKPS1
900 #define TMR2ON T2CON_bits.TMR2ON
901 #define TOUTPS0 T2CON_bits.TOUTPS0
902 #define TOUTPS1 T2CON_bits.TOUTPS1
903 #define TOUTPS2 T2CON_bits.TOUTPS2
904 #define TOUTPS3 T2CON_bits.TOUTPS3
906 // ----- TRISA bits --------------------
909 unsigned char TRISA0:1;
910 unsigned char TRISA1:1;
911 unsigned char TRISA2:1;
912 unsigned char TRISA3:1;
913 unsigned char TRISA4:1;
914 unsigned char TRISA5:1;
919 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
921 #define TRISA0 TRISA_bits.TRISA0
922 #define TRISA1 TRISA_bits.TRISA1
923 #define TRISA2 TRISA_bits.TRISA2
924 #define TRISA3 TRISA_bits.TRISA3
925 #define TRISA4 TRISA_bits.TRISA4
926 #define TRISA5 TRISA_bits.TRISA5
928 // ----- TRISB bits --------------------
931 unsigned char TRISB0:1;
932 unsigned char TRISB1:1;
933 unsigned char TRISB2:1;
934 unsigned char TRISB3:1;
935 unsigned char TRISB4:1;
936 unsigned char TRISB5:1;
937 unsigned char TRISB6:1;
938 unsigned char TRISB7:1;
941 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
943 #define TRISB0 TRISB_bits.TRISB0
944 #define TRISB1 TRISB_bits.TRISB1
945 #define TRISB2 TRISB_bits.TRISB2
946 #define TRISB3 TRISB_bits.TRISB3
947 #define TRISB4 TRISB_bits.TRISB4
948 #define TRISB5 TRISB_bits.TRISB5
949 #define TRISB6 TRISB_bits.TRISB6
950 #define TRISB7 TRISB_bits.TRISB7
952 // ----- TRISC bits --------------------
955 unsigned char TRISC0:1;
956 unsigned char TRISC1:1;
957 unsigned char TRISC2:1;
958 unsigned char TRISC3:1;
959 unsigned char TRISC4:1;
960 unsigned char TRISC5:1;
961 unsigned char TRISC6:1;
962 unsigned char TRISC7:1;
965 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
967 #define TRISC0 TRISC_bits.TRISC0
968 #define TRISC1 TRISC_bits.TRISC1
969 #define TRISC2 TRISC_bits.TRISC2
970 #define TRISC3 TRISC_bits.TRISC3
971 #define TRISC4 TRISC_bits.TRISC4
972 #define TRISC5 TRISC_bits.TRISC5
973 #define TRISC6 TRISC_bits.TRISC6
974 #define TRISC7 TRISC_bits.TRISC7
976 // ----- TRISD bits --------------------
979 unsigned char TRISD0:1;
980 unsigned char TRISD1:1;
981 unsigned char TRISD2:1;
982 unsigned char TRISD3:1;
983 unsigned char TRISD4:1;
984 unsigned char TRISD5:1;
985 unsigned char TRISD6:1;
986 unsigned char TRISD7:1;
989 extern volatile __TRISD_bits_t __at(TRISD_ADDR) TRISD_bits;
991 #define TRISD0 TRISD_bits.TRISD0
992 #define TRISD1 TRISD_bits.TRISD1
993 #define TRISD2 TRISD_bits.TRISD2
994 #define TRISD3 TRISD_bits.TRISD3
995 #define TRISD4 TRISD_bits.TRISD4
996 #define TRISD5 TRISD_bits.TRISD5
997 #define TRISD6 TRISD_bits.TRISD6
998 #define TRISD7 TRISD_bits.TRISD7
1000 // ----- TRISE bits --------------------
1003 unsigned char TRISE0:1;
1004 unsigned char TRISE1:1;
1005 unsigned char TRISE2:1;
1007 unsigned char PSPMODE:1;
1008 unsigned char IBOV:1;
1009 unsigned char OBF:1;
1010 unsigned char IBF:1;
1013 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
1015 #define TRISE0 TRISE_bits.TRISE0
1016 #define TRISE1 TRISE_bits.TRISE1
1017 #define TRISE2 TRISE_bits.TRISE2
1018 #define PSPMODE TRISE_bits.PSPMODE
1019 #define IBOV TRISE_bits.IBOV
1020 #define OBF TRISE_bits.OBF
1021 #define IBF TRISE_bits.IBF