2 // Register Declarations for Microchip 16C925 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define TMR1L_ADDR 0x000E
42 #define TMR1H_ADDR 0x000F
43 #define T1CON_ADDR 0x0010
44 #define TMR2_ADDR 0x0011
45 #define T2CON_ADDR 0x0012
46 #define SSPBUF_ADDR 0x0013
47 #define SSPCON_ADDR 0x0014
48 #define CCPR1L_ADDR 0x0015
49 #define CCPR1H_ADDR 0x0016
50 #define CCP1CON_ADDR 0x0017
51 #define ADRESH_ADDR 0x001E
52 #define ADCON0_ADDR 0x001F
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISB_ADDR 0x0086
56 #define TRISC_ADDR 0x0087
57 #define TRISD_ADDR 0x0088
58 #define TRISE_ADDR 0x0089
59 #define PIE1_ADDR 0x008C
60 #define PCON_ADDR 0x008E
61 #define PR2_ADDR 0x0092
62 #define SSPADD_ADDR 0x0093
63 #define SSPSTAT_ADDR 0x0094
64 #define ADRESL_ADDR 0x009E
65 #define ADCON1_ADDR 0x009F
66 #define PORTF_ADDR 0x0107
67 #define PORTG_ADDR 0x0108
68 #define PMCON1_ADDR 0x010C
69 #define LCDSE_ADDR 0x010D
70 #define LCDPS_ADDR 0x010E
71 #define LCDCON_ADDR 0x010F
72 #define LCDD00_ADDR 0x0110
73 #define LCDD01_ADDR 0x0111
74 #define LCDD02_ADDR 0x0112
75 #define LCDD03_ADDR 0x0113
76 #define LCDD04_ADDR 0x0114
77 #define LCDD05_ADDR 0x0115
78 #define LCDD06_ADDR 0x0116
79 #define LCDD07_ADDR 0x0117
80 #define LCDD08_ADDR 0x0118
81 #define LCDD09_ADDR 0x0119
82 #define LCDD10_ADDR 0x011A
83 #define LCDD11_ADDR 0x011B
84 #define LCDD12_ADDR 0x011C
85 #define LCDD13_ADDR 0x011D
86 #define LCDD14_ADDR 0x011E
87 #define LCDD15_ADDR 0x011F
88 #define TRISF_ADDR 0x0187
89 #define TRISG_ADDR 0x0188
90 #define PMDATA_ADDR 0x018C
91 #define PMDATH_ADDR 0x018D
92 #define PMADR_ADDR 0x018E
93 #define PMADRH_ADDR 0x018F
96 // Memory organization.
99 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
100 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
101 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
102 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
103 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
104 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
105 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
106 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
107 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
108 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
109 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
110 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
111 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
112 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
113 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
114 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
115 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
116 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
117 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
118 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
119 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
120 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
121 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
122 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
123 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
124 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
125 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
126 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
127 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
128 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
129 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
130 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
131 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
132 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
133 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
134 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
135 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
136 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
137 #pragma memmap PORTF_ADDR PORTF_ADDR SFR 0x000 // PORTF
138 #pragma memmap PORTG_ADDR PORTG_ADDR SFR 0x000 // PORTG
139 #pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
140 #pragma memmap LCDSE_ADDR LCDSE_ADDR SFR 0x000 // LCDSE
141 #pragma memmap LCDPS_ADDR LCDPS_ADDR SFR 0x000 // LCDPS
142 #pragma memmap LCDCON_ADDR LCDCON_ADDR SFR 0x000 // LCDCON
143 #pragma memmap LCDD00_ADDR LCDD00_ADDR SFR 0x000 // LCDD00
144 #pragma memmap LCDD01_ADDR LCDD01_ADDR SFR 0x000 // LCDD01
145 #pragma memmap LCDD02_ADDR LCDD02_ADDR SFR 0x000 // LCDD02
146 #pragma memmap LCDD03_ADDR LCDD03_ADDR SFR 0x000 // LCDD03
147 #pragma memmap LCDD04_ADDR LCDD04_ADDR SFR 0x000 // LCDD04
148 #pragma memmap LCDD05_ADDR LCDD05_ADDR SFR 0x000 // LCDD05
149 #pragma memmap LCDD06_ADDR LCDD06_ADDR SFR 0x000 // LCDD06
150 #pragma memmap LCDD07_ADDR LCDD07_ADDR SFR 0x000 // LCDD07
151 #pragma memmap LCDD08_ADDR LCDD08_ADDR SFR 0x000 // LCDD08
152 #pragma memmap LCDD09_ADDR LCDD09_ADDR SFR 0x000 // LCDD09
153 #pragma memmap LCDD10_ADDR LCDD10_ADDR SFR 0x000 // LCDD10
154 #pragma memmap LCDD11_ADDR LCDD11_ADDR SFR 0x000 // LCDD11
155 #pragma memmap LCDD12_ADDR LCDD12_ADDR SFR 0x000 // LCDD12
156 #pragma memmap LCDD13_ADDR LCDD13_ADDR SFR 0x000 // LCDD13
157 #pragma memmap LCDD14_ADDR LCDD14_ADDR SFR 0x000 // LCDD14
158 #pragma memmap LCDD15_ADDR LCDD15_ADDR SFR 0x000 // LCDD15
159 #pragma memmap TRISF_ADDR TRISF_ADDR SFR 0x000 // TRISF
160 #pragma memmap TRISG_ADDR TRISG_ADDR SFR 0x000 // TRISG
161 #pragma memmap PMDATA_ADDR PMDATA_ADDR SFR 0x000 // PMDATA
162 #pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
163 #pragma memmap PMADR_ADDR PMADR_ADDR SFR 0x000 // PMADR
164 #pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
168 // P16C925.INC Standard Header File, Version 1.02 Microchip Technology, Inc.
171 // This header file defines configurations, registers, and other useful bits of
172 // information for the PIC16C925 microcontroller. These names are taken to match
173 // the data sheets as closely as possible.
175 // Note that the processor must be selected before this file is
176 // included. The processor may be selected the following ways:
178 // 1. Command line switch:
179 // C:\ MPASM MYFILE.ASM /PIC16C925
180 // 2. LIST directive in the source file
182 // 3. Processor Type entry in the MPASM full-screen interface
184 //==========================================================================
188 //==========================================================================
192 //1.00 11/21/00 Initial Release
193 //1.01 02/27/01 Changes to reflect design changes to data memory map:
194 // 1.) Locations of PMDATA and PMCON1 swapped.
195 // 2.) Locations of PMDATH and PMADR swapped.
196 //1.02 03/02/01 PORTF, PORTG, TRISF, and TRISG addresses corrected.
197 //1.03 03/06/01 RD bit in PMCON1 defined.
198 //1.04 03/12/01 Locations of PMDATH and PMADR restored to before v1.01.
199 //1.05 10/19/01 Locations of PMDATH and PMADR restored to before v1.04.
200 //1.06 06/03/01 Values for _CP_ALL, _CP_75, _CP_50, and _BODEN_OFF corrected.
202 //==========================================================================
206 //==========================================================================
209 // MESSG "Processor-header file mismatch. Verify selected processor."
212 //==========================================================================
214 // Register Definitions
216 //==========================================================================
221 //----- Register Files------------------------------------------------------
223 extern __data __at (INDF_ADDR) volatile char INDF;
224 extern __sfr __at (TMR0_ADDR) TMR0;
225 extern __data __at (PCL_ADDR) volatile char PCL;
226 extern __sfr __at (STATUS_ADDR) STATUS;
227 extern __sfr __at (FSR_ADDR) FSR;
228 extern __sfr __at (PORTA_ADDR) PORTA;
229 extern __sfr __at (PORTB_ADDR) PORTB;
230 extern __sfr __at (PORTC_ADDR) PORTC;
231 extern __sfr __at (PORTD_ADDR) PORTD;
232 extern __sfr __at (PORTE_ADDR) PORTE;
233 extern __sfr __at (PCLATH_ADDR) PCLATH;
234 extern __sfr __at (INTCON_ADDR) INTCON;
235 extern __sfr __at (PIR1_ADDR) PIR1;
236 extern __sfr __at (TMR1L_ADDR) TMR1L;
237 extern __sfr __at (TMR1H_ADDR) TMR1H;
238 extern __sfr __at (T1CON_ADDR) T1CON;
239 extern __sfr __at (TMR2_ADDR) TMR2;
240 extern __sfr __at (T2CON_ADDR) T2CON;
241 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
242 extern __sfr __at (SSPCON_ADDR) SSPCON;
243 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
244 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
245 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
246 extern __sfr __at (ADRESH_ADDR) ADRESH;
247 extern __sfr __at (ADCON0_ADDR) ADCON0;
249 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
250 extern __sfr __at (TRISA_ADDR) TRISA;
251 extern __sfr __at (TRISB_ADDR) TRISB;
252 extern __sfr __at (TRISC_ADDR) TRISC;
253 extern __sfr __at (TRISD_ADDR) TRISD;
254 extern __sfr __at (TRISE_ADDR) TRISE;
255 extern __sfr __at (PIE1_ADDR) PIE1;
256 extern __sfr __at (PCON_ADDR) PCON;
257 extern __sfr __at (PR2_ADDR) PR2;
258 extern __sfr __at (SSPADD_ADDR) SSPADD;
259 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
260 extern __sfr __at (ADRESL_ADDR) ADRESL;
261 extern __sfr __at (ADCON1_ADDR) ADCON1;
263 extern __sfr __at (PORTF_ADDR) PORTF;
264 extern __sfr __at (PORTG_ADDR) PORTG;
265 extern __sfr __at (PMCON1_ADDR) PMCON1;
266 extern __sfr __at (LCDSE_ADDR) LCDSE;
267 extern __sfr __at (LCDPS_ADDR) LCDPS;
268 extern __sfr __at (LCDCON_ADDR) LCDCON;
269 extern __sfr __at (LCDD00_ADDR) LCDD00;
270 extern __sfr __at (LCDD01_ADDR) LCDD01;
271 extern __sfr __at (LCDD02_ADDR) LCDD02;
272 extern __sfr __at (LCDD03_ADDR) LCDD03;
273 extern __sfr __at (LCDD04_ADDR) LCDD04;
274 extern __sfr __at (LCDD05_ADDR) LCDD05;
275 extern __sfr __at (LCDD06_ADDR) LCDD06;
276 extern __sfr __at (LCDD07_ADDR) LCDD07;
277 extern __sfr __at (LCDD08_ADDR) LCDD08;
278 extern __sfr __at (LCDD09_ADDR) LCDD09;
279 extern __sfr __at (LCDD10_ADDR) LCDD10;
280 extern __sfr __at (LCDD11_ADDR) LCDD11;
281 extern __sfr __at (LCDD12_ADDR) LCDD12;
282 extern __sfr __at (LCDD13_ADDR) LCDD13;
283 extern __sfr __at (LCDD14_ADDR) LCDD14;
284 extern __sfr __at (LCDD15_ADDR) LCDD15;
286 extern __sfr __at (TRISF_ADDR) TRISF;
287 extern __sfr __at (TRISG_ADDR) TRISG;
288 extern __sfr __at (PMDATA_ADDR) PMDATA;
289 extern __sfr __at (PMDATH_ADDR) PMDATH;
290 extern __sfr __at (PMADR_ADDR) PMADR;
291 extern __sfr __at (PMADRH_ADDR) PMADRH;
294 //----- STATUS Bits --------------------------------------------------------
297 //----- INTCON Bits --------------------------------------------------------
300 //----- PIR1 Bits ----------------------------------------------------------
303 //----- T1CON Bits ---------------------------------------------------------
306 //----- T2CON Bits ---------------------------------------------------------
309 //----- SSPCON Bits --------------------------------------------------------
312 //----- CCP1CON Bits -------------------------------------------------------
315 //----- ADCON0 Bits --------------------------------------------------------
318 //----- ADCON1 Bits --------------------------------------------------------
322 //----- OPTION Bits --------------------------------------------------------
325 //----- TRISE Bits ---------------------------------------------------------
328 //----- PIE1 Bits ----------------------------------------------------------
331 //----- PCON Bits ----------------------------------------------------------
334 //----- SSPSTAT Bits -------------------------------------------------------
337 //----- LCDSE Bits ---------------------------------------------------------
340 //----- LCDPS Bits ---------------------------------------------------------
343 //----- LCDCON Bits --------------------------------------------------------
346 //----- PMCON1 Bits --------------------------------------------------------
348 //==========================================================================
352 //==========================================================================
355 // __BADRAM H'0D', H'18'-H'1D'
356 // __BADRAM H'8D', H'8F'-H'91', H'95'-H'9D'
357 // __BADRAM H'105', H'109', H'120'-H'16F'
358 // __BADRAM H'185', H'189', H'190'-H'1EF'
360 //==========================================================================
362 // Configuration Bits
364 //==========================================================================
366 #define _CP_ALL 0x3FCF
367 #define _CP_75 0x3FDF
368 #define _CP_50 0x3FEF
369 #define _CP_OFF 0x3FFF
370 #define _BODEN_OFF 0x3FBF
371 #define _BODEN_ON 0x3FFF
372 #define _PWRTE_OFF 0x3FFF
373 #define _PWRTE_ON 0x3FF7
374 #define _WDT_ON 0x3FFF
375 #define _WDT_OFF 0x3FFB
376 #define _LP_OSC 0x3FFC
377 #define _XT_OSC 0x3FFD
378 #define _HS_OSC 0x3FFE
379 #define _RC_OSC 0x3FFF
383 // ----- ADCON0 bits --------------------
386 unsigned char ADON:1;
389 unsigned char CHS0:1;
390 unsigned char CHS1:1;
391 unsigned char CHS2:1;
392 unsigned char ADCS0:1;
393 unsigned char ADCS1:1;
398 unsigned char NOT_DONE:1;
408 unsigned char GO_DONE:1;
416 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
418 #define ADON ADCON0_bits.ADON
419 #define GO ADCON0_bits.GO
420 #define NOT_DONE ADCON0_bits.NOT_DONE
421 #define GO_DONE ADCON0_bits.GO_DONE
422 #define CHS0 ADCON0_bits.CHS0
423 #define CHS1 ADCON0_bits.CHS1
424 #define CHS2 ADCON0_bits.CHS2
425 #define ADCS0 ADCON0_bits.ADCS0
426 #define ADCS1 ADCON0_bits.ADCS1
428 // ----- ADCON1 bits --------------------
431 unsigned char PCFG0:1;
432 unsigned char PCFG1:1;
433 unsigned char PCFG2:1;
434 unsigned char PCFG3:1;
438 unsigned char ADFM:1;
441 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
443 #define PCFG0 ADCON1_bits.PCFG0
444 #define PCFG1 ADCON1_bits.PCFG1
445 #define PCFG2 ADCON1_bits.PCFG2
446 #define PCFG3 ADCON1_bits.PCFG3
447 #define ADFM ADCON1_bits.ADFM
449 // ----- CCP1CON bits --------------------
452 unsigned char CCP1M0:1;
453 unsigned char CCP1M1:1;
454 unsigned char CCP1M2:1;
455 unsigned char CCP1M3:1;
456 unsigned char CCP1Y:1;
457 unsigned char CCP1X:1;
462 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
464 #define CCP1M0 CCP1CON_bits.CCP1M0
465 #define CCP1M1 CCP1CON_bits.CCP1M1
466 #define CCP1M2 CCP1CON_bits.CCP1M2
467 #define CCP1M3 CCP1CON_bits.CCP1M3
468 #define CCP1Y CCP1CON_bits.CCP1Y
469 #define CCP1X CCP1CON_bits.CCP1X
471 // ----- INTCON bits --------------------
474 unsigned char RBIF:1;
475 unsigned char INTF:1;
476 unsigned char T0IF:1;
477 unsigned char RBIE:1;
478 unsigned char INTE:1;
479 unsigned char T0IE:1;
480 unsigned char PEIE:1;
484 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
486 #define RBIF INTCON_bits.RBIF
487 #define INTF INTCON_bits.INTF
488 #define T0IF INTCON_bits.T0IF
489 #define RBIE INTCON_bits.RBIE
490 #define INTE INTCON_bits.INTE
491 #define T0IE INTCON_bits.T0IE
492 #define PEIE INTCON_bits.PEIE
493 #define GIE INTCON_bits.GIE
495 // ----- LCDCON bits --------------------
498 unsigned char LMUX0:1;
499 unsigned char LMUX1:1;
502 unsigned char BIAS:1;
503 unsigned char WERR:1;
504 unsigned char SLPEN:1;
505 unsigned char LCDEN:1;
508 extern volatile __LCDCON_bits_t __at(LCDCON_ADDR) LCDCON_bits;
510 #define LMUX0 LCDCON_bits.LMUX0
511 #define LMUX1 LCDCON_bits.LMUX1
512 #define CS0 LCDCON_bits.CS0
513 #define CS1 LCDCON_bits.CS1
514 #define BIAS LCDCON_bits.BIAS
515 #define WERR LCDCON_bits.WERR
516 #define SLPEN LCDCON_bits.SLPEN
517 #define LCDEN LCDCON_bits.LCDEN
519 // ----- LCDPS bits --------------------
532 extern volatile __LCDPS_bits_t __at(LCDPS_ADDR) LCDPS_bits;
534 #define LP0 LCDPS_bits.LP0
535 #define LP1 LCDPS_bits.LP1
536 #define LP2 LCDPS_bits.LP2
537 #define LP3 LCDPS_bits.LP3
539 // ----- LCDSE bits --------------------
545 unsigned char SE12:1;
546 unsigned char SE16:1;
547 unsigned char SE20:1;
548 unsigned char SE27:1;
549 unsigned char SE29:1;
552 extern volatile __LCDSE_bits_t __at(LCDSE_ADDR) LCDSE_bits;
554 #define SE0 LCDSE_bits.SE0
555 #define SE5 LCDSE_bits.SE5
556 #define SE9 LCDSE_bits.SE9
557 #define SE12 LCDSE_bits.SE12
558 #define SE16 LCDSE_bits.SE16
559 #define SE20 LCDSE_bits.SE20
560 #define SE27 LCDSE_bits.SE27
561 #define SE29 LCDSE_bits.SE29
563 // ----- OPTION_REG bits --------------------
570 unsigned char T0SE:1;
571 unsigned char T0CS:1;
572 unsigned char INTEDG:1;
573 unsigned char NOT_RBPU:1;
575 } __OPTION_REG_bits_t;
576 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
578 #define PS0 OPTION_REG_bits.PS0
579 #define PS1 OPTION_REG_bits.PS1
580 #define PS2 OPTION_REG_bits.PS2
581 #define PSA OPTION_REG_bits.PSA
582 #define T0SE OPTION_REG_bits.T0SE
583 #define T0CS OPTION_REG_bits.T0CS
584 #define INTEDG OPTION_REG_bits.INTEDG
585 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
587 // ----- PCON bits --------------------
590 unsigned char NOT_BOR:1;
591 unsigned char NOT_POR:1;
600 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
602 #define NOT_BOR PCON_bits.NOT_BOR
603 #define NOT_POR PCON_bits.NOT_POR
605 // ----- PIE1 bits --------------------
608 unsigned char TMR1IE:1;
609 unsigned char TMR2IE:1;
610 unsigned char CCP1IE:1;
611 unsigned char SSPIE:1;
614 unsigned char ADIE:1;
615 unsigned char LCDIE:1;
618 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
620 #define TMR1IE PIE1_bits.TMR1IE
621 #define TMR2IE PIE1_bits.TMR2IE
622 #define CCP1IE PIE1_bits.CCP1IE
623 #define SSPIE PIE1_bits.SSPIE
624 #define ADIE PIE1_bits.ADIE
625 #define LCDIE PIE1_bits.LCDIE
627 // ----- PIR1 bits --------------------
630 unsigned char TMR1IF:1;
631 unsigned char TMR2IF:1;
632 unsigned char CCP1IF:1;
633 unsigned char SSPIF:1;
636 unsigned char ADIF:1;
637 unsigned char LCDIF:1;
640 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
642 #define TMR1IF PIR1_bits.TMR1IF
643 #define TMR2IF PIR1_bits.TMR2IF
644 #define CCP1IF PIR1_bits.CCP1IF
645 #define SSPIF PIR1_bits.SSPIF
646 #define ADIF PIR1_bits.ADIF
647 #define LCDIF PIR1_bits.LCDIF
649 // ----- PMCON1 bits --------------------
662 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
664 #define RD PMCON1_bits.RD
666 // ----- SSPCON bits --------------------
669 unsigned char SSPM0:1;
670 unsigned char SSPM1:1;
671 unsigned char SSPM2:1;
672 unsigned char SSPM3:1;
674 unsigned char SSPEN:1;
675 unsigned char SSPOV:1;
676 unsigned char WCOL:1;
679 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
681 #define SSPM0 SSPCON_bits.SSPM0
682 #define SSPM1 SSPCON_bits.SSPM1
683 #define SSPM2 SSPCON_bits.SSPM2
684 #define SSPM3 SSPCON_bits.SSPM3
685 #define CKP SSPCON_bits.CKP
686 #define SSPEN SSPCON_bits.SSPEN
687 #define SSPOV SSPCON_bits.SSPOV
688 #define WCOL SSPCON_bits.WCOL
690 // ----- SSPSTAT bits --------------------
705 unsigned char I2C_READ:1;
706 unsigned char I2C_START:1;
707 unsigned char I2C_STOP:1;
708 unsigned char I2C_DATA:1;
715 unsigned char NOT_W:1;
718 unsigned char NOT_A:1;
725 unsigned char NOT_WRITE:1;
728 unsigned char NOT_ADDRESS:1;
745 unsigned char READ_WRITE:1;
748 unsigned char DATA_ADDRESS:1;
753 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
755 #define BF SSPSTAT_bits.BF
756 #define UA SSPSTAT_bits.UA
757 #define R SSPSTAT_bits.R
758 #define I2C_READ SSPSTAT_bits.I2C_READ
759 #define NOT_W SSPSTAT_bits.NOT_W
760 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
761 #define R_W SSPSTAT_bits.R_W
762 #define READ_WRITE SSPSTAT_bits.READ_WRITE
763 #define S SSPSTAT_bits.S
764 #define I2C_START SSPSTAT_bits.I2C_START
765 #define P SSPSTAT_bits.P
766 #define I2C_STOP SSPSTAT_bits.I2C_STOP
767 #define D SSPSTAT_bits.D
768 #define I2C_DATA SSPSTAT_bits.I2C_DATA
769 #define NOT_A SSPSTAT_bits.NOT_A
770 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
771 #define D_A SSPSTAT_bits.D_A
772 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
773 #define CKE SSPSTAT_bits.CKE
774 #define SMP SSPSTAT_bits.SMP
776 // ----- STATUS bits --------------------
782 unsigned char NOT_PD:1;
783 unsigned char NOT_TO:1;
789 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
791 #define C STATUS_bits.C
792 #define DC STATUS_bits.DC
793 #define Z STATUS_bits.Z
794 #define NOT_PD STATUS_bits.NOT_PD
795 #define NOT_TO STATUS_bits.NOT_TO
796 #define RP0 STATUS_bits.RP0
797 #define RP1 STATUS_bits.RP1
798 #define IRP STATUS_bits.IRP
800 // ----- T1CON bits --------------------
803 unsigned char TMR1ON:1;
804 unsigned char TMR1CS:1;
805 unsigned char NOT_T1SYNC:1;
806 unsigned char T1OSCEN:1;
807 unsigned char T1CKPS0:1;
808 unsigned char T1CKPS1:1;
815 unsigned char T1INSYNC:1;
823 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
825 #define TMR1ON T1CON_bits.TMR1ON
826 #define TMR1CS T1CON_bits.TMR1CS
827 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
828 #define T1INSYNC T1CON_bits.T1INSYNC
829 #define T1OSCEN T1CON_bits.T1OSCEN
830 #define T1CKPS0 T1CON_bits.T1CKPS0
831 #define T1CKPS1 T1CON_bits.T1CKPS1
833 // ----- T2CON bits --------------------
836 unsigned char T2CKPS0:1;
837 unsigned char T2CKPS1:1;
838 unsigned char TMR2ON:1;
839 unsigned char TOUTPS0:1;
840 unsigned char TOUTPS1:1;
841 unsigned char TOUTPS2:1;
842 unsigned char TOUTPS3:1;
846 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
848 #define T2CKPS0 T2CON_bits.T2CKPS0
849 #define T2CKPS1 T2CON_bits.T2CKPS1
850 #define TMR2ON T2CON_bits.TMR2ON
851 #define TOUTPS0 T2CON_bits.TOUTPS0
852 #define TOUTPS1 T2CON_bits.TOUTPS1
853 #define TOUTPS2 T2CON_bits.TOUTPS2
854 #define TOUTPS3 T2CON_bits.TOUTPS3
856 // ----- TRISE bits --------------------
859 unsigned char TRISE0:1;
860 unsigned char TRISE1:1;
861 unsigned char TRISE2:1;
863 unsigned char PSPMODE:1;
864 unsigned char IBOV:1;
869 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
871 #define TRISE0 TRISE_bits.TRISE0
872 #define TRISE1 TRISE_bits.TRISE1
873 #define TRISE2 TRISE_bits.TRISE2
874 #define PSPMODE TRISE_bits.PSPMODE
875 #define IBOV TRISE_bits.IBOV
876 #define OBF TRISE_bits.OBF
877 #define IBF TRISE_bits.IBF