2 // Register Declarations for Microchip 16C782 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define ADRES_ADDR 0x001E
42 #define ADCON0_ADDR 0x001F
43 #define OPTION_REG_ADDR 0x0081
44 #define TRISA_ADDR 0x0085
45 #define TRISB_ADDR 0x0086
46 #define PIE1_ADDR 0x008C
47 #define PCON_ADDR 0x008E
48 #define WPUB_ADDR 0x0095
49 #define IOCB_ADDR 0x0096
50 #define REFCON_ADDR 0x009B
51 #define LVDCON_ADDR 0x009C
52 #define ANSEL_ADDR 0x009D
53 #define ADCON1_ADDR 0x009F
54 #define PMDATL_ADDR 0x010C
55 #define PMADRL_ADDR 0x010D
56 #define PMDATH_ADDR 0x010E
57 #define PMADRH_ADDR 0x010F
58 #define CALCON_ADDR 0x0110
59 #define PSMCCON0_ADDR 0x0111
60 #define PSMCCON1_ADDR 0x0112
61 #define CM1CON0_ADDR 0x0119
62 #define CM2CON0_ADDR 0x011A
63 #define CM2CON1_ADDR 0x011B
64 #define OPACON_ADDR 0x011C
65 #define DAC_ADDR 0x011E
66 #define DACON0_ADDR 0x011F
67 #define PMCON1_ADDR 0x018C
70 // Memory organization.
73 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
74 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
75 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
76 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
77 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
78 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
79 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
80 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
81 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
82 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
83 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
84 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
85 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
86 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
87 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
88 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
89 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
90 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
91 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
92 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
93 #pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB
94 #pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
95 #pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON
96 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
97 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
98 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
99 #pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL
100 #pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL
101 #pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
102 #pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
103 #pragma memmap CALCON_ADDR CALCON_ADDR SFR 0x000 // CALCON
104 #pragma memmap PSMCCON0_ADDR PSMCCON0_ADDR SFR 0x000 // PSMCCON0
105 #pragma memmap PSMCCON1_ADDR PSMCCON1_ADDR SFR 0x000 // PSMCCON1
106 #pragma memmap CM1CON0_ADDR CM1CON0_ADDR SFR 0x000 // CM1CON0
107 #pragma memmap CM2CON0_ADDR CM2CON0_ADDR SFR 0x000 // CM2CON0
108 #pragma memmap CM2CON1_ADDR CM2CON1_ADDR SFR 0x000 // CM2CON1
109 #pragma memmap OPACON_ADDR OPACON_ADDR SFR 0x000 // OPACON
110 #pragma memmap DAC_ADDR DAC_ADDR SFR 0x000 // DAC
111 #pragma memmap DACON0_ADDR DACON0_ADDR SFR 0x000 // DACON0
112 #pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
116 // P16C782.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
119 // This header file defines configurations, registers, and other useful bits of
120 // information for the PIC16C782 microcontroller. These names are taken to match
121 // the data sheets as closely as possible.
123 // Note that the processor must be selected before this file is
124 // included. The processor may be selected the following ways:
126 // 1. Command line switch:
127 // C:\ MPASM MYFILE.ASM /PIC16C782
128 // 2. LIST directive in the source file
130 // 3. Processor Type entry in the MPASM full-screen interface
132 //==========================================================================
136 //==========================================================================
140 //1.00 16May2001 Initial Release
142 //==========================================================================
146 //==========================================================================
149 // MESSG "Processor-header file mismatch. Verify selected processor."
152 //==========================================================================
154 // Register Definitions
156 //==========================================================================
161 //----- Register Files------------------------------------------------------
163 extern data __at (INDF_ADDR) volatile char INDF;
164 extern sfr __at (TMR0_ADDR) TMR0;
165 extern data __at (PCL_ADDR) volatile char PCL;
166 extern sfr __at (STATUS_ADDR) STATUS;
167 extern sfr __at (FSR_ADDR) FSR;
168 extern sfr __at (PORTA_ADDR) PORTA;
169 extern sfr __at (PORTB_ADDR) PORTB;
170 extern sfr __at (PCLATH_ADDR) PCLATH;
171 extern sfr __at (INTCON_ADDR) INTCON;
172 extern sfr __at (PIR1_ADDR) PIR1;
173 extern sfr __at (TMR1L_ADDR) TMR1L;
174 extern sfr __at (TMR1H_ADDR) TMR1H;
175 extern sfr __at (T1CON_ADDR) T1CON;
176 extern sfr __at (ADRES_ADDR) ADRES;
177 extern sfr __at (ADCON0_ADDR) ADCON0;
179 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
180 extern sfr __at (TRISA_ADDR) TRISA;
181 extern sfr __at (TRISB_ADDR) TRISB;
182 extern sfr __at (PIE1_ADDR) PIE1;
183 extern sfr __at (PCON_ADDR) PCON;
184 extern sfr __at (WPUB_ADDR) WPUB;
185 extern sfr __at (IOCB_ADDR) IOCB;
186 extern sfr __at (REFCON_ADDR) REFCON;
187 extern sfr __at (LVDCON_ADDR) LVDCON;
188 extern sfr __at (ANSEL_ADDR) ANSEL;
189 extern sfr __at (ADCON1_ADDR) ADCON1;
191 extern sfr __at (PMDATL_ADDR) PMDATL;
192 extern sfr __at (PMADRL_ADDR) PMADRL;
193 extern sfr __at (PMDATH_ADDR) PMDATH;
194 extern sfr __at (PMADRH_ADDR) PMADRH;
195 extern sfr __at (CALCON_ADDR) CALCON;
196 extern sfr __at (PSMCCON0_ADDR) PSMCCON0;
197 extern sfr __at (PSMCCON1_ADDR) PSMCCON1;
198 extern sfr __at (CM1CON0_ADDR) CM1CON0;
199 extern sfr __at (CM2CON0_ADDR) CM2CON0;
200 extern sfr __at (CM2CON1_ADDR) CM2CON1;
201 extern sfr __at (OPACON_ADDR) OPACON;
202 extern sfr __at (DAC_ADDR) DAC;
203 extern sfr __at (DACON0_ADDR) DACON0;
205 extern sfr __at (PMCON1_ADDR) PMCON1;
207 //----- STATUS Bits --------------------------------------------------------
210 //----- INTCON Bits --------------------------------------------------------
213 //----- PIR1 Bits ----------------------------------------------------------
216 //----- T1CON Bits ---------------------------------------------------------
219 //----- ADCON0 Bits --------------------------------------------------------
222 //----- OPTION Bits ----------------------------------------------------
225 //----- PIE1 Bits ----------------------------------------------------------
228 //----- PCON Bits ----------------------------------------------------------
231 //----- REFCON Bits --------------------------------------------------------
234 //----- LVDCON Bits --------------------------------------------------------
237 //----- ADCON1 Bits --------------------------------------------------------
240 //----- CALCON Bits --------------------------------------------------------
243 //----- PSMCCON0 Bits ------------------------------------------------------
246 //----- PSMCCON1 Bits ------------------------------------------------------
249 //----- CM1CON0 Bits ------------------------------------------------------
252 //----- CM2CON0 Bits ------------------------------------------------------
255 //----- CM2CON1 Bits ------------------------------------------------------
258 //----- OPACON Bits -------------------------------------------------------
261 //----- DACON0 Bits --------------------------------------------------------
264 //----- PMCON1 Bits -------------------------------------------------------
267 //==========================================================================
271 //==========================================================================
274 // __BADRAM H'07'-H'09', H'0D', H'11'-H'1D'
275 // __BADRAM H'87'-H'89', H'8D'
276 // __BADRAM H'8F'-H'94', H'97'-H'9A', H'9E', H'C0'-H'EF'
277 // __BADRAM H'105', H'107'-H'109', H'113'-H'118'
278 // __BADRAM H'11D', H'120'-H'16F'
279 // __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF'
281 //==========================================================================
283 // Configuration Bits
285 //==========================================================================
287 #define _BODEN_ON 0x3FFF
288 #define _BODEN_OFF 0x3FBF
289 #define _CP_ALL 0x0CFF
290 #define _CP_OFF 0x3FFF
291 #define _VBOR_25 0x3FFF
292 #define _VBOR_27 0x3BFF
293 #define _VBOR_42 0x37FF
294 #define _VBOR_45 0x33FF
295 #define _PWRTE_OFF 0x3FFF
296 #define _PWRTE_ON 0x3FEF
297 #define _MCLRE_OFF 0x3FDF
298 #define _MCLRE_ON 0x3FFF
299 #define _WDT_ON 0x3FFF
300 #define _WDT_OFF 0x3FF7
301 #define _ER_OSC_CLKOUT 0x3FFF
302 #define _ER_OSC_NOCLKOUT 0x3FFE
303 #define _INTRC_OSC_CLKOUT 0x3FFD
304 #define _INTRC_OSC_NOCLKOUT 0x3FFC
305 #define _EXTCLK_OSC 0x3FFB
306 #define _HS_OSC 0x3FFA
307 #define _XT_OSC 0x3FF9
308 #define _LP_OSC 0x3FF8
312 // ----- ADCON0 bits --------------------
315 unsigned char ADON:1;
316 unsigned char CHS3:1;
318 unsigned char CHS0:1;
319 unsigned char CHS1:1;
320 unsigned char CHS2:1;
321 unsigned char ADCS0:1;
322 unsigned char ADCS1:1;
327 unsigned char NOT_DONE:1;
337 unsigned char GO_DONE:1;
345 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
347 #define ADON ADCON0_bits.ADON
348 #define CHS3 ADCON0_bits.CHS3
349 #define GO ADCON0_bits.GO
350 #define NOT_DONE ADCON0_bits.NOT_DONE
351 #define GO_DONE ADCON0_bits.GO_DONE
352 #define CHS0 ADCON0_bits.CHS0
353 #define CHS1 ADCON0_bits.CHS1
354 #define CHS2 ADCON0_bits.CHS2
355 #define ADCS0 ADCON0_bits.ADCS0
356 #define ADCS1 ADCON0_bits.ADCS1
358 // ----- ADCON1 bits --------------------
365 unsigned char VCFG0:1;
366 unsigned char VCFG1:1;
371 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
373 #define VCFG0 ADCON1_bits.VCFG0
374 #define VCFG1 ADCON1_bits.VCFG1
376 // ----- CALCON bits --------------------
384 unsigned char CALREF:1;
385 unsigned char CALERR:1;
389 extern volatile __CALCON_bits_t __at(CALCON_ADDR) CALCON_bits;
391 #define CALREF CALCON_bits.CALREF
392 #define CALERR CALCON_bits.CALERR
393 #define CAL CALCON_bits.CAL
395 // ----- CM1CON0 bits --------------------
398 unsigned char C1CH0:1;
399 unsigned char C1CH1:1;
401 unsigned char C1SP:1;
402 unsigned char C1POL:1;
403 unsigned char C1OE:1;
404 unsigned char C1OUT:1;
405 unsigned char C1ON:1;
408 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
410 #define C1CH0 CM1CON0_bits.C1CH0
411 #define C1CH1 CM1CON0_bits.C1CH1
412 #define C1R CM1CON0_bits.C1R
413 #define C1SP CM1CON0_bits.C1SP
414 #define C1POL CM1CON0_bits.C1POL
415 #define C1OE CM1CON0_bits.C1OE
416 #define C1OUT CM1CON0_bits.C1OUT
417 #define C1ON CM1CON0_bits.C1ON
419 // ----- CM2CON0 bits --------------------
422 unsigned char C2CH0:1;
423 unsigned char C2CH1:1;
425 unsigned char C2SP:1;
426 unsigned char C2POL:1;
427 unsigned char C2OE:1;
428 unsigned char C2OUT:1;
429 unsigned char C2ON:1;
432 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
434 #define C2CH0 CM2CON0_bits.C2CH0
435 #define C2CH1 CM2CON0_bits.C2CH1
436 #define C2R CM2CON0_bits.C2R
437 #define C2SP CM2CON0_bits.C2SP
438 #define C2POL CM2CON0_bits.C2POL
439 #define C2OE CM2CON0_bits.C2OE
440 #define C2OUT CM2CON0_bits.C2OUT
441 #define C2ON CM2CON0_bits.C2ON
443 // ----- CM2CON1 bits --------------------
446 unsigned char C2SYNC:1;
452 unsigned char MC2OUT:1;
453 unsigned char MC1OUT:1;
456 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
458 #define C2SYNC CM2CON1_bits.C2SYNC
459 #define MC2OUT CM2CON1_bits.MC2OUT
460 #define MC1OUT CM2CON1_bits.MC1OUT
462 // ----- DACON0 bits --------------------
465 unsigned char DARS0:1;
466 unsigned char DARS1:1;
471 unsigned char DAOE:1;
472 unsigned char DAON:1;
475 extern volatile __DACON0_bits_t __at(DACON0_ADDR) DACON0_bits;
477 #define DARS0 DACON0_bits.DARS0
478 #define DARS1 DACON0_bits.DARS1
479 #define DAOE DACON0_bits.DAOE
480 #define DAON DACON0_bits.DAON
482 // ----- INTCON bits --------------------
485 unsigned char RBIF:1;
486 unsigned char INTF:1;
487 unsigned char T0IF:1;
488 unsigned char RBIE:1;
489 unsigned char INTE:1;
490 unsigned char T0IE:1;
491 unsigned char PEIE:1;
495 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
497 #define RBIF INTCON_bits.RBIF
498 #define INTF INTCON_bits.INTF
499 #define T0IF INTCON_bits.T0IF
500 #define RBIE INTCON_bits.RBIE
501 #define INTE INTCON_bits.INTE
502 #define T0IE INTCON_bits.T0IE
503 #define PEIE INTCON_bits.PEIE
504 #define GIE INTCON_bits.GIE
506 // ----- LVDCON bits --------------------
513 unsigned char LVDEN:1;
514 unsigned char BGST:1;
519 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
521 #define LV0 LVDCON_bits.LV0
522 #define LV1 LVDCON_bits.LV1
523 #define LV2 LVDCON_bits.LV2
524 #define LV3 LVDCON_bits.LV3
525 #define LVDEN LVDCON_bits.LVDEN
526 #define BGST LVDCON_bits.BGST
528 // ----- OPACON bits --------------------
531 unsigned char GBWP:1;
537 unsigned char CMPEN:1;
538 unsigned char OPAON:1;
541 extern volatile __OPACON_bits_t __at(OPACON_ADDR) OPACON_bits;
543 #define GBWP OPACON_bits.GBWP
544 #define CMPEN OPACON_bits.CMPEN
545 #define OPAON OPACON_bits.OPAON
547 // ----- OPTION_REG bits --------------------
554 unsigned char T0SE:1;
555 unsigned char T0CS:1;
556 unsigned char INTEDG:1;
557 unsigned char NOT_RBPU:1;
559 } __OPTION_REG_bits_t;
560 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
562 #define PS0 OPTION_REG_bits.PS0
563 #define PS1 OPTION_REG_bits.PS1
564 #define PS2 OPTION_REG_bits.PS2
565 #define PSA OPTION_REG_bits.PSA
566 #define T0SE OPTION_REG_bits.T0SE
567 #define T0CS OPTION_REG_bits.T0CS
568 #define INTEDG OPTION_REG_bits.INTEDG
569 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
571 // ----- PCON bits --------------------
574 unsigned char NOT_BO:1;
575 unsigned char NOT_POR:1;
577 unsigned char OSCF:1;
578 unsigned char WDTON:1;
584 unsigned char NOT_BOR:1;
594 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
596 #define NOT_BO PCON_bits.NOT_BO
597 #define NOT_BOR PCON_bits.NOT_BOR
598 #define NOT_POR PCON_bits.NOT_POR
599 #define OSCF PCON_bits.OSCF
600 #define WDTON PCON_bits.WDTON
602 // ----- PIE1 bits --------------------
605 unsigned char TMR1IE:1;
609 unsigned char C1IE:1;
610 unsigned char C2IE:1;
611 unsigned char ADIE:1;
612 unsigned char LVDIE:1;
615 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
617 #define TMR1IE PIE1_bits.TMR1IE
618 #define C1IE PIE1_bits.C1IE
619 #define C2IE PIE1_bits.C2IE
620 #define ADIE PIE1_bits.ADIE
621 #define LVDIE PIE1_bits.LVDIE
623 // ----- PIR1 bits --------------------
626 unsigned char TMR1IF:1;
630 unsigned char C1IF:1;
631 unsigned char C2IF:1;
632 unsigned char ADIF:1;
633 unsigned char LVDIF:1;
636 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
638 #define TMR1IF PIR1_bits.TMR1IF
639 #define C1IF PIR1_bits.C1IF
640 #define C2IF PIR1_bits.C2IF
641 #define ADIF PIR1_bits.ADIF
642 #define LVDIF PIR1_bits.LVDIF
644 // ----- PMCON1 bits --------------------
657 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
659 #define RD PMCON1_bits.RD
661 // ----- PSMCCON0 bits --------------------
666 unsigned char MAXDC0:1;
667 unsigned char MAXDC1:1;
668 unsigned char MINDC0:1;
669 unsigned char MINDC1:1;
670 unsigned char SMCCL0:1;
671 unsigned char SMCCL1:1;
674 extern volatile __PSMCCON0_bits_t __at(PSMCCON0_ADDR) PSMCCON0_bits;
676 #define DC0 PSMCCON0_bits.DC0
677 #define DC1 PSMCCON0_bits.DC1
678 #define MAXDC0 PSMCCON0_bits.MAXDC0
679 #define MAXDC1 PSMCCON0_bits.MAXDC1
680 #define MINDC0 PSMCCON0_bits.MINDC0
681 #define MINDC1 PSMCCON0_bits.MINDC1
682 #define SMCCL0 PSMCCON0_bits.SMCCL0
683 #define SMCCL1 PSMCCON0_bits.SMCCL1
685 // ----- PSMCCON1 bits --------------------
688 unsigned char SMCCS:1;
690 unsigned char SMCOM:1;
691 unsigned char SCEN:1;
693 unsigned char S1BPOL:1;
694 unsigned char S1APOL:1;
695 unsigned char SMCON:1;
709 unsigned char NOT_PSM:1;
718 extern volatile __PSMCCON1_bits_t __at(PSMCCON1_ADDR) PSMCCON1_bits;
720 #define SMCCS PSMCCON1_bits.SMCCS
721 #define PWM PSMCCON1_bits.PWM
722 #define PSM PSMCCON1_bits.PSM
723 #define NOT_PSM PSMCCON1_bits.NOT_PSM
724 #define SMCOM PSMCCON1_bits.SMCOM
725 #define SCEN PSMCCON1_bits.SCEN
726 #define S1BPOL PSMCCON1_bits.S1BPOL
727 #define S1APOL PSMCCON1_bits.S1APOL
728 #define SMCON PSMCCON1_bits.SMCON
730 // ----- REFCON bits --------------------
735 unsigned char VREFOE:1;
736 unsigned char VREFEN:1;
743 extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits;
745 #define VREFOE REFCON_bits.VREFOE
746 #define VREFEN REFCON_bits.VREFEN
748 // ----- STATUS bits --------------------
754 unsigned char NOT_PD:1;
755 unsigned char NOT_TO:1;
761 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
763 #define C STATUS_bits.C
764 #define DC STATUS_bits.DC
765 #define Z STATUS_bits.Z
766 #define NOT_PD STATUS_bits.NOT_PD
767 #define NOT_TO STATUS_bits.NOT_TO
768 #define RP0 STATUS_bits.RP0
769 #define RP1 STATUS_bits.RP1
770 #define IRP STATUS_bits.IRP
772 // ----- T1CON bits --------------------
775 unsigned char TMR1ON:1;
776 unsigned char TMR1CS:1;
777 unsigned char NOT_T1SYNC:1;
778 unsigned char T1OSCEN:1;
779 unsigned char T1CKPS0:1;
780 unsigned char T1CKPS1:1;
781 unsigned char TMR1GE:1;
787 unsigned char T1INSYNC:1;
795 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
797 #define TMR1ON T1CON_bits.TMR1ON
798 #define TMR1CS T1CON_bits.TMR1CS
799 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
800 #define T1INSYNC T1CON_bits.T1INSYNC
801 #define T1OSCEN T1CON_bits.T1OSCEN
802 #define T1CKPS0 T1CON_bits.T1CKPS0
803 #define T1CKPS1 T1CON_bits.T1CKPS1
804 #define TMR1GE T1CON_bits.TMR1GE