2 // Register Declarations for Microchip 16C782 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define TMR1L_ADDR 0x000E
39 #define TMR1H_ADDR 0x000F
40 #define T1CON_ADDR 0x0010
41 #define ADRES_ADDR 0x001E
42 #define ADCON0_ADDR 0x001F
43 #define OPTION_REG_ADDR 0x0081
44 #define TRISA_ADDR 0x0085
45 #define TRISB_ADDR 0x0086
46 #define PIE1_ADDR 0x008C
47 #define PCON_ADDR 0x008E
48 #define WPUB_ADDR 0x0095
49 #define IOCB_ADDR 0x0096
50 #define REFCON_ADDR 0x009B
51 #define LVDCON_ADDR 0x009C
52 #define ANSEL_ADDR 0x009D
53 #define ADCON1_ADDR 0x009F
54 #define PMDATL_ADDR 0x010C
55 #define PMADRL_ADDR 0x010D
56 #define PMDATH_ADDR 0x010E
57 #define PMADRH_ADDR 0x010F
58 #define CALCON_ADDR 0x0110
59 #define PSMCCON0_ADDR 0x0111
60 #define PSMCCON1_ADDR 0x0112
61 #define CM1CON0_ADDR 0x0119
62 #define CM2CON0_ADDR 0x011A
63 #define CM2CON1_ADDR 0x011B
64 #define OPACON_ADDR 0x011C
65 #define DAC_ADDR 0x011E
66 #define DACON0_ADDR 0x011F
67 #define PMCON1_ADDR 0x018C
70 // Memory organization.
76 // P16C782.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
79 // This header file defines configurations, registers, and other useful bits of
80 // information for the PIC16C782 microcontroller. These names are taken to match
81 // the data sheets as closely as possible.
83 // Note that the processor must be selected before this file is
84 // included. The processor may be selected the following ways:
86 // 1. Command line switch:
87 // C:\ MPASM MYFILE.ASM /PIC16C782
88 // 2. LIST directive in the source file
90 // 3. Processor Type entry in the MPASM full-screen interface
92 //==========================================================================
96 //==========================================================================
100 //1.00 16May2001 Initial Release
102 //==========================================================================
106 //==========================================================================
109 // MESSG "Processor-header file mismatch. Verify selected processor."
112 //==========================================================================
114 // Register Definitions
116 //==========================================================================
121 //----- Register Files------------------------------------------------------
123 extern __data __at (INDF_ADDR) volatile char INDF;
124 extern __sfr __at (TMR0_ADDR) TMR0;
125 extern __data __at (PCL_ADDR) volatile char PCL;
126 extern __sfr __at (STATUS_ADDR) STATUS;
127 extern __sfr __at (FSR_ADDR) FSR;
128 extern __sfr __at (PORTA_ADDR) PORTA;
129 extern __sfr __at (PORTB_ADDR) PORTB;
130 extern __sfr __at (PCLATH_ADDR) PCLATH;
131 extern __sfr __at (INTCON_ADDR) INTCON;
132 extern __sfr __at (PIR1_ADDR) PIR1;
133 extern __sfr __at (TMR1L_ADDR) TMR1L;
134 extern __sfr __at (TMR1H_ADDR) TMR1H;
135 extern __sfr __at (T1CON_ADDR) T1CON;
136 extern __sfr __at (ADRES_ADDR) ADRES;
137 extern __sfr __at (ADCON0_ADDR) ADCON0;
139 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
140 extern __sfr __at (TRISA_ADDR) TRISA;
141 extern __sfr __at (TRISB_ADDR) TRISB;
142 extern __sfr __at (PIE1_ADDR) PIE1;
143 extern __sfr __at (PCON_ADDR) PCON;
144 extern __sfr __at (WPUB_ADDR) WPUB;
145 extern __sfr __at (IOCB_ADDR) IOCB;
146 extern __sfr __at (REFCON_ADDR) REFCON;
147 extern __sfr __at (LVDCON_ADDR) LVDCON;
148 extern __sfr __at (ANSEL_ADDR) ANSEL;
149 extern __sfr __at (ADCON1_ADDR) ADCON1;
151 extern __sfr __at (PMDATL_ADDR) PMDATL;
152 extern __sfr __at (PMADRL_ADDR) PMADRL;
153 extern __sfr __at (PMDATH_ADDR) PMDATH;
154 extern __sfr __at (PMADRH_ADDR) PMADRH;
155 extern __sfr __at (CALCON_ADDR) CALCON;
156 extern __sfr __at (PSMCCON0_ADDR) PSMCCON0;
157 extern __sfr __at (PSMCCON1_ADDR) PSMCCON1;
158 extern __sfr __at (CM1CON0_ADDR) CM1CON0;
159 extern __sfr __at (CM2CON0_ADDR) CM2CON0;
160 extern __sfr __at (CM2CON1_ADDR) CM2CON1;
161 extern __sfr __at (OPACON_ADDR) OPACON;
162 extern __sfr __at (DAC_ADDR) DAC;
163 extern __sfr __at (DACON0_ADDR) DACON0;
165 extern __sfr __at (PMCON1_ADDR) PMCON1;
167 //----- STATUS Bits --------------------------------------------------------
170 //----- INTCON Bits --------------------------------------------------------
173 //----- PIR1 Bits ----------------------------------------------------------
176 //----- T1CON Bits ---------------------------------------------------------
179 //----- ADCON0 Bits --------------------------------------------------------
182 //----- OPTION Bits ----------------------------------------------------
185 //----- PIE1 Bits ----------------------------------------------------------
188 //----- PCON Bits ----------------------------------------------------------
191 //----- REFCON Bits --------------------------------------------------------
194 //----- LVDCON Bits --------------------------------------------------------
197 //----- ADCON1 Bits --------------------------------------------------------
200 //----- CALCON Bits --------------------------------------------------------
203 //----- PSMCCON0 Bits ------------------------------------------------------
206 //----- PSMCCON1 Bits ------------------------------------------------------
209 //----- CM1CON0 Bits ------------------------------------------------------
212 //----- CM2CON0 Bits ------------------------------------------------------
215 //----- CM2CON1 Bits ------------------------------------------------------
218 //----- OPACON Bits -------------------------------------------------------
221 //----- DACON0 Bits --------------------------------------------------------
224 //----- PMCON1 Bits -------------------------------------------------------
227 //==========================================================================
231 //==========================================================================
234 // __BADRAM H'07'-H'09', H'0D', H'11'-H'1D'
235 // __BADRAM H'87'-H'89', H'8D'
236 // __BADRAM H'8F'-H'94', H'97'-H'9A', H'9E', H'C0'-H'EF'
237 // __BADRAM H'105', H'107'-H'109', H'113'-H'118'
238 // __BADRAM H'11D', H'120'-H'16F'
239 // __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF'
241 //==========================================================================
243 // Configuration Bits
245 //==========================================================================
247 #define _BODEN_ON 0x3FFF
248 #define _BODEN_OFF 0x3FBF
249 #define _CP_ALL 0x0CFF
250 #define _CP_OFF 0x3FFF
251 #define _VBOR_25 0x3FFF
252 #define _VBOR_27 0x3BFF
253 #define _VBOR_42 0x37FF
254 #define _VBOR_45 0x33FF
255 #define _PWRTE_OFF 0x3FFF
256 #define _PWRTE_ON 0x3FEF
257 #define _MCLRE_OFF 0x3FDF
258 #define _MCLRE_ON 0x3FFF
259 #define _WDT_ON 0x3FFF
260 #define _WDT_OFF 0x3FF7
261 #define _ER_OSC_CLKOUT 0x3FFF
262 #define _ER_OSC_NOCLKOUT 0x3FFE
263 #define _INTRC_OSC_CLKOUT 0x3FFD
264 #define _INTRC_OSC_NOCLKOUT 0x3FFC
265 #define _EXTCLK_OSC 0x3FFB
266 #define _HS_OSC 0x3FFA
267 #define _XT_OSC 0x3FF9
268 #define _LP_OSC 0x3FF8
272 // ----- ADCON0 bits --------------------
275 unsigned char ADON:1;
276 unsigned char CHS3:1;
278 unsigned char CHS0:1;
279 unsigned char CHS1:1;
280 unsigned char CHS2:1;
281 unsigned char ADCS0:1;
282 unsigned char ADCS1:1;
287 unsigned char NOT_DONE:1;
297 unsigned char GO_DONE:1;
305 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
307 #define ADON ADCON0_bits.ADON
308 #define CHS3 ADCON0_bits.CHS3
309 #define GO ADCON0_bits.GO
310 #define NOT_DONE ADCON0_bits.NOT_DONE
311 #define GO_DONE ADCON0_bits.GO_DONE
312 #define CHS0 ADCON0_bits.CHS0
313 #define CHS1 ADCON0_bits.CHS1
314 #define CHS2 ADCON0_bits.CHS2
315 #define ADCS0 ADCON0_bits.ADCS0
316 #define ADCS1 ADCON0_bits.ADCS1
318 // ----- ADCON1 bits --------------------
325 unsigned char VCFG0:1;
326 unsigned char VCFG1:1;
331 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
333 #define VCFG0 ADCON1_bits.VCFG0
334 #define VCFG1 ADCON1_bits.VCFG1
336 // ----- CALCON bits --------------------
344 unsigned char CALREF:1;
345 unsigned char CALERR:1;
349 extern volatile __CALCON_bits_t __at(CALCON_ADDR) CALCON_bits;
351 #define CALREF CALCON_bits.CALREF
352 #define CALERR CALCON_bits.CALERR
353 #define CAL CALCON_bits.CAL
355 // ----- CM1CON0 bits --------------------
358 unsigned char C1CH0:1;
359 unsigned char C1CH1:1;
361 unsigned char C1SP:1;
362 unsigned char C1POL:1;
363 unsigned char C1OE:1;
364 unsigned char C1OUT:1;
365 unsigned char C1ON:1;
368 extern volatile __CM1CON0_bits_t __at(CM1CON0_ADDR) CM1CON0_bits;
370 #define C1CH0 CM1CON0_bits.C1CH0
371 #define C1CH1 CM1CON0_bits.C1CH1
372 #define C1R CM1CON0_bits.C1R
373 #define C1SP CM1CON0_bits.C1SP
374 #define C1POL CM1CON0_bits.C1POL
375 #define C1OE CM1CON0_bits.C1OE
376 #define C1OUT CM1CON0_bits.C1OUT
377 #define C1ON CM1CON0_bits.C1ON
379 // ----- CM2CON0 bits --------------------
382 unsigned char C2CH0:1;
383 unsigned char C2CH1:1;
385 unsigned char C2SP:1;
386 unsigned char C2POL:1;
387 unsigned char C2OE:1;
388 unsigned char C2OUT:1;
389 unsigned char C2ON:1;
392 extern volatile __CM2CON0_bits_t __at(CM2CON0_ADDR) CM2CON0_bits;
394 #define C2CH0 CM2CON0_bits.C2CH0
395 #define C2CH1 CM2CON0_bits.C2CH1
396 #define C2R CM2CON0_bits.C2R
397 #define C2SP CM2CON0_bits.C2SP
398 #define C2POL CM2CON0_bits.C2POL
399 #define C2OE CM2CON0_bits.C2OE
400 #define C2OUT CM2CON0_bits.C2OUT
401 #define C2ON CM2CON0_bits.C2ON
403 // ----- CM2CON1 bits --------------------
406 unsigned char C2SYNC:1;
412 unsigned char MC2OUT:1;
413 unsigned char MC1OUT:1;
416 extern volatile __CM2CON1_bits_t __at(CM2CON1_ADDR) CM2CON1_bits;
418 #define C2SYNC CM2CON1_bits.C2SYNC
419 #define MC2OUT CM2CON1_bits.MC2OUT
420 #define MC1OUT CM2CON1_bits.MC1OUT
422 // ----- DACON0 bits --------------------
425 unsigned char DARS0:1;
426 unsigned char DARS1:1;
431 unsigned char DAOE:1;
432 unsigned char DAON:1;
435 extern volatile __DACON0_bits_t __at(DACON0_ADDR) DACON0_bits;
437 #define DARS0 DACON0_bits.DARS0
438 #define DARS1 DACON0_bits.DARS1
439 #define DAOE DACON0_bits.DAOE
440 #define DAON DACON0_bits.DAON
442 // ----- INTCON bits --------------------
445 unsigned char RBIF:1;
446 unsigned char INTF:1;
447 unsigned char T0IF:1;
448 unsigned char RBIE:1;
449 unsigned char INTE:1;
450 unsigned char T0IE:1;
451 unsigned char PEIE:1;
455 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
457 #define RBIF INTCON_bits.RBIF
458 #define INTF INTCON_bits.INTF
459 #define T0IF INTCON_bits.T0IF
460 #define RBIE INTCON_bits.RBIE
461 #define INTE INTCON_bits.INTE
462 #define T0IE INTCON_bits.T0IE
463 #define PEIE INTCON_bits.PEIE
464 #define GIE INTCON_bits.GIE
466 // ----- LVDCON bits --------------------
473 unsigned char LVDEN:1;
474 unsigned char BGST:1;
479 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
481 #define LV0 LVDCON_bits.LV0
482 #define LV1 LVDCON_bits.LV1
483 #define LV2 LVDCON_bits.LV2
484 #define LV3 LVDCON_bits.LV3
485 #define LVDEN LVDCON_bits.LVDEN
486 #define BGST LVDCON_bits.BGST
488 // ----- OPACON bits --------------------
491 unsigned char GBWP:1;
497 unsigned char CMPEN:1;
498 unsigned char OPAON:1;
501 extern volatile __OPACON_bits_t __at(OPACON_ADDR) OPACON_bits;
503 #define GBWP OPACON_bits.GBWP
504 #define CMPEN OPACON_bits.CMPEN
505 #define OPAON OPACON_bits.OPAON
507 // ----- OPTION_REG bits --------------------
514 unsigned char T0SE:1;
515 unsigned char T0CS:1;
516 unsigned char INTEDG:1;
517 unsigned char NOT_RBPU:1;
519 } __OPTION_REG_bits_t;
520 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
522 #define PS0 OPTION_REG_bits.PS0
523 #define PS1 OPTION_REG_bits.PS1
524 #define PS2 OPTION_REG_bits.PS2
525 #define PSA OPTION_REG_bits.PSA
526 #define T0SE OPTION_REG_bits.T0SE
527 #define T0CS OPTION_REG_bits.T0CS
528 #define INTEDG OPTION_REG_bits.INTEDG
529 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
531 // ----- PCON bits --------------------
534 unsigned char NOT_BO:1;
535 unsigned char NOT_POR:1;
537 unsigned char OSCF:1;
538 unsigned char WDTON:1;
544 unsigned char NOT_BOR:1;
554 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
556 #define NOT_BO PCON_bits.NOT_BO
557 #define NOT_BOR PCON_bits.NOT_BOR
558 #define NOT_POR PCON_bits.NOT_POR
559 #define OSCF PCON_bits.OSCF
560 #define WDTON PCON_bits.WDTON
562 // ----- PIE1 bits --------------------
565 unsigned char TMR1IE:1;
569 unsigned char C1IE:1;
570 unsigned char C2IE:1;
571 unsigned char ADIE:1;
572 unsigned char LVDIE:1;
575 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
577 #define TMR1IE PIE1_bits.TMR1IE
578 #define C1IE PIE1_bits.C1IE
579 #define C2IE PIE1_bits.C2IE
580 #define ADIE PIE1_bits.ADIE
581 #define LVDIE PIE1_bits.LVDIE
583 // ----- PIR1 bits --------------------
586 unsigned char TMR1IF:1;
590 unsigned char C1IF:1;
591 unsigned char C2IF:1;
592 unsigned char ADIF:1;
593 unsigned char LVDIF:1;
596 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
598 #define TMR1IF PIR1_bits.TMR1IF
599 #define C1IF PIR1_bits.C1IF
600 #define C2IF PIR1_bits.C2IF
601 #define ADIF PIR1_bits.ADIF
602 #define LVDIF PIR1_bits.LVDIF
604 // ----- PMCON1 bits --------------------
617 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
619 #define RD PMCON1_bits.RD
621 // ----- PSMCCON0 bits --------------------
626 unsigned char MAXDC0:1;
627 unsigned char MAXDC1:1;
628 unsigned char MINDC0:1;
629 unsigned char MINDC1:1;
630 unsigned char SMCCL0:1;
631 unsigned char SMCCL1:1;
634 extern volatile __PSMCCON0_bits_t __at(PSMCCON0_ADDR) PSMCCON0_bits;
636 #define DC0 PSMCCON0_bits.DC0
637 #define DC1 PSMCCON0_bits.DC1
638 #define MAXDC0 PSMCCON0_bits.MAXDC0
639 #define MAXDC1 PSMCCON0_bits.MAXDC1
640 #define MINDC0 PSMCCON0_bits.MINDC0
641 #define MINDC1 PSMCCON0_bits.MINDC1
642 #define SMCCL0 PSMCCON0_bits.SMCCL0
643 #define SMCCL1 PSMCCON0_bits.SMCCL1
645 // ----- PSMCCON1 bits --------------------
648 unsigned char SMCCS:1;
650 unsigned char SMCOM:1;
651 unsigned char SCEN:1;
653 unsigned char S1BPOL:1;
654 unsigned char S1APOL:1;
655 unsigned char SMCON:1;
669 unsigned char NOT_PSM:1;
678 extern volatile __PSMCCON1_bits_t __at(PSMCCON1_ADDR) PSMCCON1_bits;
680 #define SMCCS PSMCCON1_bits.SMCCS
681 #define PWM PSMCCON1_bits.PWM
682 #define PSM PSMCCON1_bits.PSM
683 #define NOT_PSM PSMCCON1_bits.NOT_PSM
684 #define SMCOM PSMCCON1_bits.SMCOM
685 #define SCEN PSMCCON1_bits.SCEN
686 #define S1BPOL PSMCCON1_bits.S1BPOL
687 #define S1APOL PSMCCON1_bits.S1APOL
688 #define SMCON PSMCCON1_bits.SMCON
690 // ----- REFCON bits --------------------
695 unsigned char VREFOE:1;
696 unsigned char VREFEN:1;
703 extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits;
705 #define VREFOE REFCON_bits.VREFOE
706 #define VREFEN REFCON_bits.VREFEN
708 // ----- STATUS bits --------------------
714 unsigned char NOT_PD:1;
715 unsigned char NOT_TO:1;
721 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
723 #define C STATUS_bits.C
724 #define DC STATUS_bits.DC
725 #define Z STATUS_bits.Z
726 #define NOT_PD STATUS_bits.NOT_PD
727 #define NOT_TO STATUS_bits.NOT_TO
728 #define RP0 STATUS_bits.RP0
729 #define RP1 STATUS_bits.RP1
730 #define IRP STATUS_bits.IRP
732 // ----- T1CON bits --------------------
735 unsigned char TMR1ON:1;
736 unsigned char TMR1CS:1;
737 unsigned char NOT_T1SYNC:1;
738 unsigned char T1OSCEN:1;
739 unsigned char T1CKPS0:1;
740 unsigned char T1CKPS1:1;
741 unsigned char TMR1GE:1;
747 unsigned char T1INSYNC:1;
755 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
757 #define TMR1ON T1CON_bits.TMR1ON
758 #define TMR1CS T1CON_bits.TMR1CS
759 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
760 #define T1INSYNC T1CON_bits.T1INSYNC
761 #define T1OSCEN T1CON_bits.T1OSCEN
762 #define T1CKPS0 T1CON_bits.T1CKPS0
763 #define T1CKPS1 T1CON_bits.T1CKPS1
764 #define TMR1GE T1CON_bits.TMR1GE