2 // Register Declarations for Microchip 16C774 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define TXSTA_ADDR 0x0098
74 #define SPBRG_ADDR 0x0099
75 #define REFCON_ADDR 0x009B
76 #define LVDCON_ADDR 0x009C
77 #define ADRESL_ADDR 0x009E
78 #define ADCON1_ADDR 0x009F
81 // Memory organization.
84 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
85 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
86 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
87 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
88 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
89 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
90 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
91 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
92 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
93 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
94 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
95 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
96 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
97 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
98 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
99 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
100 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
101 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
102 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
103 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
104 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
105 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
106 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
107 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
108 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
109 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
110 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
111 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
112 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
113 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
114 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
115 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
116 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
117 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
118 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
119 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
120 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
121 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
122 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
123 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
124 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
125 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
126 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
127 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
128 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
129 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
130 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
131 #pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON
132 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
133 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
134 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
138 // P16C774.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
141 // This header file defines configurations, registers, and other useful bits of
142 // information for the PIC16C774 microcontroller. These names are taken to match
143 // the data sheets as closely as possible.
145 // Note that the processor must be selected before this file is
146 // included. The processor may be selected the following ways:
148 // 1. Command line switch:
149 // C:\ MPASM MYFILE.ASM /PIC16C774
150 // 2. LIST directive in the source file
152 // 3. Processor Type entry in the MPASM full-screen interface
154 //==========================================================================
158 //==========================================================================
162 //1.00 08/07/98 Initial Release
163 //1.01 25Jan99 Fixed LVVx bits
165 //==========================================================================
169 //==========================================================================
172 // MESSG "Processor-header file mismatch. Verify selected processor."
175 //==========================================================================
177 // Register Definitions
179 //==========================================================================
184 //----- Register Files------------------------------------------------------
186 extern __data __at (INDF_ADDR) volatile char INDF;
187 extern __sfr __at (TMR0_ADDR) TMR0;
188 extern __data __at (PCL_ADDR) volatile char PCL;
189 extern __sfr __at (STATUS_ADDR) STATUS;
190 extern __sfr __at (FSR_ADDR) FSR;
191 extern __sfr __at (PORTA_ADDR) PORTA;
192 extern __sfr __at (PORTB_ADDR) PORTB;
193 extern __sfr __at (PORTC_ADDR) PORTC;
194 extern __sfr __at (PORTD_ADDR) PORTD;
195 extern __sfr __at (PORTE_ADDR) PORTE;
196 extern __sfr __at (PCLATH_ADDR) PCLATH;
197 extern __sfr __at (INTCON_ADDR) INTCON;
198 extern __sfr __at (PIR1_ADDR) PIR1;
199 extern __sfr __at (PIR2_ADDR) PIR2;
200 extern __sfr __at (TMR1L_ADDR) TMR1L;
201 extern __sfr __at (TMR1H_ADDR) TMR1H;
202 extern __sfr __at (T1CON_ADDR) T1CON;
203 extern __sfr __at (TMR2_ADDR) TMR2;
204 extern __sfr __at (T2CON_ADDR) T2CON;
205 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
206 extern __sfr __at (SSPCON_ADDR) SSPCON;
207 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
208 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
209 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
210 extern __sfr __at (RCSTA_ADDR) RCSTA;
211 extern __sfr __at (TXREG_ADDR) TXREG;
212 extern __sfr __at (RCREG_ADDR) RCREG;
213 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
214 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
215 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
216 extern __sfr __at (ADRESH_ADDR) ADRESH;
217 extern __sfr __at (ADCON0_ADDR) ADCON0;
219 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
220 extern __sfr __at (TRISA_ADDR) TRISA;
221 extern __sfr __at (TRISB_ADDR) TRISB;
222 extern __sfr __at (TRISC_ADDR) TRISC;
223 extern __sfr __at (TRISD_ADDR) TRISD;
224 extern __sfr __at (TRISE_ADDR) TRISE;
225 extern __sfr __at (PIE1_ADDR) PIE1;
226 extern __sfr __at (PIE2_ADDR) PIE2;
227 extern __sfr __at (PCON_ADDR) PCON;
228 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
229 extern __sfr __at (PR2_ADDR) PR2;
230 extern __sfr __at (SSPADD_ADDR) SSPADD;
231 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
232 extern __sfr __at (TXSTA_ADDR) TXSTA;
233 extern __sfr __at (SPBRG_ADDR) SPBRG;
234 extern __sfr __at (REFCON_ADDR) REFCON;
235 extern __sfr __at (LVDCON_ADDR) LVDCON;
236 extern __sfr __at (ADRESL_ADDR) ADRESL;
237 extern __sfr __at (ADCON1_ADDR) ADCON1;
239 //----- STATUS Bits --------------------------------------------------------
242 //----- INTCON Bits --------------------------------------------------------
245 //----- PIR1 Bits ----------------------------------------------------------
248 //----- PIR2 Bits ----------------------------------------------------------
251 //----- T1CON Bits ---------------------------------------------------------
254 //----- T2CON Bits ---------------------------------------------------------
257 //----- SSPCON Bits --------------------------------------------------------
260 //----- CCP1CON Bits -------------------------------------------------------
263 //----- RCSTA Bits ---------------------------------------------------------
266 //----- CCP2CON Bits -------------------------------------------------------
269 //----- ADCON0 Bits --------------------------------------------------------
272 //----- OPTION Bits ----------------------------------------------------
275 //----- TRISE Bits ---------------------------------------------------------
278 //----- PIE1 Bits ----------------------------------------------------------
281 //----- PIE2 Bits ----------------------------------------------------------
284 //----- PCON Bits ----------------------------------------------------------
287 //----- SSPCON2 Bits --------------------------------------------------------
290 //----- SSPSTAT Bits -------------------------------------------------------
293 //----- TXSTA Bits ---------------------------------------------------------
296 //----- REFCON Bits --------------------------------------------------------
299 //----- LVDCON Bits --------------------------------------------------------
302 //----- ADCON1 Bits --------------------------------------------------------
305 //==========================================================================
309 //==========================================================================
312 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A', H'9D'
313 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F'
314 // __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF'
316 //==========================================================================
318 // Configuration Bits
320 //==========================================================================
322 #define _BODEN_ON 0x3FFF
323 #define _BODEN_OFF 0x3FBF
324 #define _CP_ALL 0x0CCF
325 #define _CP_75 0x1DDF
326 #define _CP_50 0x2EEF
327 #define _CP_OFF 0x3FFF
328 #define _VBOR_25 0x3FFF
329 #define _VBOR_27 0x3BFF
330 #define _VBOR_42 0x37FF
331 #define _VBOR_45 0x33FF
332 #define _PWRTE_OFF 0x3FFF
333 #define _PWRTE_ON 0x3FF7
334 #define _WDT_ON 0x3FFF
335 #define _WDT_OFF 0x3FFB
336 #define _LP_OSC 0x3FFC
337 #define _XT_OSC 0x3FFD
338 #define _HS_OSC 0x3FFE
339 #define _RC_OSC 0x3FFF
343 // ----- ADCON0 bits --------------------
346 unsigned char ADON:1;
347 unsigned char CHS3:1;
349 unsigned char CHS0:1;
350 unsigned char CHS1:1;
351 unsigned char CHS2:1;
352 unsigned char ADCS0:1;
353 unsigned char ADCS1:1;
358 unsigned char NOT_DONE:1;
368 unsigned char GO_DONE:1;
376 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
378 #define ADON ADCON0_bits.ADON
379 #define CHS3 ADCON0_bits.CHS3
380 #define GO ADCON0_bits.GO
381 #define NOT_DONE ADCON0_bits.NOT_DONE
382 #define GO_DONE ADCON0_bits.GO_DONE
383 #define CHS0 ADCON0_bits.CHS0
384 #define CHS1 ADCON0_bits.CHS1
385 #define CHS2 ADCON0_bits.CHS2
386 #define ADCS0 ADCON0_bits.ADCS0
387 #define ADCS1 ADCON0_bits.ADCS1
389 // ----- ADCON1 bits --------------------
392 unsigned char PCFG0:1;
393 unsigned char PCFG1:1;
394 unsigned char PCFG2:1;
395 unsigned char PCFG3:1;
396 unsigned char VCFG0:1;
397 unsigned char VCFG1:1;
398 unsigned char VCFG2:1;
399 unsigned char ADFM:1;
402 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
404 #define PCFG0 ADCON1_bits.PCFG0
405 #define PCFG1 ADCON1_bits.PCFG1
406 #define PCFG2 ADCON1_bits.PCFG2
407 #define PCFG3 ADCON1_bits.PCFG3
408 #define VCFG0 ADCON1_bits.VCFG0
409 #define VCFG1 ADCON1_bits.VCFG1
410 #define VCFG2 ADCON1_bits.VCFG2
411 #define ADFM ADCON1_bits.ADFM
413 // ----- CCP1CON bits --------------------
416 unsigned char CCP1M0:1;
417 unsigned char CCP1M1:1;
418 unsigned char CCP1M2:1;
419 unsigned char CCP1M3:1;
420 unsigned char CCP1Y:1;
421 unsigned char CCP1X:1;
426 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
428 #define CCP1M0 CCP1CON_bits.CCP1M0
429 #define CCP1M1 CCP1CON_bits.CCP1M1
430 #define CCP1M2 CCP1CON_bits.CCP1M2
431 #define CCP1M3 CCP1CON_bits.CCP1M3
432 #define CCP1Y CCP1CON_bits.CCP1Y
433 #define CCP1X CCP1CON_bits.CCP1X
435 // ----- CCP2CON bits --------------------
438 unsigned char CCP2M0:1;
439 unsigned char CCP2M1:1;
440 unsigned char CCP2M2:1;
441 unsigned char CCP2M3:1;
442 unsigned char CCP2Y:1;
443 unsigned char CCP2X:1;
448 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
450 #define CCP2M0 CCP2CON_bits.CCP2M0
451 #define CCP2M1 CCP2CON_bits.CCP2M1
452 #define CCP2M2 CCP2CON_bits.CCP2M2
453 #define CCP2M3 CCP2CON_bits.CCP2M3
454 #define CCP2Y CCP2CON_bits.CCP2Y
455 #define CCP2X CCP2CON_bits.CCP2X
457 // ----- INTCON bits --------------------
460 unsigned char RBIF:1;
461 unsigned char INTF:1;
462 unsigned char T0IF:1;
463 unsigned char RBIE:1;
464 unsigned char INTE:1;
465 unsigned char T0IE:1;
466 unsigned char PEIE:1;
470 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
472 #define RBIF INTCON_bits.RBIF
473 #define INTF INTCON_bits.INTF
474 #define T0IF INTCON_bits.T0IF
475 #define RBIE INTCON_bits.RBIE
476 #define INTE INTCON_bits.INTE
477 #define T0IE INTCON_bits.T0IE
478 #define PEIE INTCON_bits.PEIE
479 #define GIE INTCON_bits.GIE
481 // ----- LVDCON bits --------------------
488 unsigned char LVDEN:1;
489 unsigned char BGST:1;
494 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
496 #define LV0 LVDCON_bits.LV0
497 #define LV1 LVDCON_bits.LV1
498 #define LV2 LVDCON_bits.LV2
499 #define LV3 LVDCON_bits.LV3
500 #define LVDEN LVDCON_bits.LVDEN
501 #define BGST LVDCON_bits.BGST
503 // ----- OPTION_REG bits --------------------
510 unsigned char T0SE:1;
511 unsigned char T0CS:1;
512 unsigned char INTEDG:1;
513 unsigned char NOT_RBPU:1;
515 } __OPTION_REG_bits_t;
516 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
518 #define PS0 OPTION_REG_bits.PS0
519 #define PS1 OPTION_REG_bits.PS1
520 #define PS2 OPTION_REG_bits.PS2
521 #define PSA OPTION_REG_bits.PSA
522 #define T0SE OPTION_REG_bits.T0SE
523 #define T0CS OPTION_REG_bits.T0CS
524 #define INTEDG OPTION_REG_bits.INTEDG
525 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
527 // ----- PCON bits --------------------
530 unsigned char NOT_BO:1;
531 unsigned char NOT_POR:1;
540 unsigned char NOT_BOR:1;
550 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
552 #define NOT_BO PCON_bits.NOT_BO
553 #define NOT_BOR PCON_bits.NOT_BOR
554 #define NOT_POR PCON_bits.NOT_POR
556 // ----- PIE1 bits --------------------
559 unsigned char TMR1IE:1;
560 unsigned char TMR2IE:1;
561 unsigned char CCP1IE:1;
562 unsigned char SSPIE:1;
563 unsigned char TXIE:1;
564 unsigned char RCIE:1;
565 unsigned char ADIE:1;
569 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
571 #define TMR1IE PIE1_bits.TMR1IE
572 #define TMR2IE PIE1_bits.TMR2IE
573 #define CCP1IE PIE1_bits.CCP1IE
574 #define SSPIE PIE1_bits.SSPIE
575 #define TXIE PIE1_bits.TXIE
576 #define RCIE PIE1_bits.RCIE
577 #define ADIE PIE1_bits.ADIE
579 // ----- PIE2 bits --------------------
582 unsigned char CCP2IE:1;
585 unsigned char BCLIE:1;
589 unsigned char LVDIE:1;
592 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
594 #define CCP2IE PIE2_bits.CCP2IE
595 #define BCLIE PIE2_bits.BCLIE
596 #define LVDIE PIE2_bits.LVDIE
598 // ----- PIR1 bits --------------------
601 unsigned char TMR1IF:1;
602 unsigned char TMR2IF:1;
603 unsigned char CCP1IF:1;
604 unsigned char SSPIF:1;
605 unsigned char TXIF:1;
606 unsigned char RCIF:1;
607 unsigned char ADIF:1;
611 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
613 #define TMR1IF PIR1_bits.TMR1IF
614 #define TMR2IF PIR1_bits.TMR2IF
615 #define CCP1IF PIR1_bits.CCP1IF
616 #define SSPIF PIR1_bits.SSPIF
617 #define TXIF PIR1_bits.TXIF
618 #define RCIF PIR1_bits.RCIF
619 #define ADIF PIR1_bits.ADIF
621 // ----- PIR2 bits --------------------
624 unsigned char CCP2IF:1;
627 unsigned char BCLIF:1;
631 unsigned char LVDIF:1;
634 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
636 #define CCP2IF PIR2_bits.CCP2IF
637 #define BCLIF PIR2_bits.BCLIF
638 #define LVDIF PIR2_bits.LVDIF
640 // ----- RCSTA bits --------------------
643 unsigned char RX9D:1;
644 unsigned char OERR:1;
645 unsigned char FERR:1;
646 unsigned char ADDEN:1;
647 unsigned char CREN:1;
648 unsigned char SREN:1;
650 unsigned char SPEN:1;
653 unsigned char RCD8:1;
669 unsigned char NOT_RC8:1;
679 unsigned char RC8_9:1;
683 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
685 #define RX9D RCSTA_bits.RX9D
686 #define RCD8 RCSTA_bits.RCD8
687 #define OERR RCSTA_bits.OERR
688 #define FERR RCSTA_bits.FERR
689 #define ADDEN RCSTA_bits.ADDEN
690 #define CREN RCSTA_bits.CREN
691 #define SREN RCSTA_bits.SREN
692 #define RX9 RCSTA_bits.RX9
693 #define RC9 RCSTA_bits.RC9
694 #define NOT_RC8 RCSTA_bits.NOT_RC8
695 #define RC8_9 RCSTA_bits.RC8_9
696 #define SPEN RCSTA_bits.SPEN
698 // ----- REFCON bits --------------------
705 unsigned char VRLOEN:1;
706 unsigned char VRHOEN:1;
707 unsigned char VRLEN:1;
708 unsigned char VRHEN:1;
711 extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits;
713 #define VRLOEN REFCON_bits.VRLOEN
714 #define VRHOEN REFCON_bits.VRHOEN
715 #define VRLEN REFCON_bits.VRLEN
716 #define VRHEN REFCON_bits.VRHEN
718 // ----- SSPCON bits --------------------
721 unsigned char SSPM0:1;
722 unsigned char SSPM1:1;
723 unsigned char SSPM2:1;
724 unsigned char SSPM3:1;
726 unsigned char SSPEN:1;
727 unsigned char SSPOV:1;
728 unsigned char WCOL:1;
731 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
733 #define SSPM0 SSPCON_bits.SSPM0
734 #define SSPM1 SSPCON_bits.SSPM1
735 #define SSPM2 SSPCON_bits.SSPM2
736 #define SSPM3 SSPCON_bits.SSPM3
737 #define CKP SSPCON_bits.CKP
738 #define SSPEN SSPCON_bits.SSPEN
739 #define SSPOV SSPCON_bits.SSPOV
740 #define WCOL SSPCON_bits.WCOL
742 // ----- SSPCON2 bits --------------------
746 unsigned char RSEN:1;
748 unsigned char RCEN:1;
749 unsigned char ACKEN:1;
750 unsigned char ACKDT:1;
751 unsigned char ACKSTAT:1;
752 unsigned char GCEN:1;
755 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
757 #define SEN SSPCON2_bits.SEN
758 #define RSEN SSPCON2_bits.RSEN
759 #define PEN SSPCON2_bits.PEN
760 #define RCEN SSPCON2_bits.RCEN
761 #define ACKEN SSPCON2_bits.ACKEN
762 #define ACKDT SSPCON2_bits.ACKDT
763 #define ACKSTAT SSPCON2_bits.ACKSTAT
764 #define GCEN SSPCON2_bits.GCEN
766 // ----- SSPSTAT bits --------------------
781 unsigned char I2C_READ:1;
782 unsigned char I2C_START:1;
783 unsigned char I2C_STOP:1;
784 unsigned char I2C_DATA:1;
791 unsigned char NOT_W:1;
794 unsigned char NOT_A:1;
801 unsigned char NOT_WRITE:1;
804 unsigned char NOT_ADDRESS:1;
821 unsigned char READ_WRITE:1;
824 unsigned char DATA_ADDRESS:1;
829 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
831 #define BF SSPSTAT_bits.BF
832 #define UA SSPSTAT_bits.UA
833 #define R SSPSTAT_bits.R
834 #define I2C_READ SSPSTAT_bits.I2C_READ
835 #define NOT_W SSPSTAT_bits.NOT_W
836 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
837 #define R_W SSPSTAT_bits.R_W
838 #define READ_WRITE SSPSTAT_bits.READ_WRITE
839 #define S SSPSTAT_bits.S
840 #define I2C_START SSPSTAT_bits.I2C_START
841 #define P SSPSTAT_bits.P
842 #define I2C_STOP SSPSTAT_bits.I2C_STOP
843 #define D SSPSTAT_bits.D
844 #define I2C_DATA SSPSTAT_bits.I2C_DATA
845 #define NOT_A SSPSTAT_bits.NOT_A
846 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
847 #define D_A SSPSTAT_bits.D_A
848 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
849 #define CKE SSPSTAT_bits.CKE
850 #define SMP SSPSTAT_bits.SMP
852 // ----- STATUS bits --------------------
858 unsigned char NOT_PD:1;
859 unsigned char NOT_TO:1;
865 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
867 #define C STATUS_bits.C
868 #define DC STATUS_bits.DC
869 #define Z STATUS_bits.Z
870 #define NOT_PD STATUS_bits.NOT_PD
871 #define NOT_TO STATUS_bits.NOT_TO
872 #define RP0 STATUS_bits.RP0
873 #define RP1 STATUS_bits.RP1
874 #define IRP STATUS_bits.IRP
876 // ----- T1CON bits --------------------
879 unsigned char TMR1ON:1;
880 unsigned char TMR1CS:1;
881 unsigned char NOT_T1SYNC:1;
882 unsigned char T1OSCEN:1;
883 unsigned char T1CKPS0:1;
884 unsigned char T1CKPS1:1;
891 unsigned char T1INSYNC:1;
901 unsigned char T1SYNC:1;
909 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
911 #define TMR1ON T1CON_bits.TMR1ON
912 #define TMR1CS T1CON_bits.TMR1CS
913 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
914 #define T1INSYNC T1CON_bits.T1INSYNC
915 #define T1SYNC T1CON_bits.T1SYNC
916 #define T1OSCEN T1CON_bits.T1OSCEN
917 #define T1CKPS0 T1CON_bits.T1CKPS0
918 #define T1CKPS1 T1CON_bits.T1CKPS1
920 // ----- T2CON bits --------------------
923 unsigned char T2CKPS0:1;
924 unsigned char T2CKPS1:1;
925 unsigned char TMR2ON:1;
926 unsigned char TOUTPS0:1;
927 unsigned char TOUTPS1:1;
928 unsigned char TOUTPS2:1;
929 unsigned char TOUTPS3:1;
933 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
935 #define T2CKPS0 T2CON_bits.T2CKPS0
936 #define T2CKPS1 T2CON_bits.T2CKPS1
937 #define TMR2ON T2CON_bits.TMR2ON
938 #define TOUTPS0 T2CON_bits.TOUTPS0
939 #define TOUTPS1 T2CON_bits.TOUTPS1
940 #define TOUTPS2 T2CON_bits.TOUTPS2
941 #define TOUTPS3 T2CON_bits.TOUTPS3
943 // ----- TRISE bits --------------------
946 unsigned char TRISE0:1;
947 unsigned char TRISE1:1;
948 unsigned char TRISE2:1;
950 unsigned char PSPMODE:1;
951 unsigned char IBOV:1;
956 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
958 #define TRISE0 TRISE_bits.TRISE0
959 #define TRISE1 TRISE_bits.TRISE1
960 #define TRISE2 TRISE_bits.TRISE2
961 #define PSPMODE TRISE_bits.PSPMODE
962 #define IBOV TRISE_bits.IBOV
963 #define OBF TRISE_bits.OBF
964 #define IBF TRISE_bits.IBF
966 // ----- TXSTA bits --------------------
969 unsigned char TX9D:1;
970 unsigned char TRMT:1;
971 unsigned char BRGH:1;
973 unsigned char SYNC:1;
974 unsigned char TXEN:1;
976 unsigned char CSRC:1;
979 unsigned char TXD8:1;
985 unsigned char NOT_TX8:1;
995 unsigned char TX8_9:1;
999 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
1001 #define TX9D TXSTA_bits.TX9D
1002 #define TXD8 TXSTA_bits.TXD8
1003 #define TRMT TXSTA_bits.TRMT
1004 #define BRGH TXSTA_bits.BRGH
1005 #define SYNC TXSTA_bits.SYNC
1006 #define TXEN TXSTA_bits.TXEN
1007 #define TX9 TXSTA_bits.TX9
1008 #define NOT_TX8 TXSTA_bits.NOT_TX8
1009 #define TX8_9 TXSTA_bits.TX8_9
1010 #define CSRC TXSTA_bits.CSRC