2 // Register Declarations for Microchip 16C774 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define SSPCON2_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define SSPADD_ADDR 0x0093
72 #define SSPSTAT_ADDR 0x0094
73 #define TXSTA_ADDR 0x0098
74 #define SPBRG_ADDR 0x0099
75 #define REFCON_ADDR 0x009B
76 #define LVDCON_ADDR 0x009C
77 #define ADRESL_ADDR 0x009E
78 #define ADCON1_ADDR 0x009F
81 // Memory organization.
87 // P16C774.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
90 // This header file defines configurations, registers, and other useful bits of
91 // information for the PIC16C774 microcontroller. These names are taken to match
92 // the data sheets as closely as possible.
94 // Note that the processor must be selected before this file is
95 // included. The processor may be selected the following ways:
97 // 1. Command line switch:
98 // C:\ MPASM MYFILE.ASM /PIC16C774
99 // 2. LIST directive in the source file
101 // 3. Processor Type entry in the MPASM full-screen interface
103 //==========================================================================
107 //==========================================================================
111 //1.00 08/07/98 Initial Release
112 //1.01 25Jan99 Fixed LVVx bits
114 //==========================================================================
118 //==========================================================================
121 // MESSG "Processor-header file mismatch. Verify selected processor."
124 //==========================================================================
126 // Register Definitions
128 //==========================================================================
133 //----- Register Files------------------------------------------------------
135 extern __data __at (INDF_ADDR) volatile char INDF;
136 extern __sfr __at (TMR0_ADDR) TMR0;
137 extern __data __at (PCL_ADDR) volatile char PCL;
138 extern __sfr __at (STATUS_ADDR) STATUS;
139 extern __sfr __at (FSR_ADDR) FSR;
140 extern __sfr __at (PORTA_ADDR) PORTA;
141 extern __sfr __at (PORTB_ADDR) PORTB;
142 extern __sfr __at (PORTC_ADDR) PORTC;
143 extern __sfr __at (PORTD_ADDR) PORTD;
144 extern __sfr __at (PORTE_ADDR) PORTE;
145 extern __sfr __at (PCLATH_ADDR) PCLATH;
146 extern __sfr __at (INTCON_ADDR) INTCON;
147 extern __sfr __at (PIR1_ADDR) PIR1;
148 extern __sfr __at (PIR2_ADDR) PIR2;
149 extern __sfr __at (TMR1L_ADDR) TMR1L;
150 extern __sfr __at (TMR1H_ADDR) TMR1H;
151 extern __sfr __at (T1CON_ADDR) T1CON;
152 extern __sfr __at (TMR2_ADDR) TMR2;
153 extern __sfr __at (T2CON_ADDR) T2CON;
154 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
155 extern __sfr __at (SSPCON_ADDR) SSPCON;
156 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
157 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
158 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
159 extern __sfr __at (RCSTA_ADDR) RCSTA;
160 extern __sfr __at (TXREG_ADDR) TXREG;
161 extern __sfr __at (RCREG_ADDR) RCREG;
162 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
163 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
164 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
165 extern __sfr __at (ADRESH_ADDR) ADRESH;
166 extern __sfr __at (ADCON0_ADDR) ADCON0;
168 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
169 extern __sfr __at (TRISA_ADDR) TRISA;
170 extern __sfr __at (TRISB_ADDR) TRISB;
171 extern __sfr __at (TRISC_ADDR) TRISC;
172 extern __sfr __at (TRISD_ADDR) TRISD;
173 extern __sfr __at (TRISE_ADDR) TRISE;
174 extern __sfr __at (PIE1_ADDR) PIE1;
175 extern __sfr __at (PIE2_ADDR) PIE2;
176 extern __sfr __at (PCON_ADDR) PCON;
177 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
178 extern __sfr __at (PR2_ADDR) PR2;
179 extern __sfr __at (SSPADD_ADDR) SSPADD;
180 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
181 extern __sfr __at (TXSTA_ADDR) TXSTA;
182 extern __sfr __at (SPBRG_ADDR) SPBRG;
183 extern __sfr __at (REFCON_ADDR) REFCON;
184 extern __sfr __at (LVDCON_ADDR) LVDCON;
185 extern __sfr __at (ADRESL_ADDR) ADRESL;
186 extern __sfr __at (ADCON1_ADDR) ADCON1;
188 //----- STATUS Bits --------------------------------------------------------
191 //----- INTCON Bits --------------------------------------------------------
194 //----- PIR1 Bits ----------------------------------------------------------
197 //----- PIR2 Bits ----------------------------------------------------------
200 //----- T1CON Bits ---------------------------------------------------------
203 //----- T2CON Bits ---------------------------------------------------------
206 //----- SSPCON Bits --------------------------------------------------------
209 //----- CCP1CON Bits -------------------------------------------------------
212 //----- RCSTA Bits ---------------------------------------------------------
215 //----- CCP2CON Bits -------------------------------------------------------
218 //----- ADCON0 Bits --------------------------------------------------------
221 //----- OPTION Bits ----------------------------------------------------
224 //----- TRISE Bits ---------------------------------------------------------
227 //----- PIE1 Bits ----------------------------------------------------------
230 //----- PIE2 Bits ----------------------------------------------------------
233 //----- PCON Bits ----------------------------------------------------------
236 //----- SSPCON2 Bits --------------------------------------------------------
239 //----- SSPSTAT Bits -------------------------------------------------------
242 //----- TXSTA Bits ---------------------------------------------------------
245 //----- REFCON Bits --------------------------------------------------------
248 //----- LVDCON Bits --------------------------------------------------------
251 //----- ADCON1 Bits --------------------------------------------------------
254 //==========================================================================
258 //==========================================================================
261 // __BADRAM H'8F'-H'90', H'95'-H'97', H'9A', H'9D'
262 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F'
263 // __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF'
265 //==========================================================================
267 // Configuration Bits
269 //==========================================================================
271 #define _BODEN_ON 0x3FFF
272 #define _BODEN_OFF 0x3FBF
273 #define _CP_ALL 0x0CCF
274 #define _CP_75 0x1DDF
275 #define _CP_50 0x2EEF
276 #define _CP_OFF 0x3FFF
277 #define _VBOR_25 0x3FFF
278 #define _VBOR_27 0x3BFF
279 #define _VBOR_42 0x37FF
280 #define _VBOR_45 0x33FF
281 #define _PWRTE_OFF 0x3FFF
282 #define _PWRTE_ON 0x3FF7
283 #define _WDT_ON 0x3FFF
284 #define _WDT_OFF 0x3FFB
285 #define _LP_OSC 0x3FFC
286 #define _XT_OSC 0x3FFD
287 #define _HS_OSC 0x3FFE
288 #define _RC_OSC 0x3FFF
292 // ----- ADCON0 bits --------------------
295 unsigned char ADON:1;
296 unsigned char CHS3:1;
298 unsigned char CHS0:1;
299 unsigned char CHS1:1;
300 unsigned char CHS2:1;
301 unsigned char ADCS0:1;
302 unsigned char ADCS1:1;
307 unsigned char NOT_DONE:1;
317 unsigned char GO_DONE:1;
325 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
327 #define ADON ADCON0_bits.ADON
328 #define CHS3 ADCON0_bits.CHS3
329 #define GO ADCON0_bits.GO
330 #define NOT_DONE ADCON0_bits.NOT_DONE
331 #define GO_DONE ADCON0_bits.GO_DONE
332 #define CHS0 ADCON0_bits.CHS0
333 #define CHS1 ADCON0_bits.CHS1
334 #define CHS2 ADCON0_bits.CHS2
335 #define ADCS0 ADCON0_bits.ADCS0
336 #define ADCS1 ADCON0_bits.ADCS1
338 // ----- ADCON1 bits --------------------
341 unsigned char PCFG0:1;
342 unsigned char PCFG1:1;
343 unsigned char PCFG2:1;
344 unsigned char PCFG3:1;
345 unsigned char VCFG0:1;
346 unsigned char VCFG1:1;
347 unsigned char VCFG2:1;
348 unsigned char ADFM:1;
351 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
353 #define PCFG0 ADCON1_bits.PCFG0
354 #define PCFG1 ADCON1_bits.PCFG1
355 #define PCFG2 ADCON1_bits.PCFG2
356 #define PCFG3 ADCON1_bits.PCFG3
357 #define VCFG0 ADCON1_bits.VCFG0
358 #define VCFG1 ADCON1_bits.VCFG1
359 #define VCFG2 ADCON1_bits.VCFG2
360 #define ADFM ADCON1_bits.ADFM
362 // ----- CCP1CON bits --------------------
365 unsigned char CCP1M0:1;
366 unsigned char CCP1M1:1;
367 unsigned char CCP1M2:1;
368 unsigned char CCP1M3:1;
369 unsigned char CCP1Y:1;
370 unsigned char CCP1X:1;
375 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
377 #define CCP1M0 CCP1CON_bits.CCP1M0
378 #define CCP1M1 CCP1CON_bits.CCP1M1
379 #define CCP1M2 CCP1CON_bits.CCP1M2
380 #define CCP1M3 CCP1CON_bits.CCP1M3
381 #define CCP1Y CCP1CON_bits.CCP1Y
382 #define CCP1X CCP1CON_bits.CCP1X
384 // ----- CCP2CON bits --------------------
387 unsigned char CCP2M0:1;
388 unsigned char CCP2M1:1;
389 unsigned char CCP2M2:1;
390 unsigned char CCP2M3:1;
391 unsigned char CCP2Y:1;
392 unsigned char CCP2X:1;
397 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
399 #define CCP2M0 CCP2CON_bits.CCP2M0
400 #define CCP2M1 CCP2CON_bits.CCP2M1
401 #define CCP2M2 CCP2CON_bits.CCP2M2
402 #define CCP2M3 CCP2CON_bits.CCP2M3
403 #define CCP2Y CCP2CON_bits.CCP2Y
404 #define CCP2X CCP2CON_bits.CCP2X
406 // ----- INTCON bits --------------------
409 unsigned char RBIF:1;
410 unsigned char INTF:1;
411 unsigned char T0IF:1;
412 unsigned char RBIE:1;
413 unsigned char INTE:1;
414 unsigned char T0IE:1;
415 unsigned char PEIE:1;
419 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
421 #define RBIF INTCON_bits.RBIF
422 #define INTF INTCON_bits.INTF
423 #define T0IF INTCON_bits.T0IF
424 #define RBIE INTCON_bits.RBIE
425 #define INTE INTCON_bits.INTE
426 #define T0IE INTCON_bits.T0IE
427 #define PEIE INTCON_bits.PEIE
428 #define GIE INTCON_bits.GIE
430 // ----- LVDCON bits --------------------
437 unsigned char LVDEN:1;
438 unsigned char BGST:1;
443 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
445 #define LV0 LVDCON_bits.LV0
446 #define LV1 LVDCON_bits.LV1
447 #define LV2 LVDCON_bits.LV2
448 #define LV3 LVDCON_bits.LV3
449 #define LVDEN LVDCON_bits.LVDEN
450 #define BGST LVDCON_bits.BGST
452 // ----- OPTION_REG bits --------------------
459 unsigned char T0SE:1;
460 unsigned char T0CS:1;
461 unsigned char INTEDG:1;
462 unsigned char NOT_RBPU:1;
464 } __OPTION_REG_bits_t;
465 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
467 #define PS0 OPTION_REG_bits.PS0
468 #define PS1 OPTION_REG_bits.PS1
469 #define PS2 OPTION_REG_bits.PS2
470 #define PSA OPTION_REG_bits.PSA
471 #define T0SE OPTION_REG_bits.T0SE
472 #define T0CS OPTION_REG_bits.T0CS
473 #define INTEDG OPTION_REG_bits.INTEDG
474 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
476 // ----- PCON bits --------------------
479 unsigned char NOT_BO:1;
480 unsigned char NOT_POR:1;
489 unsigned char NOT_BOR:1;
499 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
501 #define NOT_BO PCON_bits.NOT_BO
502 #define NOT_BOR PCON_bits.NOT_BOR
503 #define NOT_POR PCON_bits.NOT_POR
505 // ----- PIE1 bits --------------------
508 unsigned char TMR1IE:1;
509 unsigned char TMR2IE:1;
510 unsigned char CCP1IE:1;
511 unsigned char SSPIE:1;
512 unsigned char TXIE:1;
513 unsigned char RCIE:1;
514 unsigned char ADIE:1;
518 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
520 #define TMR1IE PIE1_bits.TMR1IE
521 #define TMR2IE PIE1_bits.TMR2IE
522 #define CCP1IE PIE1_bits.CCP1IE
523 #define SSPIE PIE1_bits.SSPIE
524 #define TXIE PIE1_bits.TXIE
525 #define RCIE PIE1_bits.RCIE
526 #define ADIE PIE1_bits.ADIE
528 // ----- PIE2 bits --------------------
531 unsigned char CCP2IE:1;
534 unsigned char BCLIE:1;
538 unsigned char LVDIE:1;
541 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
543 #define CCP2IE PIE2_bits.CCP2IE
544 #define BCLIE PIE2_bits.BCLIE
545 #define LVDIE PIE2_bits.LVDIE
547 // ----- PIR1 bits --------------------
550 unsigned char TMR1IF:1;
551 unsigned char TMR2IF:1;
552 unsigned char CCP1IF:1;
553 unsigned char SSPIF:1;
554 unsigned char TXIF:1;
555 unsigned char RCIF:1;
556 unsigned char ADIF:1;
560 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
562 #define TMR1IF PIR1_bits.TMR1IF
563 #define TMR2IF PIR1_bits.TMR2IF
564 #define CCP1IF PIR1_bits.CCP1IF
565 #define SSPIF PIR1_bits.SSPIF
566 #define TXIF PIR1_bits.TXIF
567 #define RCIF PIR1_bits.RCIF
568 #define ADIF PIR1_bits.ADIF
570 // ----- PIR2 bits --------------------
573 unsigned char CCP2IF:1;
576 unsigned char BCLIF:1;
580 unsigned char LVDIF:1;
583 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
585 #define CCP2IF PIR2_bits.CCP2IF
586 #define BCLIF PIR2_bits.BCLIF
587 #define LVDIF PIR2_bits.LVDIF
589 // ----- RCSTA bits --------------------
592 unsigned char RX9D:1;
593 unsigned char OERR:1;
594 unsigned char FERR:1;
595 unsigned char ADDEN:1;
596 unsigned char CREN:1;
597 unsigned char SREN:1;
599 unsigned char SPEN:1;
602 unsigned char RCD8:1;
618 unsigned char NOT_RC8:1;
628 unsigned char RC8_9:1;
632 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
634 #define RX9D RCSTA_bits.RX9D
635 #define RCD8 RCSTA_bits.RCD8
636 #define OERR RCSTA_bits.OERR
637 #define FERR RCSTA_bits.FERR
638 #define ADDEN RCSTA_bits.ADDEN
639 #define CREN RCSTA_bits.CREN
640 #define SREN RCSTA_bits.SREN
641 #define RX9 RCSTA_bits.RX9
642 #define RC9 RCSTA_bits.RC9
643 #define NOT_RC8 RCSTA_bits.NOT_RC8
644 #define RC8_9 RCSTA_bits.RC8_9
645 #define SPEN RCSTA_bits.SPEN
647 // ----- REFCON bits --------------------
654 unsigned char VRLOEN:1;
655 unsigned char VRHOEN:1;
656 unsigned char VRLEN:1;
657 unsigned char VRHEN:1;
660 extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits;
662 #define VRLOEN REFCON_bits.VRLOEN
663 #define VRHOEN REFCON_bits.VRHOEN
664 #define VRLEN REFCON_bits.VRLEN
665 #define VRHEN REFCON_bits.VRHEN
667 // ----- SSPCON bits --------------------
670 unsigned char SSPM0:1;
671 unsigned char SSPM1:1;
672 unsigned char SSPM2:1;
673 unsigned char SSPM3:1;
675 unsigned char SSPEN:1;
676 unsigned char SSPOV:1;
677 unsigned char WCOL:1;
680 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
682 #define SSPM0 SSPCON_bits.SSPM0
683 #define SSPM1 SSPCON_bits.SSPM1
684 #define SSPM2 SSPCON_bits.SSPM2
685 #define SSPM3 SSPCON_bits.SSPM3
686 #define CKP SSPCON_bits.CKP
687 #define SSPEN SSPCON_bits.SSPEN
688 #define SSPOV SSPCON_bits.SSPOV
689 #define WCOL SSPCON_bits.WCOL
691 // ----- SSPCON2 bits --------------------
695 unsigned char RSEN:1;
697 unsigned char RCEN:1;
698 unsigned char ACKEN:1;
699 unsigned char ACKDT:1;
700 unsigned char ACKSTAT:1;
701 unsigned char GCEN:1;
704 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
706 #define SEN SSPCON2_bits.SEN
707 #define RSEN SSPCON2_bits.RSEN
708 #define PEN SSPCON2_bits.PEN
709 #define RCEN SSPCON2_bits.RCEN
710 #define ACKEN SSPCON2_bits.ACKEN
711 #define ACKDT SSPCON2_bits.ACKDT
712 #define ACKSTAT SSPCON2_bits.ACKSTAT
713 #define GCEN SSPCON2_bits.GCEN
715 // ----- SSPSTAT bits --------------------
730 unsigned char I2C_READ:1;
731 unsigned char I2C_START:1;
732 unsigned char I2C_STOP:1;
733 unsigned char I2C_DATA:1;
740 unsigned char NOT_W:1;
743 unsigned char NOT_A:1;
750 unsigned char NOT_WRITE:1;
753 unsigned char NOT_ADDRESS:1;
770 unsigned char READ_WRITE:1;
773 unsigned char DATA_ADDRESS:1;
778 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
780 #define BF SSPSTAT_bits.BF
781 #define UA SSPSTAT_bits.UA
782 #define R SSPSTAT_bits.R
783 #define I2C_READ SSPSTAT_bits.I2C_READ
784 #define NOT_W SSPSTAT_bits.NOT_W
785 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
786 #define R_W SSPSTAT_bits.R_W
787 #define READ_WRITE SSPSTAT_bits.READ_WRITE
788 #define S SSPSTAT_bits.S
789 #define I2C_START SSPSTAT_bits.I2C_START
790 #define P SSPSTAT_bits.P
791 #define I2C_STOP SSPSTAT_bits.I2C_STOP
792 #define D SSPSTAT_bits.D
793 #define I2C_DATA SSPSTAT_bits.I2C_DATA
794 #define NOT_A SSPSTAT_bits.NOT_A
795 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
796 #define D_A SSPSTAT_bits.D_A
797 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
798 #define CKE SSPSTAT_bits.CKE
799 #define SMP SSPSTAT_bits.SMP
801 // ----- STATUS bits --------------------
807 unsigned char NOT_PD:1;
808 unsigned char NOT_TO:1;
814 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
816 #define C STATUS_bits.C
817 #define DC STATUS_bits.DC
818 #define Z STATUS_bits.Z
819 #define NOT_PD STATUS_bits.NOT_PD
820 #define NOT_TO STATUS_bits.NOT_TO
821 #define RP0 STATUS_bits.RP0
822 #define RP1 STATUS_bits.RP1
823 #define IRP STATUS_bits.IRP
825 // ----- T1CON bits --------------------
828 unsigned char TMR1ON:1;
829 unsigned char TMR1CS:1;
830 unsigned char NOT_T1SYNC:1;
831 unsigned char T1OSCEN:1;
832 unsigned char T1CKPS0:1;
833 unsigned char T1CKPS1:1;
840 unsigned char T1INSYNC:1;
850 unsigned char T1SYNC:1;
858 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
860 #define TMR1ON T1CON_bits.TMR1ON
861 #define TMR1CS T1CON_bits.TMR1CS
862 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
863 #define T1INSYNC T1CON_bits.T1INSYNC
864 #define T1SYNC T1CON_bits.T1SYNC
865 #define T1OSCEN T1CON_bits.T1OSCEN
866 #define T1CKPS0 T1CON_bits.T1CKPS0
867 #define T1CKPS1 T1CON_bits.T1CKPS1
869 // ----- T2CON bits --------------------
872 unsigned char T2CKPS0:1;
873 unsigned char T2CKPS1:1;
874 unsigned char TMR2ON:1;
875 unsigned char TOUTPS0:1;
876 unsigned char TOUTPS1:1;
877 unsigned char TOUTPS2:1;
878 unsigned char TOUTPS3:1;
882 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
884 #define T2CKPS0 T2CON_bits.T2CKPS0
885 #define T2CKPS1 T2CON_bits.T2CKPS1
886 #define TMR2ON T2CON_bits.TMR2ON
887 #define TOUTPS0 T2CON_bits.TOUTPS0
888 #define TOUTPS1 T2CON_bits.TOUTPS1
889 #define TOUTPS2 T2CON_bits.TOUTPS2
890 #define TOUTPS3 T2CON_bits.TOUTPS3
892 // ----- TRISE bits --------------------
895 unsigned char TRISE0:1;
896 unsigned char TRISE1:1;
897 unsigned char TRISE2:1;
899 unsigned char PSPMODE:1;
900 unsigned char IBOV:1;
905 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
907 #define TRISE0 TRISE_bits.TRISE0
908 #define TRISE1 TRISE_bits.TRISE1
909 #define TRISE2 TRISE_bits.TRISE2
910 #define PSPMODE TRISE_bits.PSPMODE
911 #define IBOV TRISE_bits.IBOV
912 #define OBF TRISE_bits.OBF
913 #define IBF TRISE_bits.IBF
915 // ----- TXSTA bits --------------------
918 unsigned char TX9D:1;
919 unsigned char TRMT:1;
920 unsigned char BRGH:1;
922 unsigned char SYNC:1;
923 unsigned char TXEN:1;
925 unsigned char CSRC:1;
928 unsigned char TXD8:1;
934 unsigned char NOT_TX8:1;
944 unsigned char TX8_9:1;
948 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
950 #define TX9D TXSTA_bits.TX9D
951 #define TXD8 TXSTA_bits.TXD8
952 #define TRMT TXSTA_bits.TRMT
953 #define BRGH TXSTA_bits.BRGH
954 #define SYNC TXSTA_bits.SYNC
955 #define TXEN TXSTA_bits.TXEN
956 #define TX9 TXSTA_bits.TX9
957 #define NOT_TX8 TXSTA_bits.NOT_TX8
958 #define TX8_9 TXSTA_bits.TX8_9
959 #define CSRC TXSTA_bits.CSRC