2 // Register Declarations for Microchip 16C773 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRESH_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define SSPCON2_ADDR 0x0091
66 #define PR2_ADDR 0x0092
67 #define SSPADD_ADDR 0x0093
68 #define SSPSTAT_ADDR 0x0094
69 #define TXSTA_ADDR 0x0098
70 #define SPBRG_ADDR 0x0099
71 #define REFCON_ADDR 0x009B
72 #define LVDCON_ADDR 0x009C
73 #define ADRESL_ADDR 0x009E
74 #define ADCON1_ADDR 0x009F
77 // Memory organization.
80 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
81 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
82 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
83 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
84 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
85 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
86 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
87 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
88 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
89 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
90 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
91 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
92 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
93 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
94 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
95 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
96 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
97 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
98 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
99 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
100 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
101 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
102 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
103 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
104 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
105 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
106 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
107 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
108 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
109 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
110 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
111 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
112 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
113 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
114 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
115 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
116 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
117 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
118 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
119 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
120 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
121 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
122 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
123 #pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON
124 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
125 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
126 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
130 // P16C773.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
133 // This header file defines configurations, registers, and other useful bits of
134 // information for the PIC16C773 microcontroller. These names are taken to match
135 // the data sheets as closely as possible.
137 // Note that the processor must be selected before this file is
138 // included. The processor may be selected the following ways:
140 // 1. Command line switch:
141 // C:\ MPASM MYFILE.ASM /PIC16C773
142 // 2. LIST directive in the source file
144 // 3. Processor Type entry in the MPASM full-screen interface
146 //==========================================================================
150 //==========================================================================
154 //1.00 08/07/98 Initial Release
155 //1.01 25Jan99 Fixed LVVx bits
157 //==========================================================================
161 //==========================================================================
164 // MESSG "Processor-header file mismatch. Verify selected processor."
167 //==========================================================================
169 // Register Definitions
171 //==========================================================================
176 //----- Register Files------------------------------------------------------
178 extern __data __at (INDF_ADDR) volatile char INDF;
179 extern __sfr __at (TMR0_ADDR) TMR0;
180 extern __data __at (PCL_ADDR) volatile char PCL;
181 extern __sfr __at (STATUS_ADDR) STATUS;
182 extern __sfr __at (FSR_ADDR) FSR;
183 extern __sfr __at (PORTA_ADDR) PORTA;
184 extern __sfr __at (PORTB_ADDR) PORTB;
185 extern __sfr __at (PORTC_ADDR) PORTC;
186 extern __sfr __at (PCLATH_ADDR) PCLATH;
187 extern __sfr __at (INTCON_ADDR) INTCON;
188 extern __sfr __at (PIR1_ADDR) PIR1;
189 extern __sfr __at (PIR2_ADDR) PIR2;
190 extern __sfr __at (TMR1L_ADDR) TMR1L;
191 extern __sfr __at (TMR1H_ADDR) TMR1H;
192 extern __sfr __at (T1CON_ADDR) T1CON;
193 extern __sfr __at (TMR2_ADDR) TMR2;
194 extern __sfr __at (T2CON_ADDR) T2CON;
195 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
196 extern __sfr __at (SSPCON_ADDR) SSPCON;
197 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
198 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
199 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
200 extern __sfr __at (RCSTA_ADDR) RCSTA;
201 extern __sfr __at (TXREG_ADDR) TXREG;
202 extern __sfr __at (RCREG_ADDR) RCREG;
203 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
204 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
205 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
206 extern __sfr __at (ADRESH_ADDR) ADRESH;
207 extern __sfr __at (ADCON0_ADDR) ADCON0;
209 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
210 extern __sfr __at (TRISA_ADDR) TRISA;
211 extern __sfr __at (TRISB_ADDR) TRISB;
212 extern __sfr __at (TRISC_ADDR) TRISC;
213 extern __sfr __at (PIE1_ADDR) PIE1;
214 extern __sfr __at (PIE2_ADDR) PIE2;
215 extern __sfr __at (PCON_ADDR) PCON;
216 extern __sfr __at (SSPCON2_ADDR) SSPCON2;
217 extern __sfr __at (PR2_ADDR) PR2;
218 extern __sfr __at (SSPADD_ADDR) SSPADD;
219 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
220 extern __sfr __at (TXSTA_ADDR) TXSTA;
221 extern __sfr __at (SPBRG_ADDR) SPBRG;
222 extern __sfr __at (REFCON_ADDR) REFCON;
223 extern __sfr __at (LVDCON_ADDR) LVDCON;
224 extern __sfr __at (ADRESL_ADDR) ADRESL;
225 extern __sfr __at (ADCON1_ADDR) ADCON1;
227 //----- STATUS Bits --------------------------------------------------------
230 //----- INTCON Bits --------------------------------------------------------
233 //----- PIR1 Bits ----------------------------------------------------------
236 //----- PIR2 Bits ----------------------------------------------------------
239 //----- T1CON Bits ---------------------------------------------------------
242 //----- T2CON Bits ---------------------------------------------------------
245 //----- SSPCON Bits --------------------------------------------------------
248 //----- CCP1CON Bits -------------------------------------------------------
251 //----- RCSTA Bits ---------------------------------------------------------
254 //----- CCP2CON Bits -------------------------------------------------------
257 //----- ADCON0 Bits --------------------------------------------------------
260 //----- OPTION Bits ----------------------------------------------------
263 //----- PIE1 Bits ----------------------------------------------------------
266 //----- PIE2 Bits ----------------------------------------------------------
269 //----- PCON Bits ----------------------------------------------------------
272 //----- SSPCON2 Bits --------------------------------------------------------
275 //----- SSPSTAT Bits -------------------------------------------------------
278 //----- TXSTA Bits ---------------------------------------------------------
281 //----- REFCON Bits --------------------------------------------------------
284 //----- LVDCON Bits --------------------------------------------------------
287 //----- ADCON1 Bits --------------------------------------------------------
290 //==========================================================================
294 //==========================================================================
297 // __BADRAM H'08'-H'09'
298 // __BADRAM H'88'-H'89', H'8F'-H'90', H'95'-H'97', H'9A', H'9D'
299 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F'
300 // __BADRAM H'185', H'187'-H'189', H'18C'-H'1EF'
302 //==========================================================================
304 // Configuration Bits
306 //==========================================================================
308 #define _BODEN_ON 0x3FFF
309 #define _BODEN_OFF 0x3FBF
310 #define _CP_ALL 0x0CCF
311 #define _CP_75 0x1DDF
312 #define _CP_50 0x2EEF
313 #define _CP_OFF 0x3FFF
314 #define _VBOR_25 0x3FFF
315 #define _VBOR_27 0x3BFF
316 #define _VBOR_42 0x37FF
317 #define _VBOR_45 0x33FF
318 #define _PWRTE_OFF 0x3FFF
319 #define _PWRTE_ON 0x3FF7
320 #define _WDT_ON 0x3FFF
321 #define _WDT_OFF 0x3FFB
322 #define _LP_OSC 0x3FFC
323 #define _XT_OSC 0x3FFD
324 #define _HS_OSC 0x3FFE
325 #define _RC_OSC 0x3FFF
329 // ----- ADCON0 bits --------------------
332 unsigned char ADON:1;
333 unsigned char CHS3:1;
335 unsigned char CHS0:1;
336 unsigned char CHS1:1;
337 unsigned char CHS2:1;
338 unsigned char ADCS0:1;
339 unsigned char ADCS1:1;
344 unsigned char NOT_DONE:1;
354 unsigned char GO_DONE:1;
362 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
364 #define ADON ADCON0_bits.ADON
365 #define CHS3 ADCON0_bits.CHS3
366 #define GO ADCON0_bits.GO
367 #define NOT_DONE ADCON0_bits.NOT_DONE
368 #define GO_DONE ADCON0_bits.GO_DONE
369 #define CHS0 ADCON0_bits.CHS0
370 #define CHS1 ADCON0_bits.CHS1
371 #define CHS2 ADCON0_bits.CHS2
372 #define ADCS0 ADCON0_bits.ADCS0
373 #define ADCS1 ADCON0_bits.ADCS1
375 // ----- ADCON1 bits --------------------
378 unsigned char PCFG0:1;
379 unsigned char PCFG1:1;
380 unsigned char PCFG2:1;
381 unsigned char PCFG3:1;
382 unsigned char VCFG0:1;
383 unsigned char VCFG1:1;
384 unsigned char VCFG2:1;
385 unsigned char ADFM:1;
388 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
390 #define PCFG0 ADCON1_bits.PCFG0
391 #define PCFG1 ADCON1_bits.PCFG1
392 #define PCFG2 ADCON1_bits.PCFG2
393 #define PCFG3 ADCON1_bits.PCFG3
394 #define VCFG0 ADCON1_bits.VCFG0
395 #define VCFG1 ADCON1_bits.VCFG1
396 #define VCFG2 ADCON1_bits.VCFG2
397 #define ADFM ADCON1_bits.ADFM
399 // ----- CCP1CON bits --------------------
402 unsigned char CCP1M0:1;
403 unsigned char CCP1M1:1;
404 unsigned char CCP1M2:1;
405 unsigned char CCP1M3:1;
406 unsigned char CCP1Y:1;
407 unsigned char CCP1X:1;
412 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
414 #define CCP1M0 CCP1CON_bits.CCP1M0
415 #define CCP1M1 CCP1CON_bits.CCP1M1
416 #define CCP1M2 CCP1CON_bits.CCP1M2
417 #define CCP1M3 CCP1CON_bits.CCP1M3
418 #define CCP1Y CCP1CON_bits.CCP1Y
419 #define CCP1X CCP1CON_bits.CCP1X
421 // ----- CCP2CON bits --------------------
424 unsigned char CCP2M0:1;
425 unsigned char CCP2M1:1;
426 unsigned char CCP2M2:1;
427 unsigned char CCP2M3:1;
428 unsigned char CCP2Y:1;
429 unsigned char CCP2X:1;
434 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
436 #define CCP2M0 CCP2CON_bits.CCP2M0
437 #define CCP2M1 CCP2CON_bits.CCP2M1
438 #define CCP2M2 CCP2CON_bits.CCP2M2
439 #define CCP2M3 CCP2CON_bits.CCP2M3
440 #define CCP2Y CCP2CON_bits.CCP2Y
441 #define CCP2X CCP2CON_bits.CCP2X
443 // ----- INTCON bits --------------------
446 unsigned char RBIF:1;
447 unsigned char INTF:1;
448 unsigned char T0IF:1;
449 unsigned char RBIE:1;
450 unsigned char INTE:1;
451 unsigned char T0IE:1;
452 unsigned char PEIE:1;
456 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
458 #define RBIF INTCON_bits.RBIF
459 #define INTF INTCON_bits.INTF
460 #define T0IF INTCON_bits.T0IF
461 #define RBIE INTCON_bits.RBIE
462 #define INTE INTCON_bits.INTE
463 #define T0IE INTCON_bits.T0IE
464 #define PEIE INTCON_bits.PEIE
465 #define GIE INTCON_bits.GIE
467 // ----- LVDCON bits --------------------
474 unsigned char LVDEN:1;
475 unsigned char BGST:1;
480 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
482 #define LV0 LVDCON_bits.LV0
483 #define LV1 LVDCON_bits.LV1
484 #define LV2 LVDCON_bits.LV2
485 #define LV3 LVDCON_bits.LV3
486 #define LVDEN LVDCON_bits.LVDEN
487 #define BGST LVDCON_bits.BGST
489 // ----- OPTION_REG bits --------------------
496 unsigned char T0SE:1;
497 unsigned char T0CS:1;
498 unsigned char INTEDG:1;
499 unsigned char NOT_RBPU:1;
501 } __OPTION_REG_bits_t;
502 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
504 #define PS0 OPTION_REG_bits.PS0
505 #define PS1 OPTION_REG_bits.PS1
506 #define PS2 OPTION_REG_bits.PS2
507 #define PSA OPTION_REG_bits.PSA
508 #define T0SE OPTION_REG_bits.T0SE
509 #define T0CS OPTION_REG_bits.T0CS
510 #define INTEDG OPTION_REG_bits.INTEDG
511 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
513 // ----- PCON bits --------------------
516 unsigned char NOT_BO:1;
517 unsigned char NOT_POR:1;
526 unsigned char NOT_BOR:1;
536 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
538 #define NOT_BO PCON_bits.NOT_BO
539 #define NOT_BOR PCON_bits.NOT_BOR
540 #define NOT_POR PCON_bits.NOT_POR
542 // ----- PIE1 bits --------------------
545 unsigned char TMR1IE:1;
546 unsigned char TMR2IE:1;
547 unsigned char CCP1IE:1;
548 unsigned char SSPIE:1;
549 unsigned char TXIE:1;
550 unsigned char RCIE:1;
551 unsigned char ADIE:1;
555 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
557 #define TMR1IE PIE1_bits.TMR1IE
558 #define TMR2IE PIE1_bits.TMR2IE
559 #define CCP1IE PIE1_bits.CCP1IE
560 #define SSPIE PIE1_bits.SSPIE
561 #define TXIE PIE1_bits.TXIE
562 #define RCIE PIE1_bits.RCIE
563 #define ADIE PIE1_bits.ADIE
565 // ----- PIE2 bits --------------------
568 unsigned char CCP2IE:1;
571 unsigned char BCLIE:1;
575 unsigned char LVDIE:1;
578 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
580 #define CCP2IE PIE2_bits.CCP2IE
581 #define BCLIE PIE2_bits.BCLIE
582 #define LVDIE PIE2_bits.LVDIE
584 // ----- PIR1 bits --------------------
587 unsigned char TMR1IF:1;
588 unsigned char TMR2IF:1;
589 unsigned char CCP1IF:1;
590 unsigned char SSPIF:1;
591 unsigned char TXIF:1;
592 unsigned char RCIF:1;
593 unsigned char ADIF:1;
597 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
599 #define TMR1IF PIR1_bits.TMR1IF
600 #define TMR2IF PIR1_bits.TMR2IF
601 #define CCP1IF PIR1_bits.CCP1IF
602 #define SSPIF PIR1_bits.SSPIF
603 #define TXIF PIR1_bits.TXIF
604 #define RCIF PIR1_bits.RCIF
605 #define ADIF PIR1_bits.ADIF
607 // ----- PIR2 bits --------------------
610 unsigned char CCP2IF:1;
613 unsigned char BCLIF:1;
617 unsigned char LVDIF:1;
620 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
622 #define CCP2IF PIR2_bits.CCP2IF
623 #define BCLIF PIR2_bits.BCLIF
624 #define LVDIF PIR2_bits.LVDIF
626 // ----- RCSTA bits --------------------
629 unsigned char RX9D:1;
630 unsigned char OERR:1;
631 unsigned char FERR:1;
632 unsigned char ADDEN:1;
633 unsigned char CREN:1;
634 unsigned char SREN:1;
636 unsigned char SPEN:1;
639 unsigned char RCD8:1;
655 unsigned char NOT_RC8:1;
665 unsigned char RC8_9:1;
669 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
671 #define RX9D RCSTA_bits.RX9D
672 #define RCD8 RCSTA_bits.RCD8
673 #define OERR RCSTA_bits.OERR
674 #define FERR RCSTA_bits.FERR
675 #define ADDEN RCSTA_bits.ADDEN
676 #define CREN RCSTA_bits.CREN
677 #define SREN RCSTA_bits.SREN
678 #define RX9 RCSTA_bits.RX9
679 #define RC9 RCSTA_bits.RC9
680 #define NOT_RC8 RCSTA_bits.NOT_RC8
681 #define RC8_9 RCSTA_bits.RC8_9
682 #define SPEN RCSTA_bits.SPEN
684 // ----- REFCON bits --------------------
691 unsigned char VRLOEN:1;
692 unsigned char VRHOEN:1;
693 unsigned char VRLEN:1;
694 unsigned char VRHEN:1;
697 extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits;
699 #define VRLOEN REFCON_bits.VRLOEN
700 #define VRHOEN REFCON_bits.VRHOEN
701 #define VRLEN REFCON_bits.VRLEN
702 #define VRHEN REFCON_bits.VRHEN
704 // ----- SSPCON bits --------------------
707 unsigned char SSPM0:1;
708 unsigned char SSPM1:1;
709 unsigned char SSPM2:1;
710 unsigned char SSPM3:1;
712 unsigned char SSPEN:1;
713 unsigned char SSPOV:1;
714 unsigned char WCOL:1;
717 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
719 #define SSPM0 SSPCON_bits.SSPM0
720 #define SSPM1 SSPCON_bits.SSPM1
721 #define SSPM2 SSPCON_bits.SSPM2
722 #define SSPM3 SSPCON_bits.SSPM3
723 #define CKP SSPCON_bits.CKP
724 #define SSPEN SSPCON_bits.SSPEN
725 #define SSPOV SSPCON_bits.SSPOV
726 #define WCOL SSPCON_bits.WCOL
728 // ----- SSPCON2 bits --------------------
732 unsigned char RSEN:1;
734 unsigned char RCEN:1;
735 unsigned char ACKEN:1;
736 unsigned char ACKDT:1;
737 unsigned char ACKSTAT:1;
738 unsigned char GCEN:1;
741 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
743 #define SEN SSPCON2_bits.SEN
744 #define RSEN SSPCON2_bits.RSEN
745 #define PEN SSPCON2_bits.PEN
746 #define RCEN SSPCON2_bits.RCEN
747 #define ACKEN SSPCON2_bits.ACKEN
748 #define ACKDT SSPCON2_bits.ACKDT
749 #define ACKSTAT SSPCON2_bits.ACKSTAT
750 #define GCEN SSPCON2_bits.GCEN
752 // ----- SSPSTAT bits --------------------
767 unsigned char I2C_READ:1;
768 unsigned char I2C_START:1;
769 unsigned char I2C_STOP:1;
770 unsigned char I2C_DATA:1;
777 unsigned char NOT_W:1;
780 unsigned char NOT_A:1;
787 unsigned char NOT_WRITE:1;
790 unsigned char NOT_ADDRESS:1;
807 unsigned char READ_WRITE:1;
810 unsigned char DATA_ADDRESS:1;
815 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
817 #define BF SSPSTAT_bits.BF
818 #define UA SSPSTAT_bits.UA
819 #define R SSPSTAT_bits.R
820 #define I2C_READ SSPSTAT_bits.I2C_READ
821 #define NOT_W SSPSTAT_bits.NOT_W
822 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
823 #define R_W SSPSTAT_bits.R_W
824 #define READ_WRITE SSPSTAT_bits.READ_WRITE
825 #define S SSPSTAT_bits.S
826 #define I2C_START SSPSTAT_bits.I2C_START
827 #define P SSPSTAT_bits.P
828 #define I2C_STOP SSPSTAT_bits.I2C_STOP
829 #define D SSPSTAT_bits.D
830 #define I2C_DATA SSPSTAT_bits.I2C_DATA
831 #define NOT_A SSPSTAT_bits.NOT_A
832 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
833 #define D_A SSPSTAT_bits.D_A
834 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
835 #define CKE SSPSTAT_bits.CKE
836 #define SMP SSPSTAT_bits.SMP
838 // ----- STATUS bits --------------------
844 unsigned char NOT_PD:1;
845 unsigned char NOT_TO:1;
851 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
853 #define C STATUS_bits.C
854 #define DC STATUS_bits.DC
855 #define Z STATUS_bits.Z
856 #define NOT_PD STATUS_bits.NOT_PD
857 #define NOT_TO STATUS_bits.NOT_TO
858 #define RP0 STATUS_bits.RP0
859 #define RP1 STATUS_bits.RP1
860 #define IRP STATUS_bits.IRP
862 // ----- T1CON bits --------------------
865 unsigned char TMR1ON:1;
866 unsigned char TMR1CS:1;
867 unsigned char NOT_T1SYNC:1;
868 unsigned char T1OSCEN:1;
869 unsigned char T1CKPS0:1;
870 unsigned char T1CKPS1:1;
877 unsigned char T1INSYNC:1;
887 unsigned char T1SYNC:1;
895 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
897 #define TMR1ON T1CON_bits.TMR1ON
898 #define TMR1CS T1CON_bits.TMR1CS
899 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
900 #define T1INSYNC T1CON_bits.T1INSYNC
901 #define T1SYNC T1CON_bits.T1SYNC
902 #define T1OSCEN T1CON_bits.T1OSCEN
903 #define T1CKPS0 T1CON_bits.T1CKPS0
904 #define T1CKPS1 T1CON_bits.T1CKPS1
906 // ----- T2CON bits --------------------
909 unsigned char T2CKPS0:1;
910 unsigned char T2CKPS1:1;
911 unsigned char TMR2ON:1;
912 unsigned char TOUTPS0:1;
913 unsigned char TOUTPS1:1;
914 unsigned char TOUTPS2:1;
915 unsigned char TOUTPS3:1;
919 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
921 #define T2CKPS0 T2CON_bits.T2CKPS0
922 #define T2CKPS1 T2CON_bits.T2CKPS1
923 #define TMR2ON T2CON_bits.TMR2ON
924 #define TOUTPS0 T2CON_bits.TOUTPS0
925 #define TOUTPS1 T2CON_bits.TOUTPS1
926 #define TOUTPS2 T2CON_bits.TOUTPS2
927 #define TOUTPS3 T2CON_bits.TOUTPS3
929 // ----- TXSTA bits --------------------
932 unsigned char TX9D:1;
933 unsigned char TRMT:1;
934 unsigned char BRGH:1;
936 unsigned char SYNC:1;
937 unsigned char TXEN:1;
939 unsigned char CSRC:1;
942 unsigned char TXD8:1;
948 unsigned char NOT_TX8:1;
958 unsigned char TX8_9:1;
962 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
964 #define TX9D TXSTA_bits.TX9D
965 #define TXD8 TXSTA_bits.TXD8
966 #define TRMT TXSTA_bits.TRMT
967 #define BRGH TXSTA_bits.BRGH
968 #define SYNC TXSTA_bits.SYNC
969 #define TXEN TXSTA_bits.TXEN
970 #define TX9 TXSTA_bits.TX9
971 #define NOT_TX8 TXSTA_bits.NOT_TX8
972 #define TX8_9 TXSTA_bits.TX8_9
973 #define CSRC TXSTA_bits.CSRC