2 // Register Declarations for Microchip 16C771 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define PIR2_ADDR 0x000D
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define ADRESH_ADDR 0x001E
50 #define ADCON0_ADDR 0x001F
51 #define OPTION_REG_ADDR 0x0081
52 #define TRISA_ADDR 0x0085
53 #define TRISB_ADDR 0x0086
54 #define PIE1_ADDR 0x008C
55 #define PIE2_ADDR 0x008D
56 #define PCON_ADDR 0x008E
57 #define SSPCON2_ADDR 0x0091
58 #define PR2_ADDR 0x0092
59 #define SSPADD_ADDR 0x0093
60 #define SSPSTAT_ADDR 0x0094
61 #define WPUB_ADDR 0x0095
62 #define IOCB_ADDR 0x0096
63 #define P1DEL_ADDR 0x0097
64 #define REFCON_ADDR 0x009B
65 #define LVDCON_ADDR 0x009C
66 #define ANSEL_ADDR 0x009D
67 #define ADRESL_ADDR 0x009E
68 #define ADCON1_ADDR 0x009F
69 #define PMDATL_ADDR 0x010C
70 #define PMADRL_ADDR 0x010D
71 #define PMDATH_ADDR 0x010E
72 #define PMADRH_ADDR 0x010F
73 #define PMCON1_ADDR 0x018C
76 // Memory organization.
79 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
80 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
81 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
82 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
83 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
84 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
85 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
86 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
87 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
88 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
89 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
90 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
91 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
92 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
93 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
94 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
95 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
96 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
97 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
98 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
99 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
100 #pragma memmap ADRESH_ADDR ADRESH_ADDR SFR 0x000 // ADRESH
101 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
102 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
103 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
104 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
105 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
106 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
107 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
108 #pragma memmap SSPCON2_ADDR SSPCON2_ADDR SFR 0x000 // SSPCON2
109 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
110 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
111 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
112 #pragma memmap WPUB_ADDR WPUB_ADDR SFR 0x000 // WPUB
113 #pragma memmap IOCB_ADDR IOCB_ADDR SFR 0x000 // IOCB
114 #pragma memmap P1DEL_ADDR P1DEL_ADDR SFR 0x000 // P1DEL
115 #pragma memmap REFCON_ADDR REFCON_ADDR SFR 0x000 // REFCON
116 #pragma memmap LVDCON_ADDR LVDCON_ADDR SFR 0x000 // LVDCON
117 #pragma memmap ANSEL_ADDR ANSEL_ADDR SFR 0x000 // ANSEL
118 #pragma memmap ADRESL_ADDR ADRESL_ADDR SFR 0x000 // ADRESL
119 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
120 #pragma memmap PMDATL_ADDR PMDATL_ADDR SFR 0x000 // PMDATL
121 #pragma memmap PMADRL_ADDR PMADRL_ADDR SFR 0x000 // PMADRL
122 #pragma memmap PMDATH_ADDR PMDATH_ADDR SFR 0x000 // PMDATH
123 #pragma memmap PMADRH_ADDR PMADRH_ADDR SFR 0x000 // PMADRH
124 #pragma memmap PMCON1_ADDR PMCON1_ADDR SFR 0x000 // PMCON1
128 // P16C771.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
131 // This header file defines configurations, registers, and other useful bits of
132 // information for the PIC16C771 microcontroller. These names are taken to match
133 // the data sheets as closely as possible.
135 // Note that the processor must be selected before this file is
136 // included. The processor may be selected the following ways:
138 // 1. Command line switch:
139 // C:\ MPASM MYFILE.ASM /PIC16C771
140 // 2. LIST directive in the source file
142 // 3. Processor Type entry in the MPASM full-screen interface
144 //==========================================================================
148 //==========================================================================
152 //1.00 14Sep1999 Initial Release
154 //==========================================================================
158 //==========================================================================
161 // MESSG "Processor-header file mismatch. Verify selected processor."
164 //==========================================================================
166 // Register Definitions
168 //==========================================================================
173 //----- Register Files------------------------------------------------------
175 extern data __at (INDF_ADDR) volatile char INDF;
176 extern sfr __at (TMR0_ADDR) TMR0;
177 extern data __at (PCL_ADDR) volatile char PCL;
178 extern sfr __at (STATUS_ADDR) STATUS;
179 extern sfr __at (FSR_ADDR) FSR;
180 extern sfr __at (PORTA_ADDR) PORTA;
181 extern sfr __at (PORTB_ADDR) PORTB;
182 extern sfr __at (PCLATH_ADDR) PCLATH;
183 extern sfr __at (INTCON_ADDR) INTCON;
184 extern sfr __at (PIR1_ADDR) PIR1;
185 extern sfr __at (PIR2_ADDR) PIR2;
186 extern sfr __at (TMR1L_ADDR) TMR1L;
187 extern sfr __at (TMR1H_ADDR) TMR1H;
188 extern sfr __at (T1CON_ADDR) T1CON;
189 extern sfr __at (TMR2_ADDR) TMR2;
190 extern sfr __at (T2CON_ADDR) T2CON;
191 extern sfr __at (SSPBUF_ADDR) SSPBUF;
192 extern sfr __at (SSPCON_ADDR) SSPCON;
193 extern sfr __at (CCPR1L_ADDR) CCPR1L;
194 extern sfr __at (CCPR1H_ADDR) CCPR1H;
195 extern sfr __at (CCP1CON_ADDR) CCP1CON;
196 extern sfr __at (ADRESH_ADDR) ADRESH;
197 extern sfr __at (ADCON0_ADDR) ADCON0;
199 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
200 extern sfr __at (TRISA_ADDR) TRISA;
201 extern sfr __at (TRISB_ADDR) TRISB;
202 extern sfr __at (PIE1_ADDR) PIE1;
203 extern sfr __at (PIE2_ADDR) PIE2;
204 extern sfr __at (PCON_ADDR) PCON;
205 extern sfr __at (SSPCON2_ADDR) SSPCON2;
206 extern sfr __at (PR2_ADDR) PR2;
207 extern sfr __at (SSPADD_ADDR) SSPADD;
208 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
209 extern sfr __at (WPUB_ADDR) WPUB;
210 extern sfr __at (IOCB_ADDR) IOCB;
211 extern sfr __at (P1DEL_ADDR) P1DEL;
212 extern sfr __at (REFCON_ADDR) REFCON;
213 extern sfr __at (LVDCON_ADDR) LVDCON;
214 extern sfr __at (ANSEL_ADDR) ANSEL;
215 extern sfr __at (ADRESL_ADDR) ADRESL;
216 extern sfr __at (ADCON1_ADDR) ADCON1;
218 extern sfr __at (PMDATL_ADDR) PMDATL;
219 extern sfr __at (PMADRL_ADDR) PMADRL;
220 extern sfr __at (PMDATH_ADDR) PMDATH;
221 extern sfr __at (PMADRH_ADDR) PMADRH;
223 extern sfr __at (PMCON1_ADDR) PMCON1;
224 //----- STATUS Bits --------------------------------------------------------
227 //----- INTCON Bits --------------------------------------------------------
230 //----- PIR1 Bits ----------------------------------------------------------
233 //----- PIR2 Bits ----------------------------------------------------------
236 //----- T1CON Bits ---------------------------------------------------------
239 //----- T2CON Bits ---------------------------------------------------------
242 //----- SSPCON Bits --------------------------------------------------------
245 //----- CCP1CON Bits -------------------------------------------------------
248 //----- ADCON0 Bits --------------------------------------------------------
251 //----- OPTION Bits ----------------------------------------------------
255 //----- PIE1 Bits ----------------------------------------------------------
258 //----- PIE2 Bits ----------------------------------------------------------
261 //----- PCON Bits ----------------------------------------------------------
264 //----- SSPCON2 Bits --------------------------------------------------------
267 //----- SSPSTAT Bits -------------------------------------------------------
270 //----- REFCON Bits --------------------------------------------------------
273 //----- LVDCON Bits --------------------------------------------------------
276 //----- ADCON1 Bits --------------------------------------------------------
279 //----- PMCON1 Bits --------------------------------------------------------
283 //==========================================================================
287 //==========================================================================
290 // __BADRAM H'07'-H'09', H'18'-H'1D'
291 // __BADRAM H'87'-H'89'
292 // __BADRAM H'8F'-H'90', H'98'-H'9A'
293 // __BADRAM H'105', H'107'-H'109', H'110'-H'11F'
294 // __BADRAM H'185', H'187'-H'189', H'18D'-H'1EF'
296 //==========================================================================
298 // Configuration Bits
300 //==========================================================================
302 #define _BODEN_ON 0x3FFF
303 #define _BODEN_OFF 0x3FBF
304 #define _CP_ALL 0x0CFF
305 #define _CP_OFF 0x3FFF
306 #define _VBOR_25 0x3FFF
307 #define _VBOR_27 0x3BFF
308 #define _VBOR_42 0x37FF
309 #define _VBOR_45 0x33FF
310 #define _PWRTE_OFF 0x3FFF
311 #define _PWRTE_ON 0x3FEF
312 #define _MCLRE_OFF 0x3FDF
313 #define _MCLRE_ON 0x3FFF
314 #define _WDT_ON 0x3FFF
315 #define _WDT_OFF 0x3FF7
316 #define _ER_OSC_CLKOUT 0x3FFF
317 #define _ER_OSC_NOCLKOUT 0x3FFE
318 #define _INTRC_OSC_CLKOUT 0x3FFD
319 #define _INTRC_OSC_NOCLKOUT 0x3FFC
320 #define _EXTCLK_OSC 0x3FFB
321 #define _HS_OSC 0x3FFA
322 #define _XT_OSC 0x3FF9
323 #define _LP_OSC 0x3FF8
327 // ----- ADCON0 bits --------------------
330 unsigned char ADON:1;
331 unsigned char CHS3:1;
333 unsigned char CHS0:1;
334 unsigned char CHS1:1;
335 unsigned char CHS2:1;
336 unsigned char ADCS0:1;
337 unsigned char ADCS1:1;
342 unsigned char NOT_DONE:1;
352 unsigned char GO_DONE:1;
360 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
362 #define ADON ADCON0_bits.ADON
363 #define CHS3 ADCON0_bits.CHS3
364 #define GO ADCON0_bits.GO
365 #define NOT_DONE ADCON0_bits.NOT_DONE
366 #define GO_DONE ADCON0_bits.GO_DONE
367 #define CHS0 ADCON0_bits.CHS0
368 #define CHS1 ADCON0_bits.CHS1
369 #define CHS2 ADCON0_bits.CHS2
370 #define ADCS0 ADCON0_bits.ADCS0
371 #define ADCS1 ADCON0_bits.ADCS1
373 // ----- ADCON1 bits --------------------
380 unsigned char VCFG0:1;
381 unsigned char VCFG1:1;
382 unsigned char VCFG2:1;
383 unsigned char ADFM:1;
386 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
388 #define VCFG0 ADCON1_bits.VCFG0
389 #define VCFG1 ADCON1_bits.VCFG1
390 #define VCFG2 ADCON1_bits.VCFG2
391 #define ADFM ADCON1_bits.ADFM
393 // ----- CCP1CON bits --------------------
396 unsigned char CCP1M0:1;
397 unsigned char CCP1M1:1;
398 unsigned char CCP1M2:1;
399 unsigned char CCP1M3:1;
400 unsigned char DC1B0:1;
401 unsigned char DC1B1:1;
402 unsigned char PWM1M0:1;
403 unsigned char PWM1M1:1;
406 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
408 #define CCP1M0 CCP1CON_bits.CCP1M0
409 #define CCP1M1 CCP1CON_bits.CCP1M1
410 #define CCP1M2 CCP1CON_bits.CCP1M2
411 #define CCP1M3 CCP1CON_bits.CCP1M3
412 #define DC1B0 CCP1CON_bits.DC1B0
413 #define DC1B1 CCP1CON_bits.DC1B1
414 #define PWM1M0 CCP1CON_bits.PWM1M0
415 #define PWM1M1 CCP1CON_bits.PWM1M1
417 // ----- INTCON bits --------------------
420 unsigned char RBIF:1;
421 unsigned char INTF:1;
422 unsigned char T0IF:1;
423 unsigned char RBIE:1;
424 unsigned char INTE:1;
425 unsigned char T0IE:1;
426 unsigned char PEIE:1;
430 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
432 #define RBIF INTCON_bits.RBIF
433 #define INTF INTCON_bits.INTF
434 #define T0IF INTCON_bits.T0IF
435 #define RBIE INTCON_bits.RBIE
436 #define INTE INTCON_bits.INTE
437 #define T0IE INTCON_bits.T0IE
438 #define PEIE INTCON_bits.PEIE
439 #define GIE INTCON_bits.GIE
441 // ----- LVDCON bits --------------------
448 unsigned char LVDEN:1;
449 unsigned char BGST:1;
454 extern volatile __LVDCON_bits_t __at(LVDCON_ADDR) LVDCON_bits;
456 #define LV0 LVDCON_bits.LV0
457 #define LV1 LVDCON_bits.LV1
458 #define LV2 LVDCON_bits.LV2
459 #define LV3 LVDCON_bits.LV3
460 #define LVDEN LVDCON_bits.LVDEN
461 #define BGST LVDCON_bits.BGST
463 // ----- OPTION_REG bits --------------------
470 unsigned char T0SE:1;
471 unsigned char T0CS:1;
472 unsigned char INTEDG:1;
473 unsigned char NOT_RBPU:1;
475 } __OPTION_REG_bits_t;
476 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
478 #define PS0 OPTION_REG_bits.PS0
479 #define PS1 OPTION_REG_bits.PS1
480 #define PS2 OPTION_REG_bits.PS2
481 #define PSA OPTION_REG_bits.PSA
482 #define T0SE OPTION_REG_bits.T0SE
483 #define T0CS OPTION_REG_bits.T0CS
484 #define INTEDG OPTION_REG_bits.INTEDG
485 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
487 // ----- PCON bits --------------------
490 unsigned char NOT_BO:1;
491 unsigned char NOT_POR:1;
493 unsigned char OSCF:1;
500 unsigned char NOT_BOR:1;
510 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
512 #define NOT_BO PCON_bits.NOT_BO
513 #define NOT_BOR PCON_bits.NOT_BOR
514 #define NOT_POR PCON_bits.NOT_POR
515 #define OSCF PCON_bits.OSCF
517 // ----- PIE1 bits --------------------
520 unsigned char TMR1IE:1;
521 unsigned char TMR2IE:1;
522 unsigned char CCP1IE:1;
523 unsigned char SSPIE:1;
526 unsigned char ADIE:1;
530 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
532 #define TMR1IE PIE1_bits.TMR1IE
533 #define TMR2IE PIE1_bits.TMR2IE
534 #define CCP1IE PIE1_bits.CCP1IE
535 #define SSPIE PIE1_bits.SSPIE
536 #define ADIE PIE1_bits.ADIE
538 // ----- PIE2 bits --------------------
544 unsigned char BCLIE:1;
548 unsigned char LVDIE:1;
551 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
553 #define BCLIE PIE2_bits.BCLIE
554 #define LVDIE PIE2_bits.LVDIE
556 // ----- PIR1 bits --------------------
559 unsigned char TMR1IF:1;
560 unsigned char TMR2IF:1;
561 unsigned char CCP1IF:1;
562 unsigned char SSPIF:1;
565 unsigned char ADIF:1;
569 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
571 #define TMR1IF PIR1_bits.TMR1IF
572 #define TMR2IF PIR1_bits.TMR2IF
573 #define CCP1IF PIR1_bits.CCP1IF
574 #define SSPIF PIR1_bits.SSPIF
575 #define ADIF PIR1_bits.ADIF
577 // ----- PIR2 bits --------------------
583 unsigned char BCLIF:1;
587 unsigned char LVDIF:1;
590 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
592 #define BCLIF PIR2_bits.BCLIF
593 #define LVDIF PIR2_bits.LVDIF
595 // ----- PMCON1 bits --------------------
608 extern volatile __PMCON1_bits_t __at(PMCON1_ADDR) PMCON1_bits;
610 #define RD PMCON1_bits.RD
612 // ----- REFCON bits --------------------
619 unsigned char VRLOEN:1;
620 unsigned char VRHOEN:1;
621 unsigned char VRLEN:1;
622 unsigned char VRHEN:1;
625 extern volatile __REFCON_bits_t __at(REFCON_ADDR) REFCON_bits;
627 #define VRLOEN REFCON_bits.VRLOEN
628 #define VRHOEN REFCON_bits.VRHOEN
629 #define VRLEN REFCON_bits.VRLEN
630 #define VRHEN REFCON_bits.VRHEN
632 // ----- SSPCON bits --------------------
635 unsigned char SSPM0:1;
636 unsigned char SSPM1:1;
637 unsigned char SSPM2:1;
638 unsigned char SSPM3:1;
640 unsigned char SSPEN:1;
641 unsigned char SSPOV:1;
642 unsigned char WCOL:1;
645 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
647 #define SSPM0 SSPCON_bits.SSPM0
648 #define SSPM1 SSPCON_bits.SSPM1
649 #define SSPM2 SSPCON_bits.SSPM2
650 #define SSPM3 SSPCON_bits.SSPM3
651 #define CKP SSPCON_bits.CKP
652 #define SSPEN SSPCON_bits.SSPEN
653 #define SSPOV SSPCON_bits.SSPOV
654 #define WCOL SSPCON_bits.WCOL
656 // ----- SSPCON2 bits --------------------
660 unsigned char RSEN:1;
662 unsigned char RCEN:1;
663 unsigned char ACKEN:1;
664 unsigned char ACKDT:1;
665 unsigned char ACKSTAT:1;
666 unsigned char GCEN:1;
669 extern volatile __SSPCON2_bits_t __at(SSPCON2_ADDR) SSPCON2_bits;
671 #define SEN SSPCON2_bits.SEN
672 #define RSEN SSPCON2_bits.RSEN
673 #define PEN SSPCON2_bits.PEN
674 #define RCEN SSPCON2_bits.RCEN
675 #define ACKEN SSPCON2_bits.ACKEN
676 #define ACKDT SSPCON2_bits.ACKDT
677 #define ACKSTAT SSPCON2_bits.ACKSTAT
678 #define GCEN SSPCON2_bits.GCEN
680 // ----- SSPSTAT bits --------------------
695 unsigned char I2C_READ:1;
696 unsigned char I2C_START:1;
697 unsigned char I2C_STOP:1;
698 unsigned char I2C_DATA:1;
705 unsigned char NOT_W:1;
708 unsigned char NOT_A:1;
715 unsigned char NOT_WRITE:1;
718 unsigned char NOT_ADDRESS:1;
735 unsigned char READ_WRITE:1;
738 unsigned char DATA_ADDRESS:1;
743 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
745 #define BF SSPSTAT_bits.BF
746 #define UA SSPSTAT_bits.UA
747 #define R SSPSTAT_bits.R
748 #define I2C_READ SSPSTAT_bits.I2C_READ
749 #define NOT_W SSPSTAT_bits.NOT_W
750 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
751 #define R_W SSPSTAT_bits.R_W
752 #define READ_WRITE SSPSTAT_bits.READ_WRITE
753 #define S SSPSTAT_bits.S
754 #define I2C_START SSPSTAT_bits.I2C_START
755 #define P SSPSTAT_bits.P
756 #define I2C_STOP SSPSTAT_bits.I2C_STOP
757 #define D SSPSTAT_bits.D
758 #define I2C_DATA SSPSTAT_bits.I2C_DATA
759 #define NOT_A SSPSTAT_bits.NOT_A
760 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
761 #define D_A SSPSTAT_bits.D_A
762 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
763 #define CKE SSPSTAT_bits.CKE
764 #define SMP SSPSTAT_bits.SMP
766 // ----- STATUS bits --------------------
772 unsigned char NOT_PD:1;
773 unsigned char NOT_TO:1;
779 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
781 #define C STATUS_bits.C
782 #define DC STATUS_bits.DC
783 #define Z STATUS_bits.Z
784 #define NOT_PD STATUS_bits.NOT_PD
785 #define NOT_TO STATUS_bits.NOT_TO
786 #define RP0 STATUS_bits.RP0
787 #define RP1 STATUS_bits.RP1
788 #define IRP STATUS_bits.IRP
790 // ----- T1CON bits --------------------
793 unsigned char TMR1ON:1;
794 unsigned char TMR1CS:1;
795 unsigned char NOT_T1SYNC:1;
796 unsigned char T1OSCEN:1;
797 unsigned char T1CKPS0:1;
798 unsigned char T1CKPS1:1;
805 unsigned char T1INSYNC:1;
813 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
815 #define TMR1ON T1CON_bits.TMR1ON
816 #define TMR1CS T1CON_bits.TMR1CS
817 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
818 #define T1INSYNC T1CON_bits.T1INSYNC
819 #define T1OSCEN T1CON_bits.T1OSCEN
820 #define T1CKPS0 T1CON_bits.T1CKPS0
821 #define T1CKPS1 T1CON_bits.T1CKPS1
823 // ----- T2CON bits --------------------
826 unsigned char T2CKPS0:1;
827 unsigned char T2CKPS1:1;
828 unsigned char TMR2ON:1;
829 unsigned char TOUTPS0:1;
830 unsigned char TOUTPS1:1;
831 unsigned char TOUTPS2:1;
832 unsigned char TOUTPS3:1;
836 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
838 #define T2CKPS0 T2CON_bits.T2CKPS0
839 #define T2CKPS1 T2CON_bits.T2CKPS1
840 #define TMR2ON T2CON_bits.TMR2ON
841 #define TOUTPS0 T2CON_bits.TOUTPS0
842 #define TOUTPS1 T2CON_bits.TOUTPS1
843 #define TOUTPS2 T2CON_bits.TOUTPS2
844 #define TOUTPS3 T2CON_bits.TOUTPS3