2 // Register Declarations for Microchip 16C765 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRES_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define TRISD_ADDR 0x0088
63 #define TRISE_ADDR 0x0089
64 #define PIE1_ADDR 0x008C
65 #define PIE2_ADDR 0x008D
66 #define PCON_ADDR 0x008E
67 #define PR2_ADDR 0x0092
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define ADCON1_ADDR 0x009F
71 #define UIR_ADDR 0x0190
72 #define UIE_ADDR 0x0191
73 #define UEIR_ADDR 0x0192
74 #define UEIE_ADDR 0x0193
75 #define USTAT_ADDR 0x0194
76 #define UCTRL_ADDR 0x0195
77 #define UADDR_ADDR 0x0196
78 #define USWSTAT_ADDR 0x0197
79 #define UEP0_ADDR 0x0198
80 #define UEP1_ADDR 0x0199
81 #define UEP2_ADDR 0x019A
82 #define BD0OST_ADDR 0x01A0
83 #define BD0OBC_ADDR 0x01A1
84 #define BD0OAL_ADDR 0x01A2
85 #define BD0IST_ADDR 0x01A4
86 #define BD0IBC_ADDR 0x01A5
87 #define BD0IAL_ADDR 0x01A6
88 #define BD1OST_ADDR 0x01A8
89 #define BD1OBC_ADDR 0x01A9
90 #define BD1OAL_ADDR 0x01AA
91 #define BD1IST_ADDR 0x01AC
92 #define BD1IBC_ADDR 0x01AD
93 #define BD1IAL_ADDR 0x01AE
94 #define BD2OST_ADDR 0x01B0
95 #define BD2OBC_ADDR 0x01B1
96 #define BD2OAL_ADDR 0x01B2
97 #define BD2IST_ADDR 0x01B4
98 #define BD2IBC_ADDR 0x01B5
99 #define BD2IAL_ADDR 0x01B6
102 // Memory organization.
105 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
106 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
107 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
108 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
109 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
110 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
111 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
112 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
113 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
114 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
115 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
116 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
117 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
118 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
119 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
120 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
121 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
122 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
123 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
124 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
125 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
126 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
127 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
128 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
129 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
130 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
131 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
132 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
133 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
134 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
135 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
136 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
137 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
138 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
139 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
140 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
141 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
142 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
143 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
144 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
145 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
146 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
147 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
148 #pragma memmap UIR_ADDR UIR_ADDR SFR 0x000 // UIR
149 #pragma memmap UIE_ADDR UIE_ADDR SFR 0x000 // UIE
150 #pragma memmap UEIR_ADDR UEIR_ADDR SFR 0x000 // UEIR
151 #pragma memmap UEIE_ADDR UEIE_ADDR SFR 0x000 // UEIE
152 #pragma memmap USTAT_ADDR USTAT_ADDR SFR 0x000 // USTAT
153 #pragma memmap UCTRL_ADDR UCTRL_ADDR SFR 0x000 // UCTRL
154 #pragma memmap UADDR_ADDR UADDR_ADDR SFR 0x000 // UADDR
155 #pragma memmap USWSTAT_ADDR USWSTAT_ADDR SFR 0x000 // USWSTAT
156 #pragma memmap UEP0_ADDR UEP0_ADDR SFR 0x000 // UEP0
157 #pragma memmap UEP1_ADDR UEP1_ADDR SFR 0x000 // UEP1
158 #pragma memmap UEP2_ADDR UEP2_ADDR SFR 0x000 // UEP2
159 #pragma memmap BD0OST_ADDR BD0OST_ADDR SFR 0x000 // BD0OST
160 #pragma memmap BD0OBC_ADDR BD0OBC_ADDR SFR 0x000 // BD0OBC
161 #pragma memmap BD0OAL_ADDR BD0OAL_ADDR SFR 0x000 // BD0OAL
162 #pragma memmap BD0IST_ADDR BD0IST_ADDR SFR 0x000 // BD0IST
163 #pragma memmap BD0IBC_ADDR BD0IBC_ADDR SFR 0x000 // BD0IBC
164 #pragma memmap BD0IAL_ADDR BD0IAL_ADDR SFR 0x000 // BD0IAL
165 #pragma memmap BD1OST_ADDR BD1OST_ADDR SFR 0x000 // BD1OST
166 #pragma memmap BD1OBC_ADDR BD1OBC_ADDR SFR 0x000 // BD1OBC
167 #pragma memmap BD1OAL_ADDR BD1OAL_ADDR SFR 0x000 // BD1OAL
168 #pragma memmap BD1IST_ADDR BD1IST_ADDR SFR 0x000 // BD1IST
169 #pragma memmap BD1IBC_ADDR BD1IBC_ADDR SFR 0x000 // BD1IBC
170 #pragma memmap BD1IAL_ADDR BD1IAL_ADDR SFR 0x000 // BD1IAL
171 #pragma memmap BD2OST_ADDR BD2OST_ADDR SFR 0x000 // BD2OST
172 #pragma memmap BD2OBC_ADDR BD2OBC_ADDR SFR 0x000 // BD2OBC
173 #pragma memmap BD2OAL_ADDR BD2OAL_ADDR SFR 0x000 // BD2OAL
174 #pragma memmap BD2IST_ADDR BD2IST_ADDR SFR 0x000 // BD2IST
175 #pragma memmap BD2IBC_ADDR BD2IBC_ADDR SFR 0x000 // BD2IBC
176 #pragma memmap BD2IAL_ADDR BD2IAL_ADDR SFR 0x000 // BD2IAL
180 // P16C765.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
183 // This header file defines configurations, registers, and other useful bits of
184 // information for the PIC16C765 microcontroller. These names are taken to match
185 // the data sheets as closely as possible.
187 // Note that the processor must be selected before this file is
188 // included. The processor may be selected the following ways:
190 // 1. Command line switch:
191 // C:\ MPASM MYFILE.ASM /PIC16C765
192 // 2. LIST directive in the source file
194 // 3. Processor Type entry in the MPASM full-screen interface
196 //==========================================================================
200 //==========================================================================
204 //1.00 28 Sep 99 Initial Release
206 //==========================================================================
210 //==========================================================================
213 // MESSG "Processor-header file mismatch. Verify selected processor."
216 //==========================================================================
218 // Register Definitions
220 //==========================================================================
225 //----- Register Files------------------------------------------------------
227 extern __data __at (INDF_ADDR) volatile char INDF;
228 extern __sfr __at (TMR0_ADDR) TMR0;
229 extern __data __at (PCL_ADDR) volatile char PCL;
230 extern __sfr __at (STATUS_ADDR) STATUS;
231 extern __sfr __at (FSR_ADDR) FSR;
232 extern __sfr __at (PORTA_ADDR) PORTA;
233 extern __sfr __at (PORTB_ADDR) PORTB;
234 extern __sfr __at (PORTC_ADDR) PORTC;
235 extern __sfr __at (PORTD_ADDR) PORTD;
236 extern __sfr __at (PORTE_ADDR) PORTE;
237 extern __sfr __at (PCLATH_ADDR) PCLATH;
238 extern __sfr __at (INTCON_ADDR) INTCON;
239 extern __sfr __at (PIR1_ADDR) PIR1;
240 extern __sfr __at (PIR2_ADDR) PIR2;
241 extern __sfr __at (TMR1L_ADDR) TMR1L;
242 extern __sfr __at (TMR1H_ADDR) TMR1H;
243 extern __sfr __at (T1CON_ADDR) T1CON;
244 extern __sfr __at (TMR2_ADDR) TMR2;
245 extern __sfr __at (T2CON_ADDR) T2CON;
246 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
247 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
248 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
249 extern __sfr __at (RCSTA_ADDR) RCSTA;
250 extern __sfr __at (TXREG_ADDR) TXREG;
251 extern __sfr __at (RCREG_ADDR) RCREG;
252 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
253 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
254 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
255 extern __sfr __at (ADRES_ADDR) ADRES;
256 extern __sfr __at (ADCON0_ADDR) ADCON0;
258 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
259 extern __sfr __at (TRISA_ADDR) TRISA;
260 extern __sfr __at (TRISB_ADDR) TRISB;
261 extern __sfr __at (TRISC_ADDR) TRISC;
262 extern __sfr __at (TRISD_ADDR) TRISD;
263 extern __sfr __at (TRISE_ADDR) TRISE;
264 extern __sfr __at (PIE1_ADDR) PIE1;
265 extern __sfr __at (PIE2_ADDR) PIE2;
266 extern __sfr __at (PCON_ADDR) PCON;
267 extern __sfr __at (PR2_ADDR) PR2;
268 extern __sfr __at (TXSTA_ADDR) TXSTA;
269 extern __sfr __at (SPBRG_ADDR) SPBRG;
270 extern __sfr __at (ADCON1_ADDR) ADCON1;
271 extern __sfr __at (UIR_ADDR) UIR;
272 extern __sfr __at (UIE_ADDR) UIE;
273 extern __sfr __at (UEIR_ADDR) UEIR;
274 extern __sfr __at (UEIE_ADDR) UEIE;
275 extern __sfr __at (USTAT_ADDR) USTAT;
276 extern __sfr __at (UCTRL_ADDR) UCTRL;
277 extern __sfr __at (UADDR_ADDR) UADDR;
278 extern __sfr __at (USWSTAT_ADDR) USWSTAT;
279 extern __sfr __at (UEP0_ADDR) UEP0;
280 extern __sfr __at (UEP1_ADDR) UEP1;
281 extern __sfr __at (UEP2_ADDR) UEP2;
283 extern __sfr __at (BD0OST_ADDR) BD0OST;
284 extern __sfr __at (BD0OBC_ADDR) BD0OBC;
285 extern __sfr __at (BD0OAL_ADDR) BD0OAL;
286 extern __sfr __at (BD0IST_ADDR) BD0IST;
287 extern __sfr __at (BD0IBC_ADDR) BD0IBC;
288 extern __sfr __at (BD0IAL_ADDR) BD0IAL;
290 extern __sfr __at (BD1OST_ADDR) BD1OST;
291 extern __sfr __at (BD1OBC_ADDR) BD1OBC;
292 extern __sfr __at (BD1OAL_ADDR) BD1OAL;
293 extern __sfr __at (BD1IST_ADDR) BD1IST;
294 extern __sfr __at (BD1IBC_ADDR) BD1IBC;
295 extern __sfr __at (BD1IAL_ADDR) BD1IAL;
297 extern __sfr __at (BD2OST_ADDR) BD2OST;
298 extern __sfr __at (BD2OBC_ADDR) BD2OBC;
299 extern __sfr __at (BD2OAL_ADDR) BD2OAL;
300 extern __sfr __at (BD2IST_ADDR) BD2IST;
301 extern __sfr __at (BD2IBC_ADDR) BD2IBC;
302 extern __sfr __at (BD2IAL_ADDR) BD2IAL;
305 //----- STATUS Bits --------------------------------------------------------
308 //----- INTCON Bits --------------------------------------------------------
311 //----- PIR1 Bits ----------------------------------------------------------
314 //----- PIR2 Bits ----------------------------------------------------------
317 //----- T1CON Bits ---------------------------------------------------------
320 //----- T2CON Bits ---------------------------------------------------------
323 //----- CCP1CON Bits -------------------------------------------------------
326 //----- RCSTA Bits ---------------------------------------------------------
329 //----- CCP2CON Bits -------------------------------------------------------
332 //----- ADCON0 Bits --------------------------------------------------------
335 //----- OPTION Bits --------------------------------------------------------
338 //----- TRISE Bits ---------------------------------------------------------
341 //----- PIE1 Bits ----------------------------------------------------------
344 //----- PIE2 Bits ----------------------------------------------------------
347 //----- PCON Bits ----------------------------------------------------------
350 //----- TXSTA Bits ---------------------------------------------------------
353 //----- ADCON1 Bits --------------------------------------------------------
356 //----- UIR/UIE Bits -----------------------------------------------------
359 //----- UEIR/UEIE Bits -----------------------------------------------------
362 //----- USTAT Bits ---------------------------------------------------------
365 //----- UCTRL Bits ---------------------------------------------------------
367 //----- UEP0/UEP1/UEP2 Bits ------------------------------------------------
370 //----- Buffer descriptor Bits ---------------------------------------------
372 //==========================================================================
376 //==========================================================================
379 // __BADRAM H'13', H'14', H'8F'-H'91'
380 // __BADRAM H'93'-H'97', H'9A'-H'9E'
381 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F'
382 // __BADRAM H'185', H'187'-H'189', H'18C'-H'18F', H'19B'-H'19F'
383 // __BADRAM H'1E0'-H'1EF'
384 //==========================================================================
386 // Configuration Bits
388 //==========================================================================
390 #define _CP_ALL 0x00CF
391 #define _CP_75 0x15DF
392 #define _CP_50 0x2AEF
393 #define _CP_OFF 0x3FFF
394 #define _PWRTE_OFF 0x3FFF
395 #define _PWRTE_ON 0x3FF7
396 #define _WDT_ON 0x3FFF
397 #define _WDT_OFF 0x3FFB
398 #define _HS_OSC 0x3FFC
399 #define _EC_OSC 0x3FFD
400 #define _H4_OSC 0x3FFE
401 #define _E4_OSC 0x3FFF
405 // ----- ADCON0 bits --------------------
408 unsigned char ADON:1;
411 unsigned char CHS0:1;
412 unsigned char CHS1:1;
413 unsigned char CHS2:1;
414 unsigned char ADCS0:1;
415 unsigned char ADCS1:1;
420 unsigned char NOT_DONE:1;
430 unsigned char GO_DONE:1;
438 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
440 #define ADON ADCON0_bits.ADON
441 #define GO ADCON0_bits.GO
442 #define NOT_DONE ADCON0_bits.NOT_DONE
443 #define GO_DONE ADCON0_bits.GO_DONE
444 #define CHS0 ADCON0_bits.CHS0
445 #define CHS1 ADCON0_bits.CHS1
446 #define CHS2 ADCON0_bits.CHS2
447 #define ADCS0 ADCON0_bits.ADCS0
448 #define ADCS1 ADCON0_bits.ADCS1
450 // ----- ADCON1 bits --------------------
453 unsigned char PCFG0:1;
454 unsigned char PCFG1:1;
455 unsigned char PCFG2:1;
463 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
465 #define PCFG0 ADCON1_bits.PCFG0
466 #define PCFG1 ADCON1_bits.PCFG1
467 #define PCFG2 ADCON1_bits.PCFG2
469 // ----- CCP1CON bits --------------------
472 unsigned char CCP1M0:1;
473 unsigned char CCP1M1:1;
474 unsigned char CCP1M2:1;
475 unsigned char CCP1M3:1;
476 unsigned char DC1B0:1;
477 unsigned char DC1B1:1;
482 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
484 #define CCP1M0 CCP1CON_bits.CCP1M0
485 #define CCP1M1 CCP1CON_bits.CCP1M1
486 #define CCP1M2 CCP1CON_bits.CCP1M2
487 #define CCP1M3 CCP1CON_bits.CCP1M3
488 #define DC1B0 CCP1CON_bits.DC1B0
489 #define DC1B1 CCP1CON_bits.DC1B1
491 // ----- CCP2CON bits --------------------
494 unsigned char CCP2M0:1;
495 unsigned char CCP2M1:1;
496 unsigned char CCP2M2:1;
497 unsigned char CCP2M3:1;
498 unsigned char DC2B0:1;
499 unsigned char DC2B1:1;
504 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
506 #define CCP2M0 CCP2CON_bits.CCP2M0
507 #define CCP2M1 CCP2CON_bits.CCP2M1
508 #define CCP2M2 CCP2CON_bits.CCP2M2
509 #define CCP2M3 CCP2CON_bits.CCP2M3
510 #define DC2B0 CCP2CON_bits.DC2B0
511 #define DC2B1 CCP2CON_bits.DC2B1
513 // ----- INTCON bits --------------------
516 unsigned char RBIF:1;
517 unsigned char INTF:1;
518 unsigned char T0IF:1;
519 unsigned char RBIE:1;
520 unsigned char INTE:1;
521 unsigned char T0IE:1;
522 unsigned char PEIE:1;
526 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
528 #define RBIF INTCON_bits.RBIF
529 #define INTF INTCON_bits.INTF
530 #define T0IF INTCON_bits.T0IF
531 #define RBIE INTCON_bits.RBIE
532 #define INTE INTCON_bits.INTE
533 #define T0IE INTCON_bits.T0IE
534 #define PEIE INTCON_bits.PEIE
535 #define GIE INTCON_bits.GIE
537 // ----- OPTION_REG bits --------------------
544 unsigned char T0SE:1;
545 unsigned char T0CS:1;
546 unsigned char INTEDG:1;
547 unsigned char NOT_RBPU:1;
549 } __OPTION_REG_bits_t;
550 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
552 #define PS0 OPTION_REG_bits.PS0
553 #define PS1 OPTION_REG_bits.PS1
554 #define PS2 OPTION_REG_bits.PS2
555 #define PSA OPTION_REG_bits.PSA
556 #define T0SE OPTION_REG_bits.T0SE
557 #define T0CS OPTION_REG_bits.T0CS
558 #define INTEDG OPTION_REG_bits.INTEDG
559 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
561 // ----- PCON bits --------------------
564 unsigned char NOT_BO:1;
565 unsigned char NOT_POR:1;
574 unsigned char NOT_BOR:1;
584 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
586 #define NOT_BO PCON_bits.NOT_BO
587 #define NOT_BOR PCON_bits.NOT_BOR
588 #define NOT_POR PCON_bits.NOT_POR
590 // ----- PIE1 bits --------------------
593 unsigned char TMR1IE:1;
594 unsigned char TMR2IE:1;
595 unsigned char CCP1IE:1;
596 unsigned char USBIE:1;
597 unsigned char TXIE:1;
598 unsigned char RCIE:1;
599 unsigned char ADIE:1;
600 unsigned char PSPIE:1;
603 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
605 #define TMR1IE PIE1_bits.TMR1IE
606 #define TMR2IE PIE1_bits.TMR2IE
607 #define CCP1IE PIE1_bits.CCP1IE
608 #define USBIE PIE1_bits.USBIE
609 #define TXIE PIE1_bits.TXIE
610 #define RCIE PIE1_bits.RCIE
611 #define ADIE PIE1_bits.ADIE
612 #define PSPIE PIE1_bits.PSPIE
614 // ----- PIE2 bits --------------------
617 unsigned char CCP2IE:1;
627 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
629 #define CCP2IE PIE2_bits.CCP2IE
631 // ----- PIR1 bits --------------------
634 unsigned char TMR1IF:1;
635 unsigned char TMR2IF:1;
636 unsigned char CCP1IF:1;
637 unsigned char USBIF:1;
638 unsigned char TXIF:1;
639 unsigned char RCIF:1;
640 unsigned char ADIF:1;
641 unsigned char PSPIF:1;
644 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
646 #define TMR1IF PIR1_bits.TMR1IF
647 #define TMR2IF PIR1_bits.TMR2IF
648 #define CCP1IF PIR1_bits.CCP1IF
649 #define USBIF PIR1_bits.USBIF
650 #define TXIF PIR1_bits.TXIF
651 #define RCIF PIR1_bits.RCIF
652 #define ADIF PIR1_bits.ADIF
653 #define PSPIF PIR1_bits.PSPIF
655 // ----- PIR2 bits --------------------
658 unsigned char CCP2IF:1;
668 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
670 #define CCP2IF PIR2_bits.CCP2IF
672 // ----- RCSTA bits --------------------
675 unsigned char RX9D:1;
676 unsigned char OERR:1;
677 unsigned char FERR:1;
679 unsigned char CREN:1;
680 unsigned char SREN:1;
682 unsigned char SPEN:1;
685 unsigned char RCD8:1;
701 unsigned char NOT_RC8:1;
711 unsigned char RC8_9:1;
715 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
717 #define RX9D RCSTA_bits.RX9D
718 #define RCD8 RCSTA_bits.RCD8
719 #define OERR RCSTA_bits.OERR
720 #define FERR RCSTA_bits.FERR
721 #define CREN RCSTA_bits.CREN
722 #define SREN RCSTA_bits.SREN
723 #define RX9 RCSTA_bits.RX9
724 #define RC9 RCSTA_bits.RC9
725 #define NOT_RC8 RCSTA_bits.NOT_RC8
726 #define RC8_9 RCSTA_bits.RC8_9
727 #define SPEN RCSTA_bits.SPEN
729 // ----- STATUS bits --------------------
735 unsigned char NOT_PD:1;
736 unsigned char NOT_TO:1;
742 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
744 #define C STATUS_bits.C
745 #define DC STATUS_bits.DC
746 #define Z STATUS_bits.Z
747 #define NOT_PD STATUS_bits.NOT_PD
748 #define NOT_TO STATUS_bits.NOT_TO
749 #define RP0 STATUS_bits.RP0
750 #define RP1 STATUS_bits.RP1
751 #define IRP STATUS_bits.IRP
753 // ----- T1CON bits --------------------
756 unsigned char TMR1ON:1;
757 unsigned char TMR1CS:1;
758 unsigned char NOT_T1SYNC:1;
759 unsigned char T1OSCEN:1;
760 unsigned char T1CKPS0:1;
761 unsigned char T1CKPS1:1;
768 unsigned char T1INSYNC:1;
776 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
778 #define TMR1ON T1CON_bits.TMR1ON
779 #define TMR1CS T1CON_bits.TMR1CS
780 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
781 #define T1INSYNC T1CON_bits.T1INSYNC
782 #define T1OSCEN T1CON_bits.T1OSCEN
783 #define T1CKPS0 T1CON_bits.T1CKPS0
784 #define T1CKPS1 T1CON_bits.T1CKPS1
786 // ----- T2CON bits --------------------
789 unsigned char T2CKPS0:1;
790 unsigned char T2CKPS1:1;
791 unsigned char TMR2ON:1;
792 unsigned char TOUTPS0:1;
793 unsigned char TOUTPS1:1;
794 unsigned char TOUTPS2:1;
795 unsigned char TOUTPS3:1;
799 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
801 #define T2CKPS0 T2CON_bits.T2CKPS0
802 #define T2CKPS1 T2CON_bits.T2CKPS1
803 #define TMR2ON T2CON_bits.TMR2ON
804 #define TOUTPS0 T2CON_bits.TOUTPS0
805 #define TOUTPS1 T2CON_bits.TOUTPS1
806 #define TOUTPS2 T2CON_bits.TOUTPS2
807 #define TOUTPS3 T2CON_bits.TOUTPS3
809 // ----- TRISE bits --------------------
812 unsigned char TRISE0:1;
813 unsigned char TRISE1:1;
814 unsigned char TRISE2:1;
816 unsigned char PSPMODE:1;
817 unsigned char IBOV:1;
822 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
824 #define TRISE0 TRISE_bits.TRISE0
825 #define TRISE1 TRISE_bits.TRISE1
826 #define TRISE2 TRISE_bits.TRISE2
827 #define PSPMODE TRISE_bits.PSPMODE
828 #define IBOV TRISE_bits.IBOV
829 #define OBF TRISE_bits.OBF
830 #define IBF TRISE_bits.IBF
832 // ----- TXSTA bits --------------------
835 unsigned char TX9D:1;
836 unsigned char TRMT:1;
837 unsigned char BRGH:1;
839 unsigned char SYNC:1;
840 unsigned char TXEN:1;
842 unsigned char CSRC:1;
845 unsigned char TXD8:1;
851 unsigned char NOT_TX8:1;
861 unsigned char TX8_9:1;
865 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
867 #define TX9D TXSTA_bits.TX9D
868 #define TXD8 TXSTA_bits.TXD8
869 #define TRMT TXSTA_bits.TRMT
870 #define BRGH TXSTA_bits.BRGH
871 #define SYNC TXSTA_bits.SYNC
872 #define TXEN TXSTA_bits.TXEN
873 #define TX9 TXSTA_bits.TX9
874 #define NOT_TX8 TXSTA_bits.NOT_TX8
875 #define TX8_9 TXSTA_bits.TX8_9
876 #define CSRC TXSTA_bits.CSRC
878 // ----- UCTRL bits --------------------
882 unsigned char SUSPND:1;
883 unsigned char RESUME:1;
884 unsigned char DEV_ATT:1;
885 unsigned char PKT_DIS:1;
891 extern volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits;
893 #define SUSPND UCTRL_bits.SUSPND
894 #define RESUME UCTRL_bits.RESUME
895 #define DEV_ATT UCTRL_bits.DEV_ATT
896 #define PKT_DIS UCTRL_bits.PKT_DIS
897 #define SE0 UCTRL_bits.SE0
899 // ----- UEIE bits --------------------
902 unsigned char PID_ERR:1;
903 unsigned char CRC5:1;
904 unsigned char CRC16:1;
905 unsigned char DFN8:1;
906 unsigned char BTO_ERR:1;
907 unsigned char WRT_ERR:1;
908 unsigned char OWN_ERR:1;
909 unsigned char BTS_ERR:1;
912 extern volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits;
914 #define PID_ERR UEIE_bits.PID_ERR
915 #define CRC5 UEIE_bits.CRC5
916 #define CRC16 UEIE_bits.CRC16
917 #define DFN8 UEIE_bits.DFN8
918 #define BTO_ERR UEIE_bits.BTO_ERR
919 #define WRT_ERR UEIE_bits.WRT_ERR
920 #define OWN_ERR UEIE_bits.OWN_ERR
921 #define BTS_ERR UEIE_bits.BTS_ERR
923 // ----- UEP2 bits --------------------
926 unsigned char EP_STALL:1;
927 unsigned char EP_IN_EN:1;
928 unsigned char EP_OUT_EN:1;
929 unsigned char EP_CTL_DIS:1;
930 unsigned char PID2:1;
931 unsigned char PID3:1;
932 unsigned char DATA01:1;
933 unsigned char UOWN:1;
938 unsigned char BSTALL:1;
948 unsigned char PID0:1;
949 unsigned char PID1:1;
956 extern volatile __UEP2_bits_t __at(UEP2_ADDR) UEP2_bits;
958 #define EP_STALL UEP2_bits.EP_STALL
959 #define EP_IN_EN UEP2_bits.EP_IN_EN
960 #define EP_OUT_EN UEP2_bits.EP_OUT_EN
961 #define BSTALL UEP2_bits.BSTALL
962 #define PID0 UEP2_bits.PID0
963 #define EP_CTL_DIS UEP2_bits.EP_CTL_DIS
964 #define DTS UEP2_bits.DTS
965 #define PID1 UEP2_bits.PID1
966 #define PID2 UEP2_bits.PID2
967 #define PID3 UEP2_bits.PID3
968 #define DATA01 UEP2_bits.DATA01
969 #define UOWN UEP2_bits.UOWN
970 #define OWN UEP2_bits.OWN
972 // ----- UIE bits --------------------
975 unsigned char USB_RST:1;
976 unsigned char UERR:1;
977 unsigned char ACTIVITY:1;
978 unsigned char TOK_DNE:1;
979 unsigned char UIDLE:1;
980 unsigned char STALL:1;
985 extern volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits;
987 #define USB_RST UIE_bits.USB_RST
988 #define UERR UIE_bits.UERR
989 #define ACTIVITY UIE_bits.ACTIVITY
990 #define TOK_DNE UIE_bits.TOK_DNE
991 #define UIDLE UIE_bits.UIDLE
992 #define STALL UIE_bits.STALL
994 // ----- USTAT bits --------------------
1000 unsigned char ENDP0:1;
1001 unsigned char ENDP1:1;
1007 extern volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits;
1009 #define IN USTAT_bits.IN
1010 #define ENDP0 USTAT_bits.ENDP0
1011 #define ENDP1 USTAT_bits.ENDP1