2 // Register Declarations for Microchip 16C765 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRES_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define TRISD_ADDR 0x0088
63 #define TRISE_ADDR 0x0089
64 #define PIE1_ADDR 0x008C
65 #define PIE2_ADDR 0x008D
66 #define PCON_ADDR 0x008E
67 #define PR2_ADDR 0x0092
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define ADCON1_ADDR 0x009F
71 #define UIR_ADDR 0x0190
72 #define UIE_ADDR 0x0191
73 #define UEIR_ADDR 0x0192
74 #define UEIE_ADDR 0x0193
75 #define USTAT_ADDR 0x0194
76 #define UCTRL_ADDR 0x0195
77 #define UADDR_ADDR 0x0196
78 #define USWSTAT_ADDR 0x0197
79 #define UEP0_ADDR 0x0198
80 #define UEP1_ADDR 0x0199
81 #define UEP2_ADDR 0x019A
82 #define BD0OST_ADDR 0x01A0
83 #define BD0OBC_ADDR 0x01A1
84 #define BD0OAL_ADDR 0x01A2
85 #define BD0IST_ADDR 0x01A4
86 #define BD0IBC_ADDR 0x01A5
87 #define BD0IAL_ADDR 0x01A6
88 #define BD1OST_ADDR 0x01A8
89 #define BD1OBC_ADDR 0x01A9
90 #define BD1OAL_ADDR 0x01AA
91 #define BD1IST_ADDR 0x01AC
92 #define BD1IBC_ADDR 0x01AD
93 #define BD1IAL_ADDR 0x01AE
94 #define BD2OST_ADDR 0x01B0
95 #define BD2OBC_ADDR 0x01B1
96 #define BD2OAL_ADDR 0x01B2
97 #define BD2IST_ADDR 0x01B4
98 #define BD2IBC_ADDR 0x01B5
99 #define BD2IAL_ADDR 0x01B6
102 // Memory organization.
108 // P16C765.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
111 // This header file defines configurations, registers, and other useful bits of
112 // information for the PIC16C765 microcontroller. These names are taken to match
113 // the data sheets as closely as possible.
115 // Note that the processor must be selected before this file is
116 // included. The processor may be selected the following ways:
118 // 1. Command line switch:
119 // C:\ MPASM MYFILE.ASM /PIC16C765
120 // 2. LIST directive in the source file
122 // 3. Processor Type entry in the MPASM full-screen interface
124 //==========================================================================
128 //==========================================================================
132 //1.00 28 Sep 99 Initial Release
134 //==========================================================================
138 //==========================================================================
141 // MESSG "Processor-header file mismatch. Verify selected processor."
144 //==========================================================================
146 // Register Definitions
148 //==========================================================================
153 //----- Register Files------------------------------------------------------
155 extern __data __at (INDF_ADDR) volatile char INDF;
156 extern __sfr __at (TMR0_ADDR) TMR0;
157 extern __data __at (PCL_ADDR) volatile char PCL;
158 extern __sfr __at (STATUS_ADDR) STATUS;
159 extern __sfr __at (FSR_ADDR) FSR;
160 extern __sfr __at (PORTA_ADDR) PORTA;
161 extern __sfr __at (PORTB_ADDR) PORTB;
162 extern __sfr __at (PORTC_ADDR) PORTC;
163 extern __sfr __at (PORTD_ADDR) PORTD;
164 extern __sfr __at (PORTE_ADDR) PORTE;
165 extern __sfr __at (PCLATH_ADDR) PCLATH;
166 extern __sfr __at (INTCON_ADDR) INTCON;
167 extern __sfr __at (PIR1_ADDR) PIR1;
168 extern __sfr __at (PIR2_ADDR) PIR2;
169 extern __sfr __at (TMR1L_ADDR) TMR1L;
170 extern __sfr __at (TMR1H_ADDR) TMR1H;
171 extern __sfr __at (T1CON_ADDR) T1CON;
172 extern __sfr __at (TMR2_ADDR) TMR2;
173 extern __sfr __at (T2CON_ADDR) T2CON;
174 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
175 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
176 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
177 extern __sfr __at (RCSTA_ADDR) RCSTA;
178 extern __sfr __at (TXREG_ADDR) TXREG;
179 extern __sfr __at (RCREG_ADDR) RCREG;
180 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
181 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
182 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
183 extern __sfr __at (ADRES_ADDR) ADRES;
184 extern __sfr __at (ADCON0_ADDR) ADCON0;
186 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
187 extern __sfr __at (TRISA_ADDR) TRISA;
188 extern __sfr __at (TRISB_ADDR) TRISB;
189 extern __sfr __at (TRISC_ADDR) TRISC;
190 extern __sfr __at (TRISD_ADDR) TRISD;
191 extern __sfr __at (TRISE_ADDR) TRISE;
192 extern __sfr __at (PIE1_ADDR) PIE1;
193 extern __sfr __at (PIE2_ADDR) PIE2;
194 extern __sfr __at (PCON_ADDR) PCON;
195 extern __sfr __at (PR2_ADDR) PR2;
196 extern __sfr __at (TXSTA_ADDR) TXSTA;
197 extern __sfr __at (SPBRG_ADDR) SPBRG;
198 extern __sfr __at (ADCON1_ADDR) ADCON1;
199 extern __sfr __at (UIR_ADDR) UIR;
200 extern __sfr __at (UIE_ADDR) UIE;
201 extern __sfr __at (UEIR_ADDR) UEIR;
202 extern __sfr __at (UEIE_ADDR) UEIE;
203 extern __sfr __at (USTAT_ADDR) USTAT;
204 extern __sfr __at (UCTRL_ADDR) UCTRL;
205 extern __sfr __at (UADDR_ADDR) UADDR;
206 extern __sfr __at (USWSTAT_ADDR) USWSTAT;
207 extern __sfr __at (UEP0_ADDR) UEP0;
208 extern __sfr __at (UEP1_ADDR) UEP1;
209 extern __sfr __at (UEP2_ADDR) UEP2;
211 extern __sfr __at (BD0OST_ADDR) BD0OST;
212 extern __sfr __at (BD0OBC_ADDR) BD0OBC;
213 extern __sfr __at (BD0OAL_ADDR) BD0OAL;
214 extern __sfr __at (BD0IST_ADDR) BD0IST;
215 extern __sfr __at (BD0IBC_ADDR) BD0IBC;
216 extern __sfr __at (BD0IAL_ADDR) BD0IAL;
218 extern __sfr __at (BD1OST_ADDR) BD1OST;
219 extern __sfr __at (BD1OBC_ADDR) BD1OBC;
220 extern __sfr __at (BD1OAL_ADDR) BD1OAL;
221 extern __sfr __at (BD1IST_ADDR) BD1IST;
222 extern __sfr __at (BD1IBC_ADDR) BD1IBC;
223 extern __sfr __at (BD1IAL_ADDR) BD1IAL;
225 extern __sfr __at (BD2OST_ADDR) BD2OST;
226 extern __sfr __at (BD2OBC_ADDR) BD2OBC;
227 extern __sfr __at (BD2OAL_ADDR) BD2OAL;
228 extern __sfr __at (BD2IST_ADDR) BD2IST;
229 extern __sfr __at (BD2IBC_ADDR) BD2IBC;
230 extern __sfr __at (BD2IAL_ADDR) BD2IAL;
233 //----- STATUS Bits --------------------------------------------------------
236 //----- INTCON Bits --------------------------------------------------------
239 //----- PIR1 Bits ----------------------------------------------------------
242 //----- PIR2 Bits ----------------------------------------------------------
245 //----- T1CON Bits ---------------------------------------------------------
248 //----- T2CON Bits ---------------------------------------------------------
251 //----- CCP1CON Bits -------------------------------------------------------
254 //----- RCSTA Bits ---------------------------------------------------------
257 //----- CCP2CON Bits -------------------------------------------------------
260 //----- ADCON0 Bits --------------------------------------------------------
263 //----- OPTION Bits --------------------------------------------------------
266 //----- TRISE Bits ---------------------------------------------------------
269 //----- PIE1 Bits ----------------------------------------------------------
272 //----- PIE2 Bits ----------------------------------------------------------
275 //----- PCON Bits ----------------------------------------------------------
278 //----- TXSTA Bits ---------------------------------------------------------
281 //----- ADCON1 Bits --------------------------------------------------------
284 //----- UIR/UIE Bits -----------------------------------------------------
287 //----- UEIR/UEIE Bits -----------------------------------------------------
290 //----- USTAT Bits ---------------------------------------------------------
293 //----- UCTRL Bits ---------------------------------------------------------
295 //----- UEP0/UEP1/UEP2 Bits ------------------------------------------------
298 //----- Buffer descriptor Bits ---------------------------------------------
300 //==========================================================================
304 //==========================================================================
307 // __BADRAM H'13', H'14', H'8F'-H'91'
308 // __BADRAM H'93'-H'97', H'9A'-H'9E'
309 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F'
310 // __BADRAM H'185', H'187'-H'189', H'18C'-H'18F', H'19B'-H'19F'
311 // __BADRAM H'1E0'-H'1EF'
312 //==========================================================================
314 // Configuration Bits
316 //==========================================================================
318 #define _CP_ALL 0x00CF
319 #define _CP_75 0x15DF
320 #define _CP_50 0x2AEF
321 #define _CP_OFF 0x3FFF
322 #define _PWRTE_OFF 0x3FFF
323 #define _PWRTE_ON 0x3FF7
324 #define _WDT_ON 0x3FFF
325 #define _WDT_OFF 0x3FFB
326 #define _HS_OSC 0x3FFC
327 #define _EC_OSC 0x3FFD
328 #define _H4_OSC 0x3FFE
329 #define _E4_OSC 0x3FFF
333 // ----- ADCON0 bits --------------------
336 unsigned char ADON:1;
339 unsigned char CHS0:1;
340 unsigned char CHS1:1;
341 unsigned char CHS2:1;
342 unsigned char ADCS0:1;
343 unsigned char ADCS1:1;
348 unsigned char NOT_DONE:1;
358 unsigned char GO_DONE:1;
366 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
368 #define ADON ADCON0_bits.ADON
369 #define GO ADCON0_bits.GO
370 #define NOT_DONE ADCON0_bits.NOT_DONE
371 #define GO_DONE ADCON0_bits.GO_DONE
372 #define CHS0 ADCON0_bits.CHS0
373 #define CHS1 ADCON0_bits.CHS1
374 #define CHS2 ADCON0_bits.CHS2
375 #define ADCS0 ADCON0_bits.ADCS0
376 #define ADCS1 ADCON0_bits.ADCS1
378 // ----- ADCON1 bits --------------------
381 unsigned char PCFG0:1;
382 unsigned char PCFG1:1;
383 unsigned char PCFG2:1;
391 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
393 #define PCFG0 ADCON1_bits.PCFG0
394 #define PCFG1 ADCON1_bits.PCFG1
395 #define PCFG2 ADCON1_bits.PCFG2
397 // ----- CCP1CON bits --------------------
400 unsigned char CCP1M0:1;
401 unsigned char CCP1M1:1;
402 unsigned char CCP1M2:1;
403 unsigned char CCP1M3:1;
404 unsigned char DC1B0:1;
405 unsigned char DC1B1:1;
410 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
412 #define CCP1M0 CCP1CON_bits.CCP1M0
413 #define CCP1M1 CCP1CON_bits.CCP1M1
414 #define CCP1M2 CCP1CON_bits.CCP1M2
415 #define CCP1M3 CCP1CON_bits.CCP1M3
416 #define DC1B0 CCP1CON_bits.DC1B0
417 #define DC1B1 CCP1CON_bits.DC1B1
419 // ----- CCP2CON bits --------------------
422 unsigned char CCP2M0:1;
423 unsigned char CCP2M1:1;
424 unsigned char CCP2M2:1;
425 unsigned char CCP2M3:1;
426 unsigned char DC2B0:1;
427 unsigned char DC2B1:1;
432 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
434 #define CCP2M0 CCP2CON_bits.CCP2M0
435 #define CCP2M1 CCP2CON_bits.CCP2M1
436 #define CCP2M2 CCP2CON_bits.CCP2M2
437 #define CCP2M3 CCP2CON_bits.CCP2M3
438 #define DC2B0 CCP2CON_bits.DC2B0
439 #define DC2B1 CCP2CON_bits.DC2B1
441 // ----- INTCON bits --------------------
444 unsigned char RBIF:1;
445 unsigned char INTF:1;
446 unsigned char T0IF:1;
447 unsigned char RBIE:1;
448 unsigned char INTE:1;
449 unsigned char T0IE:1;
450 unsigned char PEIE:1;
454 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
456 #define RBIF INTCON_bits.RBIF
457 #define INTF INTCON_bits.INTF
458 #define T0IF INTCON_bits.T0IF
459 #define RBIE INTCON_bits.RBIE
460 #define INTE INTCON_bits.INTE
461 #define T0IE INTCON_bits.T0IE
462 #define PEIE INTCON_bits.PEIE
463 #define GIE INTCON_bits.GIE
465 // ----- OPTION_REG bits --------------------
472 unsigned char T0SE:1;
473 unsigned char T0CS:1;
474 unsigned char INTEDG:1;
475 unsigned char NOT_RBPU:1;
477 } __OPTION_REG_bits_t;
478 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
480 #define PS0 OPTION_REG_bits.PS0
481 #define PS1 OPTION_REG_bits.PS1
482 #define PS2 OPTION_REG_bits.PS2
483 #define PSA OPTION_REG_bits.PSA
484 #define T0SE OPTION_REG_bits.T0SE
485 #define T0CS OPTION_REG_bits.T0CS
486 #define INTEDG OPTION_REG_bits.INTEDG
487 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
489 // ----- PCON bits --------------------
492 unsigned char NOT_BO:1;
493 unsigned char NOT_POR:1;
502 unsigned char NOT_BOR:1;
512 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
514 #define NOT_BO PCON_bits.NOT_BO
515 #define NOT_BOR PCON_bits.NOT_BOR
516 #define NOT_POR PCON_bits.NOT_POR
518 // ----- PIE1 bits --------------------
521 unsigned char TMR1IE:1;
522 unsigned char TMR2IE:1;
523 unsigned char CCP1IE:1;
524 unsigned char USBIE:1;
525 unsigned char TXIE:1;
526 unsigned char RCIE:1;
527 unsigned char ADIE:1;
528 unsigned char PSPIE:1;
531 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
533 #define TMR1IE PIE1_bits.TMR1IE
534 #define TMR2IE PIE1_bits.TMR2IE
535 #define CCP1IE PIE1_bits.CCP1IE
536 #define USBIE PIE1_bits.USBIE
537 #define TXIE PIE1_bits.TXIE
538 #define RCIE PIE1_bits.RCIE
539 #define ADIE PIE1_bits.ADIE
540 #define PSPIE PIE1_bits.PSPIE
542 // ----- PIE2 bits --------------------
545 unsigned char CCP2IE:1;
555 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
557 #define CCP2IE PIE2_bits.CCP2IE
559 // ----- PIR1 bits --------------------
562 unsigned char TMR1IF:1;
563 unsigned char TMR2IF:1;
564 unsigned char CCP1IF:1;
565 unsigned char USBIF:1;
566 unsigned char TXIF:1;
567 unsigned char RCIF:1;
568 unsigned char ADIF:1;
569 unsigned char PSPIF:1;
572 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
574 #define TMR1IF PIR1_bits.TMR1IF
575 #define TMR2IF PIR1_bits.TMR2IF
576 #define CCP1IF PIR1_bits.CCP1IF
577 #define USBIF PIR1_bits.USBIF
578 #define TXIF PIR1_bits.TXIF
579 #define RCIF PIR1_bits.RCIF
580 #define ADIF PIR1_bits.ADIF
581 #define PSPIF PIR1_bits.PSPIF
583 // ----- PIR2 bits --------------------
586 unsigned char CCP2IF:1;
596 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
598 #define CCP2IF PIR2_bits.CCP2IF
600 // ----- RCSTA bits --------------------
603 unsigned char RX9D:1;
604 unsigned char OERR:1;
605 unsigned char FERR:1;
607 unsigned char CREN:1;
608 unsigned char SREN:1;
610 unsigned char SPEN:1;
613 unsigned char RCD8:1;
629 unsigned char NOT_RC8:1;
639 unsigned char RC8_9:1;
643 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
645 #define RX9D RCSTA_bits.RX9D
646 #define RCD8 RCSTA_bits.RCD8
647 #define OERR RCSTA_bits.OERR
648 #define FERR RCSTA_bits.FERR
649 #define CREN RCSTA_bits.CREN
650 #define SREN RCSTA_bits.SREN
651 #define RX9 RCSTA_bits.RX9
652 #define RC9 RCSTA_bits.RC9
653 #define NOT_RC8 RCSTA_bits.NOT_RC8
654 #define RC8_9 RCSTA_bits.RC8_9
655 #define SPEN RCSTA_bits.SPEN
657 // ----- STATUS bits --------------------
663 unsigned char NOT_PD:1;
664 unsigned char NOT_TO:1;
670 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
672 #define C STATUS_bits.C
673 #define DC STATUS_bits.DC
674 #define Z STATUS_bits.Z
675 #define NOT_PD STATUS_bits.NOT_PD
676 #define NOT_TO STATUS_bits.NOT_TO
677 #define RP0 STATUS_bits.RP0
678 #define RP1 STATUS_bits.RP1
679 #define IRP STATUS_bits.IRP
681 // ----- T1CON bits --------------------
684 unsigned char TMR1ON:1;
685 unsigned char TMR1CS:1;
686 unsigned char NOT_T1SYNC:1;
687 unsigned char T1OSCEN:1;
688 unsigned char T1CKPS0:1;
689 unsigned char T1CKPS1:1;
696 unsigned char T1INSYNC:1;
704 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
706 #define TMR1ON T1CON_bits.TMR1ON
707 #define TMR1CS T1CON_bits.TMR1CS
708 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
709 #define T1INSYNC T1CON_bits.T1INSYNC
710 #define T1OSCEN T1CON_bits.T1OSCEN
711 #define T1CKPS0 T1CON_bits.T1CKPS0
712 #define T1CKPS1 T1CON_bits.T1CKPS1
714 // ----- T2CON bits --------------------
717 unsigned char T2CKPS0:1;
718 unsigned char T2CKPS1:1;
719 unsigned char TMR2ON:1;
720 unsigned char TOUTPS0:1;
721 unsigned char TOUTPS1:1;
722 unsigned char TOUTPS2:1;
723 unsigned char TOUTPS3:1;
727 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
729 #define T2CKPS0 T2CON_bits.T2CKPS0
730 #define T2CKPS1 T2CON_bits.T2CKPS1
731 #define TMR2ON T2CON_bits.TMR2ON
732 #define TOUTPS0 T2CON_bits.TOUTPS0
733 #define TOUTPS1 T2CON_bits.TOUTPS1
734 #define TOUTPS2 T2CON_bits.TOUTPS2
735 #define TOUTPS3 T2CON_bits.TOUTPS3
737 // ----- TRISE bits --------------------
740 unsigned char TRISE0:1;
741 unsigned char TRISE1:1;
742 unsigned char TRISE2:1;
744 unsigned char PSPMODE:1;
745 unsigned char IBOV:1;
750 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
752 #define TRISE0 TRISE_bits.TRISE0
753 #define TRISE1 TRISE_bits.TRISE1
754 #define TRISE2 TRISE_bits.TRISE2
755 #define PSPMODE TRISE_bits.PSPMODE
756 #define IBOV TRISE_bits.IBOV
757 #define OBF TRISE_bits.OBF
758 #define IBF TRISE_bits.IBF
760 // ----- TXSTA bits --------------------
763 unsigned char TX9D:1;
764 unsigned char TRMT:1;
765 unsigned char BRGH:1;
767 unsigned char SYNC:1;
768 unsigned char TXEN:1;
770 unsigned char CSRC:1;
773 unsigned char TXD8:1;
779 unsigned char NOT_TX8:1;
789 unsigned char TX8_9:1;
793 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
795 #define TX9D TXSTA_bits.TX9D
796 #define TXD8 TXSTA_bits.TXD8
797 #define TRMT TXSTA_bits.TRMT
798 #define BRGH TXSTA_bits.BRGH
799 #define SYNC TXSTA_bits.SYNC
800 #define TXEN TXSTA_bits.TXEN
801 #define TX9 TXSTA_bits.TX9
802 #define NOT_TX8 TXSTA_bits.NOT_TX8
803 #define TX8_9 TXSTA_bits.TX8_9
804 #define CSRC TXSTA_bits.CSRC
806 // ----- UCTRL bits --------------------
810 unsigned char SUSPND:1;
811 unsigned char RESUME:1;
812 unsigned char DEV_ATT:1;
813 unsigned char PKT_DIS:1;
819 extern volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits;
821 #define SUSPND UCTRL_bits.SUSPND
822 #define RESUME UCTRL_bits.RESUME
823 #define DEV_ATT UCTRL_bits.DEV_ATT
824 #define PKT_DIS UCTRL_bits.PKT_DIS
825 #define SE0 UCTRL_bits.SE0
827 // ----- UEIE bits --------------------
830 unsigned char PID_ERR:1;
831 unsigned char CRC5:1;
832 unsigned char CRC16:1;
833 unsigned char DFN8:1;
834 unsigned char BTO_ERR:1;
835 unsigned char WRT_ERR:1;
836 unsigned char OWN_ERR:1;
837 unsigned char BTS_ERR:1;
840 extern volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits;
842 #define PID_ERR UEIE_bits.PID_ERR
843 #define CRC5 UEIE_bits.CRC5
844 #define CRC16 UEIE_bits.CRC16
845 #define DFN8 UEIE_bits.DFN8
846 #define BTO_ERR UEIE_bits.BTO_ERR
847 #define WRT_ERR UEIE_bits.WRT_ERR
848 #define OWN_ERR UEIE_bits.OWN_ERR
849 #define BTS_ERR UEIE_bits.BTS_ERR
851 // ----- UEP2 bits --------------------
854 unsigned char EP_STALL:1;
855 unsigned char EP_IN_EN:1;
856 unsigned char EP_OUT_EN:1;
857 unsigned char EP_CTL_DIS:1;
858 unsigned char PID2:1;
859 unsigned char PID3:1;
860 unsigned char DATA01:1;
861 unsigned char UOWN:1;
866 unsigned char BSTALL:1;
876 unsigned char PID0:1;
877 unsigned char PID1:1;
884 extern volatile __UEP2_bits_t __at(UEP2_ADDR) UEP2_bits;
886 #define EP_STALL UEP2_bits.EP_STALL
887 #define EP_IN_EN UEP2_bits.EP_IN_EN
888 #define EP_OUT_EN UEP2_bits.EP_OUT_EN
889 #define BSTALL UEP2_bits.BSTALL
890 #define PID0 UEP2_bits.PID0
891 #define EP_CTL_DIS UEP2_bits.EP_CTL_DIS
892 #define DTS UEP2_bits.DTS
893 #define PID1 UEP2_bits.PID1
894 #define PID2 UEP2_bits.PID2
895 #define PID3 UEP2_bits.PID3
896 #define DATA01 UEP2_bits.DATA01
897 #define UOWN UEP2_bits.UOWN
898 #define OWN UEP2_bits.OWN
900 // ----- UIE bits --------------------
903 unsigned char USB_RST:1;
904 unsigned char UERR:1;
905 unsigned char ACTIVITY:1;
906 unsigned char TOK_DNE:1;
907 unsigned char UIDLE:1;
908 unsigned char STALL:1;
913 extern volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits;
915 #define USB_RST UIE_bits.USB_RST
916 #define UERR UIE_bits.UERR
917 #define ACTIVITY UIE_bits.ACTIVITY
918 #define TOK_DNE UIE_bits.TOK_DNE
919 #define UIDLE UIE_bits.UIDLE
920 #define STALL UIE_bits.STALL
922 // ----- USTAT bits --------------------
928 unsigned char ENDP0:1;
929 unsigned char ENDP1:1;
935 extern volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits;
937 #define IN USTAT_bits.IN
938 #define ENDP0 USTAT_bits.ENDP0
939 #define ENDP1 USTAT_bits.ENDP1