2 // Register Declarations for Microchip 16C74B Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define ADRES_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define TRISD_ADDR 0x0088
65 #define TRISE_ADDR 0x0089
66 #define PIE1_ADDR 0x008C
67 #define PIE2_ADDR 0x008D
68 #define PCON_ADDR 0x008E
69 #define PR2_ADDR 0x0092
70 #define SSPADD_ADDR 0x0093
71 #define SSPSTAT_ADDR 0x0094
72 #define TXSTA_ADDR 0x0098
73 #define SPBRG_ADDR 0x0099
74 #define ADCON1_ADDR 0x009F
77 // Memory organization.
80 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
81 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
82 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
83 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
84 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
85 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
86 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
87 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
88 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
89 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
90 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
91 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
92 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
93 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
94 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
95 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
96 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
97 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
98 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
99 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
100 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
101 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
102 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
103 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
104 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
105 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
106 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
107 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
108 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
109 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
110 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
111 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
112 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
113 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
114 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
115 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
116 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
117 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
118 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
119 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
120 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
121 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
122 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
123 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
124 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
125 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
126 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
130 // P16C74B.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
133 // This header file defines configurations, registers, and other useful bits of
134 // information for the PIC16C74B microcontroller. These names are taken to match
135 // the data sheets as closely as possible.
137 // Note that the processor must be selected before this file is
138 // included. The processor may be selected the following ways:
140 // 1. Command line switch:
141 // C:\ MPASM MYFILE.ASM /PIC16C74B
142 // 2. LIST directive in the source file
144 // 3. Processor Type entry in the MPASM full-screen interface
146 //==========================================================================
150 //==========================================================================
154 //1.00 12/17/97 Initial Release
156 //==========================================================================
160 //==========================================================================
163 // MESSG "Processor-header file mismatch. Verify selected processor."
166 //==========================================================================
168 // Register Definitions
170 //==========================================================================
175 //----- Register Files------------------------------------------------------
177 extern data __at (INDF_ADDR) volatile char INDF;
178 extern sfr __at (TMR0_ADDR) TMR0;
179 extern data __at (PCL_ADDR) volatile char PCL;
180 extern sfr __at (STATUS_ADDR) STATUS;
181 extern sfr __at (FSR_ADDR) FSR;
182 extern sfr __at (PORTA_ADDR) PORTA;
183 extern sfr __at (PORTB_ADDR) PORTB;
184 extern sfr __at (PORTC_ADDR) PORTC;
185 extern sfr __at (PORTD_ADDR) PORTD;
186 extern sfr __at (PORTE_ADDR) PORTE;
187 extern sfr __at (PCLATH_ADDR) PCLATH;
188 extern sfr __at (INTCON_ADDR) INTCON;
189 extern sfr __at (PIR1_ADDR) PIR1;
190 extern sfr __at (PIR2_ADDR) PIR2;
191 extern sfr __at (TMR1L_ADDR) TMR1L;
192 extern sfr __at (TMR1H_ADDR) TMR1H;
193 extern sfr __at (T1CON_ADDR) T1CON;
194 extern sfr __at (TMR2_ADDR) TMR2;
195 extern sfr __at (T2CON_ADDR) T2CON;
196 extern sfr __at (SSPBUF_ADDR) SSPBUF;
197 extern sfr __at (SSPCON_ADDR) SSPCON;
198 extern sfr __at (CCPR1L_ADDR) CCPR1L;
199 extern sfr __at (CCPR1H_ADDR) CCPR1H;
200 extern sfr __at (CCP1CON_ADDR) CCP1CON;
201 extern sfr __at (RCSTA_ADDR) RCSTA;
202 extern sfr __at (TXREG_ADDR) TXREG;
203 extern sfr __at (RCREG_ADDR) RCREG;
204 extern sfr __at (CCPR2L_ADDR) CCPR2L;
205 extern sfr __at (CCPR2H_ADDR) CCPR2H;
206 extern sfr __at (CCP2CON_ADDR) CCP2CON;
207 extern sfr __at (ADRES_ADDR) ADRES;
208 extern sfr __at (ADCON0_ADDR) ADCON0;
210 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
211 extern sfr __at (TRISA_ADDR) TRISA;
212 extern sfr __at (TRISB_ADDR) TRISB;
213 extern sfr __at (TRISC_ADDR) TRISC;
214 extern sfr __at (TRISD_ADDR) TRISD;
215 extern sfr __at (TRISE_ADDR) TRISE;
216 extern sfr __at (PIE1_ADDR) PIE1;
217 extern sfr __at (PIE2_ADDR) PIE2;
218 extern sfr __at (PCON_ADDR) PCON;
219 extern sfr __at (PR2_ADDR) PR2;
220 extern sfr __at (SSPADD_ADDR) SSPADD;
221 extern sfr __at (SSPSTAT_ADDR) SSPSTAT;
222 extern sfr __at (TXSTA_ADDR) TXSTA;
223 extern sfr __at (SPBRG_ADDR) SPBRG;
224 extern sfr __at (ADCON1_ADDR) ADCON1;
226 //----- STATUS Bits --------------------------------------------------------
229 //----- INTCON Bits --------------------------------------------------------
232 //----- PIR1 Bits ----------------------------------------------------------
235 //----- PIR2 Bits ----------------------------------------------------------
238 //----- T1CON Bits ---------------------------------------------------------
241 //----- T2CON Bits ---------------------------------------------------------
244 //----- SSPCON Bits --------------------------------------------------------
247 //----- CCP1CON Bits -------------------------------------------------------
250 //----- RCSTA Bits ---------------------------------------------------------
253 //----- CCP2CON Bits -------------------------------------------------------
256 //----- ADCON0 Bits --------------------------------------------------------
259 //----- OPTION Bits --------------------------------------------------------
262 //----- TRISE Bits ---------------------------------------------------------
265 //----- PIE1 Bits ----------------------------------------------------------
268 //----- PIE2 Bits ----------------------------------------------------------
271 //----- PCON Bits ----------------------------------------------------------
274 //----- SSPSTAT Bits -------------------------------------------------------
277 //----- TXSTA Bits ---------------------------------------------------------
280 //----- ADCON1 Bits --------------------------------------------------------
283 //==========================================================================
287 //==========================================================================
290 // __BADRAM H'8F'-H'91', H'95'-H'97', H'9A'-H'9E'
292 //==========================================================================
294 // Configuration Bits
296 //==========================================================================
298 #define _BODEN_ON 0x3FFF
299 #define _BODEN_OFF 0x3FBF
300 #define _CP_ALL 0x00CF
301 #define _CP_75 0x15DF
302 #define _CP_50 0x2AEF
303 #define _CP_OFF 0x3FFF
304 #define _PWRTE_OFF 0x3FFF
305 #define _PWRTE_ON 0x3FF7
306 #define _WDT_ON 0x3FFF
307 #define _WDT_OFF 0x3FFB
308 #define _LP_OSC 0x3FFC
309 #define _XT_OSC 0x3FFD
310 #define _HS_OSC 0x3FFE
311 #define _RC_OSC 0x3FFF
315 // ----- ADCON0 bits --------------------
318 unsigned char ADON:1;
321 unsigned char CHS0:1;
322 unsigned char CHS1:1;
323 unsigned char CHS2:1;
324 unsigned char ADCS0:1;
325 unsigned char ADCS1:1;
330 unsigned char NOT_DONE:1;
340 unsigned char GO_DONE:1;
348 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
350 #define ADON ADCON0_bits.ADON
351 #define GO ADCON0_bits.GO
352 #define NOT_DONE ADCON0_bits.NOT_DONE
353 #define GO_DONE ADCON0_bits.GO_DONE
354 #define CHS0 ADCON0_bits.CHS0
355 #define CHS1 ADCON0_bits.CHS1
356 #define CHS2 ADCON0_bits.CHS2
357 #define ADCS0 ADCON0_bits.ADCS0
358 #define ADCS1 ADCON0_bits.ADCS1
360 // ----- ADCON1 bits --------------------
363 unsigned char PCFG0:1;
364 unsigned char PCFG1:1;
365 unsigned char PCFG2:1;
373 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
375 #define PCFG0 ADCON1_bits.PCFG0
376 #define PCFG1 ADCON1_bits.PCFG1
377 #define PCFG2 ADCON1_bits.PCFG2
379 // ----- CCP1CON bits --------------------
382 unsigned char CCP1M0:1;
383 unsigned char CCP1M1:1;
384 unsigned char CCP1M2:1;
385 unsigned char CCP1M3:1;
386 unsigned char CCP1Y:1;
387 unsigned char CCP1X:1;
392 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
394 #define CCP1M0 CCP1CON_bits.CCP1M0
395 #define CCP1M1 CCP1CON_bits.CCP1M1
396 #define CCP1M2 CCP1CON_bits.CCP1M2
397 #define CCP1M3 CCP1CON_bits.CCP1M3
398 #define CCP1Y CCP1CON_bits.CCP1Y
399 #define CCP1X CCP1CON_bits.CCP1X
401 // ----- CCP2CON bits --------------------
404 unsigned char CCP2M0:1;
405 unsigned char CCP2M1:1;
406 unsigned char CCP2M2:1;
407 unsigned char CCP2M3:1;
408 unsigned char CCP2Y:1;
409 unsigned char CCP2X:1;
414 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
416 #define CCP2M0 CCP2CON_bits.CCP2M0
417 #define CCP2M1 CCP2CON_bits.CCP2M1
418 #define CCP2M2 CCP2CON_bits.CCP2M2
419 #define CCP2M3 CCP2CON_bits.CCP2M3
420 #define CCP2Y CCP2CON_bits.CCP2Y
421 #define CCP2X CCP2CON_bits.CCP2X
423 // ----- INTCON bits --------------------
426 unsigned char RBIF:1;
427 unsigned char INTF:1;
428 unsigned char T0IF:1;
429 unsigned char RBIE:1;
430 unsigned char INTE:1;
431 unsigned char T0IE:1;
432 unsigned char PEIE:1;
436 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
438 #define RBIF INTCON_bits.RBIF
439 #define INTF INTCON_bits.INTF
440 #define T0IF INTCON_bits.T0IF
441 #define RBIE INTCON_bits.RBIE
442 #define INTE INTCON_bits.INTE
443 #define T0IE INTCON_bits.T0IE
444 #define PEIE INTCON_bits.PEIE
445 #define GIE INTCON_bits.GIE
447 // ----- OPTION_REG bits --------------------
454 unsigned char T0SE:1;
455 unsigned char T0CS:1;
456 unsigned char INTEDG:1;
457 unsigned char NOT_RBPU:1;
459 } __OPTION_REG_bits_t;
460 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
462 #define PS0 OPTION_REG_bits.PS0
463 #define PS1 OPTION_REG_bits.PS1
464 #define PS2 OPTION_REG_bits.PS2
465 #define PSA OPTION_REG_bits.PSA
466 #define T0SE OPTION_REG_bits.T0SE
467 #define T0CS OPTION_REG_bits.T0CS
468 #define INTEDG OPTION_REG_bits.INTEDG
469 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
471 // ----- PCON bits --------------------
474 unsigned char NOT_BO:1;
475 unsigned char NOT_POR:1;
484 unsigned char NOT_BOR:1;
494 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
496 #define NOT_BO PCON_bits.NOT_BO
497 #define NOT_BOR PCON_bits.NOT_BOR
498 #define NOT_POR PCON_bits.NOT_POR
500 // ----- PIE1 bits --------------------
503 unsigned char TMR1IE:1;
504 unsigned char TMR2IE:1;
505 unsigned char CCP1IE:1;
506 unsigned char SSPIE:1;
507 unsigned char TXIE:1;
508 unsigned char RCIE:1;
509 unsigned char ADIE:1;
510 unsigned char PSPIE:1;
513 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
515 #define TMR1IE PIE1_bits.TMR1IE
516 #define TMR2IE PIE1_bits.TMR2IE
517 #define CCP1IE PIE1_bits.CCP1IE
518 #define SSPIE PIE1_bits.SSPIE
519 #define TXIE PIE1_bits.TXIE
520 #define RCIE PIE1_bits.RCIE
521 #define ADIE PIE1_bits.ADIE
522 #define PSPIE PIE1_bits.PSPIE
524 // ----- PIE2 bits --------------------
527 unsigned char CCP2IE:1;
537 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
539 #define CCP2IE PIE2_bits.CCP2IE
541 // ----- PIR1 bits --------------------
544 unsigned char TMR1IF:1;
545 unsigned char TMR2IF:1;
546 unsigned char CCP1IF:1;
547 unsigned char SSPIF:1;
548 unsigned char TXIF:1;
549 unsigned char RCIF:1;
550 unsigned char ADIF:1;
551 unsigned char PSPIF:1;
554 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
556 #define TMR1IF PIR1_bits.TMR1IF
557 #define TMR2IF PIR1_bits.TMR2IF
558 #define CCP1IF PIR1_bits.CCP1IF
559 #define SSPIF PIR1_bits.SSPIF
560 #define TXIF PIR1_bits.TXIF
561 #define RCIF PIR1_bits.RCIF
562 #define ADIF PIR1_bits.ADIF
563 #define PSPIF PIR1_bits.PSPIF
565 // ----- PIR2 bits --------------------
568 unsigned char CCP2IF:1;
578 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
580 #define CCP2IF PIR2_bits.CCP2IF
582 // ----- RCSTA bits --------------------
585 unsigned char RX9D:1;
586 unsigned char OERR:1;
587 unsigned char FERR:1;
589 unsigned char CREN:1;
590 unsigned char SREN:1;
592 unsigned char SPEN:1;
595 unsigned char RCD8:1;
611 unsigned char NOT_RC8:1;
621 unsigned char RC8_9:1;
625 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
627 #define RX9D RCSTA_bits.RX9D
628 #define RCD8 RCSTA_bits.RCD8
629 #define OERR RCSTA_bits.OERR
630 #define FERR RCSTA_bits.FERR
631 #define CREN RCSTA_bits.CREN
632 #define SREN RCSTA_bits.SREN
633 #define RX9 RCSTA_bits.RX9
634 #define RC9 RCSTA_bits.RC9
635 #define NOT_RC8 RCSTA_bits.NOT_RC8
636 #define RC8_9 RCSTA_bits.RC8_9
637 #define SPEN RCSTA_bits.SPEN
639 // ----- SSPCON bits --------------------
642 unsigned char SSPM0:1;
643 unsigned char SSPM1:1;
644 unsigned char SSPM2:1;
645 unsigned char SSPM3:1;
647 unsigned char SSPEN:1;
648 unsigned char SSPOV:1;
649 unsigned char WCOL:1;
652 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
654 #define SSPM0 SSPCON_bits.SSPM0
655 #define SSPM1 SSPCON_bits.SSPM1
656 #define SSPM2 SSPCON_bits.SSPM2
657 #define SSPM3 SSPCON_bits.SSPM3
658 #define CKP SSPCON_bits.CKP
659 #define SSPEN SSPCON_bits.SSPEN
660 #define SSPOV SSPCON_bits.SSPOV
661 #define WCOL SSPCON_bits.WCOL
663 // ----- SSPSTAT bits --------------------
678 unsigned char I2C_READ:1;
679 unsigned char I2C_START:1;
680 unsigned char I2C_STOP:1;
681 unsigned char I2C_DATA:1;
688 unsigned char NOT_W:1;
691 unsigned char NOT_A:1;
698 unsigned char NOT_WRITE:1;
701 unsigned char NOT_ADDRESS:1;
718 unsigned char READ_WRITE:1;
721 unsigned char DATA_ADDRESS:1;
726 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
728 #define BF SSPSTAT_bits.BF
729 #define UA SSPSTAT_bits.UA
730 #define R SSPSTAT_bits.R
731 #define I2C_READ SSPSTAT_bits.I2C_READ
732 #define NOT_W SSPSTAT_bits.NOT_W
733 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
734 #define R_W SSPSTAT_bits.R_W
735 #define READ_WRITE SSPSTAT_bits.READ_WRITE
736 #define S SSPSTAT_bits.S
737 #define I2C_START SSPSTAT_bits.I2C_START
738 #define P SSPSTAT_bits.P
739 #define I2C_STOP SSPSTAT_bits.I2C_STOP
740 #define D SSPSTAT_bits.D
741 #define I2C_DATA SSPSTAT_bits.I2C_DATA
742 #define NOT_A SSPSTAT_bits.NOT_A
743 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
744 #define D_A SSPSTAT_bits.D_A
745 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
746 #define CKE SSPSTAT_bits.CKE
747 #define SMP SSPSTAT_bits.SMP
749 // ----- STATUS bits --------------------
755 unsigned char NOT_PD:1;
756 unsigned char NOT_TO:1;
762 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
764 #define C STATUS_bits.C
765 #define DC STATUS_bits.DC
766 #define Z STATUS_bits.Z
767 #define NOT_PD STATUS_bits.NOT_PD
768 #define NOT_TO STATUS_bits.NOT_TO
769 #define RP0 STATUS_bits.RP0
770 #define RP1 STATUS_bits.RP1
771 #define IRP STATUS_bits.IRP
773 // ----- T1CON bits --------------------
776 unsigned char TMR1ON:1;
777 unsigned char TMR1CS:1;
778 unsigned char NOT_T1SYNC:1;
779 unsigned char T1OSCEN:1;
780 unsigned char T1CKPS0:1;
781 unsigned char T1CKPS1:1;
788 unsigned char T1INSYNC:1;
796 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
798 #define TMR1ON T1CON_bits.TMR1ON
799 #define TMR1CS T1CON_bits.TMR1CS
800 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
801 #define T1INSYNC T1CON_bits.T1INSYNC
802 #define T1OSCEN T1CON_bits.T1OSCEN
803 #define T1CKPS0 T1CON_bits.T1CKPS0
804 #define T1CKPS1 T1CON_bits.T1CKPS1
806 // ----- T2CON bits --------------------
809 unsigned char T2CKPS0:1;
810 unsigned char T2CKPS1:1;
811 unsigned char TMR2ON:1;
812 unsigned char TOUTPS0:1;
813 unsigned char TOUTPS1:1;
814 unsigned char TOUTPS2:1;
815 unsigned char TOUTPS3:1;
819 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
821 #define T2CKPS0 T2CON_bits.T2CKPS0
822 #define T2CKPS1 T2CON_bits.T2CKPS1
823 #define TMR2ON T2CON_bits.TMR2ON
824 #define TOUTPS0 T2CON_bits.TOUTPS0
825 #define TOUTPS1 T2CON_bits.TOUTPS1
826 #define TOUTPS2 T2CON_bits.TOUTPS2
827 #define TOUTPS3 T2CON_bits.TOUTPS3
829 // ----- TRISE bits --------------------
832 unsigned char TRISE0:1;
833 unsigned char TRISE1:1;
834 unsigned char TRISE2:1;
836 unsigned char PSPMODE:1;
837 unsigned char IBOV:1;
842 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
844 #define TRISE0 TRISE_bits.TRISE0
845 #define TRISE1 TRISE_bits.TRISE1
846 #define TRISE2 TRISE_bits.TRISE2
847 #define PSPMODE TRISE_bits.PSPMODE
848 #define IBOV TRISE_bits.IBOV
849 #define OBF TRISE_bits.OBF
850 #define IBF TRISE_bits.IBF
852 // ----- TXSTA bits --------------------
855 unsigned char TX9D:1;
856 unsigned char TRMT:1;
857 unsigned char BRGH:1;
859 unsigned char SYNC:1;
860 unsigned char TXEN:1;
862 unsigned char CSRC:1;
865 unsigned char TXD8:1;
871 unsigned char NOT_TX8:1;
881 unsigned char TX8_9:1;
885 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
887 #define TX9D TXSTA_bits.TX9D
888 #define TXD8 TXSTA_bits.TXD8
889 #define TRMT TXSTA_bits.TRMT
890 #define BRGH TXSTA_bits.BRGH
891 #define SYNC TXSTA_bits.SYNC
892 #define TXEN TXSTA_bits.TXEN
893 #define TX9 TXSTA_bits.TX9
894 #define NOT_TX8 TXSTA_bits.NOT_TX8
895 #define TX8_9 TXSTA_bits.TX8_9
896 #define CSRC TXSTA_bits.CSRC