2 // Register Declarations for Microchip 16C745 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define CCPR1L_ADDR 0x0015
46 #define CCPR1H_ADDR 0x0016
47 #define CCP1CON_ADDR 0x0017
48 #define RCSTA_ADDR 0x0018
49 #define TXREG_ADDR 0x0019
50 #define RCREG_ADDR 0x001A
51 #define CCPR2L_ADDR 0x001B
52 #define CCPR2H_ADDR 0x001C
53 #define CCP2CON_ADDR 0x001D
54 #define ADRES_ADDR 0x001E
55 #define ADCON0_ADDR 0x001F
56 #define OPTION_REG_ADDR 0x0081
57 #define TRISA_ADDR 0x0085
58 #define TRISB_ADDR 0x0086
59 #define TRISC_ADDR 0x0087
60 #define PIE1_ADDR 0x008C
61 #define PIE2_ADDR 0x008D
62 #define PCON_ADDR 0x008E
63 #define PR2_ADDR 0x0092
64 #define TXSTA_ADDR 0x0098
65 #define SPBRG_ADDR 0x0099
66 #define ADCON1_ADDR 0x009F
67 #define UIR_ADDR 0x0190
68 #define UIE_ADDR 0x0191
69 #define UEIR_ADDR 0x0192
70 #define UEIE_ADDR 0x0193
71 #define USTAT_ADDR 0x0194
72 #define UCTRL_ADDR 0x0195
73 #define UADDR_ADDR 0x0196
74 #define USWSTAT_ADDR 0x0197
75 #define UEP0_ADDR 0x0198
76 #define UEP1_ADDR 0x0199
77 #define UEP2_ADDR 0x019A
78 #define BD0OST_ADDR 0x01A0
79 #define BD0OBC_ADDR 0x01A1
80 #define BD0OAL_ADDR 0x01A2
81 #define BD0IST_ADDR 0x01A4
82 #define BD0IBC_ADDR 0x01A5
83 #define BD0IAL_ADDR 0x01A6
84 #define BD1OST_ADDR 0x01A8
85 #define BD1OBC_ADDR 0x01A9
86 #define BD1OAL_ADDR 0x01AA
87 #define BD1IST_ADDR 0x01AC
88 #define BD1IBC_ADDR 0x01AD
89 #define BD1IAL_ADDR 0x01AE
90 #define BD2OST_ADDR 0x01B0
91 #define BD2OBC_ADDR 0x01B1
92 #define BD2OAL_ADDR 0x01B2
93 #define BD2IST_ADDR 0x01B4
94 #define BD2IBC_ADDR 0x01B5
95 #define BD2IAL_ADDR 0x01B6
98 // Memory organization.
101 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
102 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
103 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
104 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
105 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
106 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
107 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
108 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
109 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
110 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
111 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
112 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
113 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
114 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
115 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
116 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
117 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
118 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
119 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
120 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
121 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
122 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
123 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
124 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
125 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
126 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
127 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
128 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
129 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
130 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
131 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
132 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
133 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
134 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
135 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
136 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
137 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
138 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
139 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
140 #pragma memmap UIR_ADDR UIR_ADDR SFR 0x000 // UIR
141 #pragma memmap UIE_ADDR UIE_ADDR SFR 0x000 // UIE
142 #pragma memmap UEIR_ADDR UEIR_ADDR SFR 0x000 // UEIR
143 #pragma memmap UEIE_ADDR UEIE_ADDR SFR 0x000 // UEIE
144 #pragma memmap USTAT_ADDR USTAT_ADDR SFR 0x000 // USTAT
145 #pragma memmap UCTRL_ADDR UCTRL_ADDR SFR 0x000 // UCTRL
146 #pragma memmap UADDR_ADDR UADDR_ADDR SFR 0x000 // UADDR
147 #pragma memmap USWSTAT_ADDR USWSTAT_ADDR SFR 0x000 // USWSTAT
148 #pragma memmap UEP0_ADDR UEP0_ADDR SFR 0x000 // UEP0
149 #pragma memmap UEP1_ADDR UEP1_ADDR SFR 0x000 // UEP1
150 #pragma memmap UEP2_ADDR UEP2_ADDR SFR 0x000 // UEP2
151 #pragma memmap BD0OST_ADDR BD0OST_ADDR SFR 0x000 // BD0OST
152 #pragma memmap BD0OBC_ADDR BD0OBC_ADDR SFR 0x000 // BD0OBC
153 #pragma memmap BD0OAL_ADDR BD0OAL_ADDR SFR 0x000 // BD0OAL
154 #pragma memmap BD0IST_ADDR BD0IST_ADDR SFR 0x000 // BD0IST
155 #pragma memmap BD0IBC_ADDR BD0IBC_ADDR SFR 0x000 // BD0IBC
156 #pragma memmap BD0IAL_ADDR BD0IAL_ADDR SFR 0x000 // BD0IAL
157 #pragma memmap BD1OST_ADDR BD1OST_ADDR SFR 0x000 // BD1OST
158 #pragma memmap BD1OBC_ADDR BD1OBC_ADDR SFR 0x000 // BD1OBC
159 #pragma memmap BD1OAL_ADDR BD1OAL_ADDR SFR 0x000 // BD1OAL
160 #pragma memmap BD1IST_ADDR BD1IST_ADDR SFR 0x000 // BD1IST
161 #pragma memmap BD1IBC_ADDR BD1IBC_ADDR SFR 0x000 // BD1IBC
162 #pragma memmap BD1IAL_ADDR BD1IAL_ADDR SFR 0x000 // BD1IAL
163 #pragma memmap BD2OST_ADDR BD2OST_ADDR SFR 0x000 // BD2OST
164 #pragma memmap BD2OBC_ADDR BD2OBC_ADDR SFR 0x000 // BD2OBC
165 #pragma memmap BD2OAL_ADDR BD2OAL_ADDR SFR 0x000 // BD2OAL
166 #pragma memmap BD2IST_ADDR BD2IST_ADDR SFR 0x000 // BD2IST
167 #pragma memmap BD2IBC_ADDR BD2IBC_ADDR SFR 0x000 // BD2IBC
168 #pragma memmap BD2IAL_ADDR BD2IAL_ADDR SFR 0x000 // BD2IAL
172 // P16C745.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
175 // This header file defines configurations, registers, and other useful bits of
176 // information for the PIC16C745 microcontroller. These names are taken to match
177 // the data sheets as closely as possible.
179 // Note that the processor must be selected before this file is
180 // included. The processor may be selected the following ways:
182 // 1. Command line switch:
183 // C:\ MPASM MYFILE.ASM /PIC16C745
184 // 2. LIST directive in the source file
186 // 3. Processor Type entry in the MPASM full-screen interface
188 //==========================================================================
192 //==========================================================================
196 //1.00 28 Sep 99 Initial Release
198 //==========================================================================
202 //==========================================================================
205 // MESSG "Processor-header file mismatch. Verify selected processor."
208 //==========================================================================
210 // Register Definitions
212 //==========================================================================
217 //----- Register Files------------------------------------------------------
219 extern data __at (INDF_ADDR) volatile char INDF;
220 extern sfr __at (TMR0_ADDR) TMR0;
221 extern data __at (PCL_ADDR) volatile char PCL;
222 extern sfr __at (STATUS_ADDR) STATUS;
223 extern sfr __at (FSR_ADDR) FSR;
224 extern sfr __at (PORTA_ADDR) PORTA;
225 extern sfr __at (PORTB_ADDR) PORTB;
226 extern sfr __at (PORTC_ADDR) PORTC;
227 extern sfr __at (PCLATH_ADDR) PCLATH;
228 extern sfr __at (INTCON_ADDR) INTCON;
229 extern sfr __at (PIR1_ADDR) PIR1;
230 extern sfr __at (PIR2_ADDR) PIR2;
231 extern sfr __at (TMR1L_ADDR) TMR1L;
232 extern sfr __at (TMR1H_ADDR) TMR1H;
233 extern sfr __at (T1CON_ADDR) T1CON;
234 extern sfr __at (TMR2_ADDR) TMR2;
235 extern sfr __at (T2CON_ADDR) T2CON;
236 extern sfr __at (CCPR1L_ADDR) CCPR1L;
237 extern sfr __at (CCPR1H_ADDR) CCPR1H;
238 extern sfr __at (CCP1CON_ADDR) CCP1CON;
239 extern sfr __at (RCSTA_ADDR) RCSTA;
240 extern sfr __at (TXREG_ADDR) TXREG;
241 extern sfr __at (RCREG_ADDR) RCREG;
242 extern sfr __at (CCPR2L_ADDR) CCPR2L;
243 extern sfr __at (CCPR2H_ADDR) CCPR2H;
244 extern sfr __at (CCP2CON_ADDR) CCP2CON;
245 extern sfr __at (ADRES_ADDR) ADRES;
246 extern sfr __at (ADCON0_ADDR) ADCON0;
248 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
249 extern sfr __at (TRISA_ADDR) TRISA;
250 extern sfr __at (TRISB_ADDR) TRISB;
251 extern sfr __at (TRISC_ADDR) TRISC;
252 extern sfr __at (PIE1_ADDR) PIE1;
253 extern sfr __at (PIE2_ADDR) PIE2;
254 extern sfr __at (PCON_ADDR) PCON;
255 extern sfr __at (PR2_ADDR) PR2;
256 extern sfr __at (TXSTA_ADDR) TXSTA;
257 extern sfr __at (SPBRG_ADDR) SPBRG;
258 extern sfr __at (ADCON1_ADDR) ADCON1;
259 extern sfr __at (UIR_ADDR) UIR;
260 extern sfr __at (UIE_ADDR) UIE;
261 extern sfr __at (UEIR_ADDR) UEIR;
262 extern sfr __at (UEIE_ADDR) UEIE;
263 extern sfr __at (USTAT_ADDR) USTAT;
264 extern sfr __at (UCTRL_ADDR) UCTRL;
265 extern sfr __at (UADDR_ADDR) UADDR;
266 extern sfr __at (USWSTAT_ADDR) USWSTAT;
267 extern sfr __at (UEP0_ADDR) UEP0;
268 extern sfr __at (UEP1_ADDR) UEP1;
269 extern sfr __at (UEP2_ADDR) UEP2;
271 extern sfr __at (BD0OST_ADDR) BD0OST;
272 extern sfr __at (BD0OBC_ADDR) BD0OBC;
273 extern sfr __at (BD0OAL_ADDR) BD0OAL;
274 extern sfr __at (BD0IST_ADDR) BD0IST;
275 extern sfr __at (BD0IBC_ADDR) BD0IBC;
276 extern sfr __at (BD0IAL_ADDR) BD0IAL;
278 extern sfr __at (BD1OST_ADDR) BD1OST;
279 extern sfr __at (BD1OBC_ADDR) BD1OBC;
280 extern sfr __at (BD1OAL_ADDR) BD1OAL;
281 extern sfr __at (BD1IST_ADDR) BD1IST;
282 extern sfr __at (BD1IBC_ADDR) BD1IBC;
283 extern sfr __at (BD1IAL_ADDR) BD1IAL;
285 extern sfr __at (BD2OST_ADDR) BD2OST;
286 extern sfr __at (BD2OBC_ADDR) BD2OBC;
287 extern sfr __at (BD2OAL_ADDR) BD2OAL;
288 extern sfr __at (BD2IST_ADDR) BD2IST;
289 extern sfr __at (BD2IBC_ADDR) BD2IBC;
290 extern sfr __at (BD2IAL_ADDR) BD2IAL;
293 //----- STATUS Bits --------------------------------------------------------
296 //----- INTCON Bits --------------------------------------------------------
299 //----- PIR1 Bits ----------------------------------------------------------
302 //----- PIR2 Bits ----------------------------------------------------------
305 //----- T1CON Bits ---------------------------------------------------------
308 //----- T2CON Bits ---------------------------------------------------------
311 //----- CCP1CON Bits -------------------------------------------------------
314 //----- RCSTA Bits ---------------------------------------------------------
317 //----- CCP2CON Bits -------------------------------------------------------
320 //----- ADCON0 Bits --------------------------------------------------------
323 //----- OPTION Bits --------------------------------------------------------
327 //----- PIE1 Bits ----------------------------------------------------------
330 //----- PIE2 Bits ----------------------------------------------------------
333 //----- PCON Bits ----------------------------------------------------------
336 //----- TXSTA Bits ---------------------------------------------------------
339 //----- ADCON1 Bits --------------------------------------------------------
342 //----- UIR/UIE Bits -----------------------------------------------------
345 //----- UEIR/UEIE Bits -----------------------------------------------------
348 //----- USTAT Bits ---------------------------------------------------------
351 //----- UCTRL Bits ---------------------------------------------------------
353 //----- UEP0/UEP1/UEP2 Bits ------------------------------------------------
356 //----- Buffer descriptor Bits ---------------------------------------------
358 //==========================================================================
362 //==========================================================================
365 // __BADRAM H'8', H'9', H'13', H'14', H'88', H'89', H'8F'-H'91'
366 // __BADRAM H'93'-H'97', H'9A'-H'9E'
367 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F'
368 // __BADRAM H'185', H'187'-H'189', H'18C'-H'18F', H'19B'-H'19F'
369 // __BADRAM H'1E0'-H'1EF'
370 //==========================================================================
372 // Configuration Bits
374 //==========================================================================
376 #define _CP_ALL 0x00CF
377 #define _CP_75 0x15DF
378 #define _CP_50 0x2AEF
379 #define _CP_OFF 0x3FFF
380 #define _PWRTE_OFF 0x3FFF
381 #define _PWRTE_ON 0x3FF7
382 #define _WDT_ON 0x3FFF
383 #define _WDT_OFF 0x3FFB
384 #define _HS_OSC 0x3FFC
385 #define _EC_OSC 0x3FFD
386 #define _H4_OSC 0x3FFE
387 #define _E4_OSC 0x3FFF
391 // ----- ADCON0 bits --------------------
394 unsigned char ADON:1;
397 unsigned char CHS0:1;
398 unsigned char CHS1:1;
399 unsigned char CHS2:1;
400 unsigned char ADCS0:1;
401 unsigned char ADCS1:1;
406 unsigned char NOT_DONE:1;
416 unsigned char GO_DONE:1;
424 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
426 #define ADON ADCON0_bits.ADON
427 #define GO ADCON0_bits.GO
428 #define NOT_DONE ADCON0_bits.NOT_DONE
429 #define GO_DONE ADCON0_bits.GO_DONE
430 #define CHS0 ADCON0_bits.CHS0
431 #define CHS1 ADCON0_bits.CHS1
432 #define CHS2 ADCON0_bits.CHS2
433 #define ADCS0 ADCON0_bits.ADCS0
434 #define ADCS1 ADCON0_bits.ADCS1
436 // ----- ADCON1 bits --------------------
439 unsigned char PCFG0:1;
440 unsigned char PCFG1:1;
441 unsigned char PCFG2:1;
449 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
451 #define PCFG0 ADCON1_bits.PCFG0
452 #define PCFG1 ADCON1_bits.PCFG1
453 #define PCFG2 ADCON1_bits.PCFG2
455 // ----- CCP1CON bits --------------------
458 unsigned char CCP1M0:1;
459 unsigned char CCP1M1:1;
460 unsigned char CCP1M2:1;
461 unsigned char CCP1M3:1;
462 unsigned char DC1B0:1;
463 unsigned char DC1B1:1;
468 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
470 #define CCP1M0 CCP1CON_bits.CCP1M0
471 #define CCP1M1 CCP1CON_bits.CCP1M1
472 #define CCP1M2 CCP1CON_bits.CCP1M2
473 #define CCP1M3 CCP1CON_bits.CCP1M3
474 #define DC1B0 CCP1CON_bits.DC1B0
475 #define DC1B1 CCP1CON_bits.DC1B1
477 // ----- CCP2CON bits --------------------
480 unsigned char CCP2M0:1;
481 unsigned char CCP2M1:1;
482 unsigned char CCP2M2:1;
483 unsigned char CCP2M3:1;
484 unsigned char DC2B0:1;
485 unsigned char DC2B1:1;
490 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
492 #define CCP2M0 CCP2CON_bits.CCP2M0
493 #define CCP2M1 CCP2CON_bits.CCP2M1
494 #define CCP2M2 CCP2CON_bits.CCP2M2
495 #define CCP2M3 CCP2CON_bits.CCP2M3
496 #define DC2B0 CCP2CON_bits.DC2B0
497 #define DC2B1 CCP2CON_bits.DC2B1
499 // ----- INTCON bits --------------------
502 unsigned char RBIF:1;
503 unsigned char INTF:1;
504 unsigned char T0IF:1;
505 unsigned char RBIE:1;
506 unsigned char INTE:1;
507 unsigned char T0IE:1;
508 unsigned char PEIE:1;
512 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
514 #define RBIF INTCON_bits.RBIF
515 #define INTF INTCON_bits.INTF
516 #define T0IF INTCON_bits.T0IF
517 #define RBIE INTCON_bits.RBIE
518 #define INTE INTCON_bits.INTE
519 #define T0IE INTCON_bits.T0IE
520 #define PEIE INTCON_bits.PEIE
521 #define GIE INTCON_bits.GIE
523 // ----- OPTION_REG bits --------------------
530 unsigned char T0SE:1;
531 unsigned char T0CS:1;
532 unsigned char INTEDG:1;
533 unsigned char NOT_RBPU:1;
535 } __OPTION_REG_bits_t;
536 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
538 #define PS0 OPTION_REG_bits.PS0
539 #define PS1 OPTION_REG_bits.PS1
540 #define PS2 OPTION_REG_bits.PS2
541 #define PSA OPTION_REG_bits.PSA
542 #define T0SE OPTION_REG_bits.T0SE
543 #define T0CS OPTION_REG_bits.T0CS
544 #define INTEDG OPTION_REG_bits.INTEDG
545 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
547 // ----- PCON bits --------------------
550 unsigned char NOT_BO:1;
551 unsigned char NOT_POR:1;
560 unsigned char NOT_BOR:1;
570 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
572 #define NOT_BO PCON_bits.NOT_BO
573 #define NOT_BOR PCON_bits.NOT_BOR
574 #define NOT_POR PCON_bits.NOT_POR
576 // ----- PIE1 bits --------------------
579 unsigned char TMR1IE:1;
580 unsigned char TMR2IE:1;
581 unsigned char CCP1IE:1;
582 unsigned char USBIE:1;
583 unsigned char TXIE:1;
584 unsigned char RCIE:1;
585 unsigned char ADIE:1;
589 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
591 #define TMR1IE PIE1_bits.TMR1IE
592 #define TMR2IE PIE1_bits.TMR2IE
593 #define CCP1IE PIE1_bits.CCP1IE
594 #define USBIE PIE1_bits.USBIE
595 #define TXIE PIE1_bits.TXIE
596 #define RCIE PIE1_bits.RCIE
597 #define ADIE PIE1_bits.ADIE
599 // ----- PIE2 bits --------------------
602 unsigned char CCP2IE:1;
612 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
614 #define CCP2IE PIE2_bits.CCP2IE
616 // ----- PIR1 bits --------------------
619 unsigned char TMR1IF:1;
620 unsigned char TMR2IF:1;
621 unsigned char CCP1IF:1;
622 unsigned char USBIF:1;
623 unsigned char TXIF:1;
624 unsigned char RCIF:1;
625 unsigned char ADIF:1;
629 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
631 #define TMR1IF PIR1_bits.TMR1IF
632 #define TMR2IF PIR1_bits.TMR2IF
633 #define CCP1IF PIR1_bits.CCP1IF
634 #define USBIF PIR1_bits.USBIF
635 #define TXIF PIR1_bits.TXIF
636 #define RCIF PIR1_bits.RCIF
637 #define ADIF PIR1_bits.ADIF
639 // ----- PIR2 bits --------------------
642 unsigned char CCP2IF:1;
652 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
654 #define CCP2IF PIR2_bits.CCP2IF
656 // ----- RCSTA bits --------------------
659 unsigned char RX9D:1;
660 unsigned char OERR:1;
661 unsigned char FERR:1;
663 unsigned char CREN:1;
664 unsigned char SREN:1;
666 unsigned char SPEN:1;
669 unsigned char RCD8:1;
685 unsigned char NOT_RC8:1;
695 unsigned char RC8_9:1;
699 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
701 #define RX9D RCSTA_bits.RX9D
702 #define RCD8 RCSTA_bits.RCD8
703 #define OERR RCSTA_bits.OERR
704 #define FERR RCSTA_bits.FERR
705 #define CREN RCSTA_bits.CREN
706 #define SREN RCSTA_bits.SREN
707 #define RX9 RCSTA_bits.RX9
708 #define RC9 RCSTA_bits.RC9
709 #define NOT_RC8 RCSTA_bits.NOT_RC8
710 #define RC8_9 RCSTA_bits.RC8_9
711 #define SPEN RCSTA_bits.SPEN
713 // ----- STATUS bits --------------------
719 unsigned char NOT_PD:1;
720 unsigned char NOT_TO:1;
726 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
728 #define C STATUS_bits.C
729 #define DC STATUS_bits.DC
730 #define Z STATUS_bits.Z
731 #define NOT_PD STATUS_bits.NOT_PD
732 #define NOT_TO STATUS_bits.NOT_TO
733 #define RP0 STATUS_bits.RP0
734 #define RP1 STATUS_bits.RP1
735 #define IRP STATUS_bits.IRP
737 // ----- T1CON bits --------------------
740 unsigned char TMR1ON:1;
741 unsigned char TMR1CS:1;
742 unsigned char NOT_T1SYNC:1;
743 unsigned char T1OSCEN:1;
744 unsigned char T1CKPS0:1;
745 unsigned char T1CKPS1:1;
752 unsigned char T1INSYNC:1;
760 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
762 #define TMR1ON T1CON_bits.TMR1ON
763 #define TMR1CS T1CON_bits.TMR1CS
764 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
765 #define T1INSYNC T1CON_bits.T1INSYNC
766 #define T1OSCEN T1CON_bits.T1OSCEN
767 #define T1CKPS0 T1CON_bits.T1CKPS0
768 #define T1CKPS1 T1CON_bits.T1CKPS1
770 // ----- T2CON bits --------------------
773 unsigned char T2CKPS0:1;
774 unsigned char T2CKPS1:1;
775 unsigned char TMR2ON:1;
776 unsigned char TOUTPS0:1;
777 unsigned char TOUTPS1:1;
778 unsigned char TOUTPS2:1;
779 unsigned char TOUTPS3:1;
783 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
785 #define T2CKPS0 T2CON_bits.T2CKPS0
786 #define T2CKPS1 T2CON_bits.T2CKPS1
787 #define TMR2ON T2CON_bits.TMR2ON
788 #define TOUTPS0 T2CON_bits.TOUTPS0
789 #define TOUTPS1 T2CON_bits.TOUTPS1
790 #define TOUTPS2 T2CON_bits.TOUTPS2
791 #define TOUTPS3 T2CON_bits.TOUTPS3
793 // ----- TXSTA bits --------------------
796 unsigned char TX9D:1;
797 unsigned char TRMT:1;
798 unsigned char BRGH:1;
800 unsigned char SYNC:1;
801 unsigned char TXEN:1;
803 unsigned char CSRC:1;
806 unsigned char TXD8:1;
812 unsigned char NOT_TX8:1;
822 unsigned char TX8_9:1;
826 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
828 #define TX9D TXSTA_bits.TX9D
829 #define TXD8 TXSTA_bits.TXD8
830 #define TRMT TXSTA_bits.TRMT
831 #define BRGH TXSTA_bits.BRGH
832 #define SYNC TXSTA_bits.SYNC
833 #define TXEN TXSTA_bits.TXEN
834 #define TX9 TXSTA_bits.TX9
835 #define NOT_TX8 TXSTA_bits.NOT_TX8
836 #define TX8_9 TXSTA_bits.TX8_9
837 #define CSRC TXSTA_bits.CSRC
839 // ----- UCTRL bits --------------------
843 unsigned char SUSPND:1;
844 unsigned char RESUME:1;
845 unsigned char DEV_ATT:1;
846 unsigned char PKT_DIS:1;
852 extern volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits;
854 #define SUSPND UCTRL_bits.SUSPND
855 #define RESUME UCTRL_bits.RESUME
856 #define DEV_ATT UCTRL_bits.DEV_ATT
857 #define PKT_DIS UCTRL_bits.PKT_DIS
858 #define SE0 UCTRL_bits.SE0
860 // ----- UEIE bits --------------------
863 unsigned char PID_ERR:1;
864 unsigned char CRC5:1;
865 unsigned char CRC16:1;
866 unsigned char DFN8:1;
867 unsigned char BTO_ERR:1;
868 unsigned char WRT_ERR:1;
869 unsigned char OWN_ERR:1;
870 unsigned char BTS_ERR:1;
873 extern volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits;
875 #define PID_ERR UEIE_bits.PID_ERR
876 #define CRC5 UEIE_bits.CRC5
877 #define CRC16 UEIE_bits.CRC16
878 #define DFN8 UEIE_bits.DFN8
879 #define BTO_ERR UEIE_bits.BTO_ERR
880 #define WRT_ERR UEIE_bits.WRT_ERR
881 #define OWN_ERR UEIE_bits.OWN_ERR
882 #define BTS_ERR UEIE_bits.BTS_ERR
884 // ----- UEP2 bits --------------------
887 unsigned char EP_STALL:1;
888 unsigned char EP_IN_EN:1;
889 unsigned char EP_OUT_EN:1;
890 unsigned char EP_CTL_DIS:1;
891 unsigned char PID2:1;
892 unsigned char PID3:1;
893 unsigned char DATA01:1;
894 unsigned char UOWN:1;
899 unsigned char BSTALL:1;
909 unsigned char PID0:1;
910 unsigned char PID1:1;
917 extern volatile __UEP2_bits_t __at(UEP2_ADDR) UEP2_bits;
919 #define EP_STALL UEP2_bits.EP_STALL
920 #define EP_IN_EN UEP2_bits.EP_IN_EN
921 #define EP_OUT_EN UEP2_bits.EP_OUT_EN
922 #define BSTALL UEP2_bits.BSTALL
923 #define PID0 UEP2_bits.PID0
924 #define EP_CTL_DIS UEP2_bits.EP_CTL_DIS
925 #define DTS UEP2_bits.DTS
926 #define PID1 UEP2_bits.PID1
927 #define PID2 UEP2_bits.PID2
928 #define PID3 UEP2_bits.PID3
929 #define DATA01 UEP2_bits.DATA01
930 #define UOWN UEP2_bits.UOWN
931 #define OWN UEP2_bits.OWN
933 // ----- UIE bits --------------------
936 unsigned char USB_RST:1;
937 unsigned char UERR:1;
938 unsigned char ACTIVITY:1;
939 unsigned char TOK_DNE:1;
940 unsigned char UIDLE:1;
941 unsigned char STALL:1;
946 extern volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits;
948 #define USB_RST UIE_bits.USB_RST
949 #define UERR UIE_bits.UERR
950 #define ACTIVITY UIE_bits.ACTIVITY
951 #define TOK_DNE UIE_bits.TOK_DNE
952 #define UIDLE UIE_bits.UIDLE
953 #define STALL UIE_bits.STALL
955 // ----- USTAT bits --------------------
961 unsigned char ENDP0:1;
962 unsigned char ENDP1:1;
968 extern volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits;
970 #define IN USTAT_bits.IN
971 #define ENDP0 USTAT_bits.ENDP0
972 #define ENDP1 USTAT_bits.ENDP1