2 // Register Declarations for Microchip 16C745 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define CCPR1L_ADDR 0x0015
46 #define CCPR1H_ADDR 0x0016
47 #define CCP1CON_ADDR 0x0017
48 #define RCSTA_ADDR 0x0018
49 #define TXREG_ADDR 0x0019
50 #define RCREG_ADDR 0x001A
51 #define CCPR2L_ADDR 0x001B
52 #define CCPR2H_ADDR 0x001C
53 #define CCP2CON_ADDR 0x001D
54 #define ADRES_ADDR 0x001E
55 #define ADCON0_ADDR 0x001F
56 #define OPTION_REG_ADDR 0x0081
57 #define TRISA_ADDR 0x0085
58 #define TRISB_ADDR 0x0086
59 #define TRISC_ADDR 0x0087
60 #define PIE1_ADDR 0x008C
61 #define PIE2_ADDR 0x008D
62 #define PCON_ADDR 0x008E
63 #define PR2_ADDR 0x0092
64 #define TXSTA_ADDR 0x0098
65 #define SPBRG_ADDR 0x0099
66 #define ADCON1_ADDR 0x009F
67 #define UIR_ADDR 0x0190
68 #define UIE_ADDR 0x0191
69 #define UEIR_ADDR 0x0192
70 #define UEIE_ADDR 0x0193
71 #define USTAT_ADDR 0x0194
72 #define UCTRL_ADDR 0x0195
73 #define UADDR_ADDR 0x0196
74 #define USWSTAT_ADDR 0x0197
75 #define UEP0_ADDR 0x0198
76 #define UEP1_ADDR 0x0199
77 #define UEP2_ADDR 0x019A
78 #define BD0OST_ADDR 0x01A0
79 #define BD0OBC_ADDR 0x01A1
80 #define BD0OAL_ADDR 0x01A2
81 #define BD0IST_ADDR 0x01A4
82 #define BD0IBC_ADDR 0x01A5
83 #define BD0IAL_ADDR 0x01A6
84 #define BD1OST_ADDR 0x01A8
85 #define BD1OBC_ADDR 0x01A9
86 #define BD1OAL_ADDR 0x01AA
87 #define BD1IST_ADDR 0x01AC
88 #define BD1IBC_ADDR 0x01AD
89 #define BD1IAL_ADDR 0x01AE
90 #define BD2OST_ADDR 0x01B0
91 #define BD2OBC_ADDR 0x01B1
92 #define BD2OAL_ADDR 0x01B2
93 #define BD2IST_ADDR 0x01B4
94 #define BD2IBC_ADDR 0x01B5
95 #define BD2IAL_ADDR 0x01B6
98 // Memory organization.
104 // P16C745.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
107 // This header file defines configurations, registers, and other useful bits of
108 // information for the PIC16C745 microcontroller. These names are taken to match
109 // the data sheets as closely as possible.
111 // Note that the processor must be selected before this file is
112 // included. The processor may be selected the following ways:
114 // 1. Command line switch:
115 // C:\ MPASM MYFILE.ASM /PIC16C745
116 // 2. LIST directive in the source file
118 // 3. Processor Type entry in the MPASM full-screen interface
120 //==========================================================================
124 //==========================================================================
128 //1.00 28 Sep 99 Initial Release
130 //==========================================================================
134 //==========================================================================
137 // MESSG "Processor-header file mismatch. Verify selected processor."
140 //==========================================================================
142 // Register Definitions
144 //==========================================================================
149 //----- Register Files------------------------------------------------------
151 extern __sfr __at (INDF_ADDR) INDF;
152 extern __sfr __at (TMR0_ADDR) TMR0;
153 extern __sfr __at (PCL_ADDR) PCL;
154 extern __sfr __at (STATUS_ADDR) STATUS;
155 extern __sfr __at (FSR_ADDR) FSR;
156 extern __sfr __at (PORTA_ADDR) PORTA;
157 extern __sfr __at (PORTB_ADDR) PORTB;
158 extern __sfr __at (PORTC_ADDR) PORTC;
159 extern __sfr __at (PCLATH_ADDR) PCLATH;
160 extern __sfr __at (INTCON_ADDR) INTCON;
161 extern __sfr __at (PIR1_ADDR) PIR1;
162 extern __sfr __at (PIR2_ADDR) PIR2;
163 extern __sfr __at (TMR1L_ADDR) TMR1L;
164 extern __sfr __at (TMR1H_ADDR) TMR1H;
165 extern __sfr __at (T1CON_ADDR) T1CON;
166 extern __sfr __at (TMR2_ADDR) TMR2;
167 extern __sfr __at (T2CON_ADDR) T2CON;
168 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
169 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
170 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
171 extern __sfr __at (RCSTA_ADDR) RCSTA;
172 extern __sfr __at (TXREG_ADDR) TXREG;
173 extern __sfr __at (RCREG_ADDR) RCREG;
174 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
175 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
176 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
177 extern __sfr __at (ADRES_ADDR) ADRES;
178 extern __sfr __at (ADCON0_ADDR) ADCON0;
180 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
181 extern __sfr __at (TRISA_ADDR) TRISA;
182 extern __sfr __at (TRISB_ADDR) TRISB;
183 extern __sfr __at (TRISC_ADDR) TRISC;
184 extern __sfr __at (PIE1_ADDR) PIE1;
185 extern __sfr __at (PIE2_ADDR) PIE2;
186 extern __sfr __at (PCON_ADDR) PCON;
187 extern __sfr __at (PR2_ADDR) PR2;
188 extern __sfr __at (TXSTA_ADDR) TXSTA;
189 extern __sfr __at (SPBRG_ADDR) SPBRG;
190 extern __sfr __at (ADCON1_ADDR) ADCON1;
191 extern __sfr __at (UIR_ADDR) UIR;
192 extern __sfr __at (UIE_ADDR) UIE;
193 extern __sfr __at (UEIR_ADDR) UEIR;
194 extern __sfr __at (UEIE_ADDR) UEIE;
195 extern __sfr __at (USTAT_ADDR) USTAT;
196 extern __sfr __at (UCTRL_ADDR) UCTRL;
197 extern __sfr __at (UADDR_ADDR) UADDR;
198 extern __sfr __at (USWSTAT_ADDR) USWSTAT;
199 extern __sfr __at (UEP0_ADDR) UEP0;
200 extern __sfr __at (UEP1_ADDR) UEP1;
201 extern __sfr __at (UEP2_ADDR) UEP2;
203 extern __sfr __at (BD0OST_ADDR) BD0OST;
204 extern __sfr __at (BD0OBC_ADDR) BD0OBC;
205 extern __sfr __at (BD0OAL_ADDR) BD0OAL;
206 extern __sfr __at (BD0IST_ADDR) BD0IST;
207 extern __sfr __at (BD0IBC_ADDR) BD0IBC;
208 extern __sfr __at (BD0IAL_ADDR) BD0IAL;
210 extern __sfr __at (BD1OST_ADDR) BD1OST;
211 extern __sfr __at (BD1OBC_ADDR) BD1OBC;
212 extern __sfr __at (BD1OAL_ADDR) BD1OAL;
213 extern __sfr __at (BD1IST_ADDR) BD1IST;
214 extern __sfr __at (BD1IBC_ADDR) BD1IBC;
215 extern __sfr __at (BD1IAL_ADDR) BD1IAL;
217 extern __sfr __at (BD2OST_ADDR) BD2OST;
218 extern __sfr __at (BD2OBC_ADDR) BD2OBC;
219 extern __sfr __at (BD2OAL_ADDR) BD2OAL;
220 extern __sfr __at (BD2IST_ADDR) BD2IST;
221 extern __sfr __at (BD2IBC_ADDR) BD2IBC;
222 extern __sfr __at (BD2IAL_ADDR) BD2IAL;
225 //----- STATUS Bits --------------------------------------------------------
228 //----- INTCON Bits --------------------------------------------------------
231 //----- PIR1 Bits ----------------------------------------------------------
234 //----- PIR2 Bits ----------------------------------------------------------
237 //----- T1CON Bits ---------------------------------------------------------
240 //----- T2CON Bits ---------------------------------------------------------
243 //----- CCP1CON Bits -------------------------------------------------------
246 //----- RCSTA Bits ---------------------------------------------------------
249 //----- CCP2CON Bits -------------------------------------------------------
252 //----- ADCON0 Bits --------------------------------------------------------
255 //----- OPTION Bits --------------------------------------------------------
259 //----- PIE1 Bits ----------------------------------------------------------
262 //----- PIE2 Bits ----------------------------------------------------------
265 //----- PCON Bits ----------------------------------------------------------
268 //----- TXSTA Bits ---------------------------------------------------------
271 //----- ADCON1 Bits --------------------------------------------------------
274 //----- UIR/UIE Bits -----------------------------------------------------
277 //----- UEIR/UEIE Bits -----------------------------------------------------
280 //----- USTAT Bits ---------------------------------------------------------
283 //----- UCTRL Bits ---------------------------------------------------------
285 //----- UEPn Bits ---------------------------------------------------------
288 //----- Buffer descriptor Bits ---------------------------------------------
290 //==========================================================================
294 //==========================================================================
297 // __BADRAM H'8', H'9', H'13', H'14', H'88', H'89', H'8F'-H'91'
298 // __BADRAM H'93'-H'97', H'9A'-H'9E'
299 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F'
300 // __BADRAM H'185', H'187'-H'189', H'18C'-H'18F', H'19B'-H'19F'
301 // __BADRAM H'1E0'-H'1EF'
302 //==========================================================================
304 // Configuration Bits
306 //==========================================================================
308 #define _CP_ALL 0x00CF
309 #define _CP_75 0x15DF
310 #define _CP_50 0x2AEF
311 #define _CP_OFF 0x3FFF
312 #define _PWRTE_OFF 0x3FFF
313 #define _PWRTE_ON 0x3FF7
314 #define _WDT_ON 0x3FFF
315 #define _WDT_OFF 0x3FFB
316 #define _HS_OSC 0x3FFC
317 #define _EC_OSC 0x3FFD
318 #define _H4_OSC 0x3FFE
319 #define _E4_OSC 0x3FFF
323 // ----- ADCON0 bits --------------------
326 unsigned char ADON:1;
329 unsigned char CHS0:1;
330 unsigned char CHS1:1;
331 unsigned char CHS2:1;
332 unsigned char ADCS0:1;
333 unsigned char ADCS1:1;
338 unsigned char NOT_DONE:1;
348 unsigned char GO_DONE:1;
356 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
358 #ifndef NO_BIT_DEFINES
359 #define ADON ADCON0_bits.ADON
360 #define GO ADCON0_bits.GO
361 #define NOT_DONE ADCON0_bits.NOT_DONE
362 #define GO_DONE ADCON0_bits.GO_DONE
363 #define CHS0 ADCON0_bits.CHS0
364 #define CHS1 ADCON0_bits.CHS1
365 #define CHS2 ADCON0_bits.CHS2
366 #define ADCS0 ADCON0_bits.ADCS0
367 #define ADCS1 ADCON0_bits.ADCS1
368 #endif /* NO_BIT_DEFINES */
370 // ----- ADCON1 bits --------------------
373 unsigned char PCFG0:1;
374 unsigned char PCFG1:1;
375 unsigned char PCFG2:1;
383 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
385 #ifndef NO_BIT_DEFINES
386 #define PCFG0 ADCON1_bits.PCFG0
387 #define PCFG1 ADCON1_bits.PCFG1
388 #define PCFG2 ADCON1_bits.PCFG2
389 #endif /* NO_BIT_DEFINES */
391 // ----- CCP1CON bits --------------------
394 unsigned char CCP1M0:1;
395 unsigned char CCP1M1:1;
396 unsigned char CCP1M2:1;
397 unsigned char CCP1M3:1;
398 unsigned char DC1B0:1;
399 unsigned char DC1B1:1;
404 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
406 #ifndef NO_BIT_DEFINES
407 #define CCP1M0 CCP1CON_bits.CCP1M0
408 #define CCP1M1 CCP1CON_bits.CCP1M1
409 #define CCP1M2 CCP1CON_bits.CCP1M2
410 #define CCP1M3 CCP1CON_bits.CCP1M3
411 #define DC1B0 CCP1CON_bits.DC1B0
412 #define DC1B1 CCP1CON_bits.DC1B1
413 #endif /* NO_BIT_DEFINES */
415 // ----- CCP2CON bits --------------------
418 unsigned char CCP2M0:1;
419 unsigned char CCP2M1:1;
420 unsigned char CCP2M2:1;
421 unsigned char CCP2M3:1;
422 unsigned char DC2B0:1;
423 unsigned char DC2B1:1;
428 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
430 #ifndef NO_BIT_DEFINES
431 #define CCP2M0 CCP2CON_bits.CCP2M0
432 #define CCP2M1 CCP2CON_bits.CCP2M1
433 #define CCP2M2 CCP2CON_bits.CCP2M2
434 #define CCP2M3 CCP2CON_bits.CCP2M3
435 #define DC2B0 CCP2CON_bits.DC2B0
436 #define DC2B1 CCP2CON_bits.DC2B1
437 #endif /* NO_BIT_DEFINES */
439 // ----- INTCON bits --------------------
442 unsigned char RBIF:1;
443 unsigned char INTF:1;
444 unsigned char T0IF:1;
445 unsigned char RBIE:1;
446 unsigned char INTE:1;
447 unsigned char T0IE:1;
448 unsigned char PEIE:1;
452 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
454 #ifndef NO_BIT_DEFINES
455 #define RBIF INTCON_bits.RBIF
456 #define INTF INTCON_bits.INTF
457 #define T0IF INTCON_bits.T0IF
458 #define RBIE INTCON_bits.RBIE
459 #define INTE INTCON_bits.INTE
460 #define T0IE INTCON_bits.T0IE
461 #define PEIE INTCON_bits.PEIE
462 #define GIE INTCON_bits.GIE
463 #endif /* NO_BIT_DEFINES */
465 // ----- OPTION_REG bits --------------------
472 unsigned char T0SE:1;
473 unsigned char T0CS:1;
474 unsigned char INTEDG:1;
475 unsigned char NOT_RBPU:1;
477 } __OPTION_REG_bits_t;
478 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
480 #ifndef NO_BIT_DEFINES
481 #define PS0 OPTION_REG_bits.PS0
482 #define PS1 OPTION_REG_bits.PS1
483 #define PS2 OPTION_REG_bits.PS2
484 #define PSA OPTION_REG_bits.PSA
485 #define T0SE OPTION_REG_bits.T0SE
486 #define T0CS OPTION_REG_bits.T0CS
487 #define INTEDG OPTION_REG_bits.INTEDG
488 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
489 #endif /* NO_BIT_DEFINES */
491 // ----- PCON bits --------------------
494 unsigned char NOT_BO:1;
495 unsigned char NOT_POR:1;
504 unsigned char NOT_BOR:1;
514 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
516 #ifndef NO_BIT_DEFINES
517 #define NOT_BO PCON_bits.NOT_BO
518 #define NOT_BOR PCON_bits.NOT_BOR
519 #define NOT_POR PCON_bits.NOT_POR
520 #endif /* NO_BIT_DEFINES */
522 // ----- PIE1 bits --------------------
525 unsigned char TMR1IE:1;
526 unsigned char TMR2IE:1;
527 unsigned char CCP1IE:1;
528 unsigned char USBIE:1;
529 unsigned char TXIE:1;
530 unsigned char RCIE:1;
531 unsigned char ADIE:1;
535 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
537 #ifndef NO_BIT_DEFINES
538 #define TMR1IE PIE1_bits.TMR1IE
539 #define TMR2IE PIE1_bits.TMR2IE
540 #define CCP1IE PIE1_bits.CCP1IE
541 #define USBIE PIE1_bits.USBIE
542 #define TXIE PIE1_bits.TXIE
543 #define RCIE PIE1_bits.RCIE
544 #define ADIE PIE1_bits.ADIE
545 #endif /* NO_BIT_DEFINES */
547 // ----- PIE2 bits --------------------
550 unsigned char CCP2IE:1;
560 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
562 #ifndef NO_BIT_DEFINES
563 #define CCP2IE PIE2_bits.CCP2IE
564 #endif /* NO_BIT_DEFINES */
566 // ----- PIR1 bits --------------------
569 unsigned char TMR1IF:1;
570 unsigned char TMR2IF:1;
571 unsigned char CCP1IF:1;
572 unsigned char USBIF:1;
573 unsigned char TXIF:1;
574 unsigned char RCIF:1;
575 unsigned char ADIF:1;
579 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
581 #ifndef NO_BIT_DEFINES
582 #define TMR1IF PIR1_bits.TMR1IF
583 #define TMR2IF PIR1_bits.TMR2IF
584 #define CCP1IF PIR1_bits.CCP1IF
585 #define USBIF PIR1_bits.USBIF
586 #define TXIF PIR1_bits.TXIF
587 #define RCIF PIR1_bits.RCIF
588 #define ADIF PIR1_bits.ADIF
589 #endif /* NO_BIT_DEFINES */
591 // ----- PIR2 bits --------------------
594 unsigned char CCP2IF:1;
604 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
606 #ifndef NO_BIT_DEFINES
607 #define CCP2IF PIR2_bits.CCP2IF
608 #endif /* NO_BIT_DEFINES */
610 // ----- PORTA bits --------------------
623 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
625 #ifndef NO_BIT_DEFINES
626 #define RA0 PORTA_bits.RA0
627 #define RA1 PORTA_bits.RA1
628 #define RA2 PORTA_bits.RA2
629 #define RA3 PORTA_bits.RA3
630 #define RA4 PORTA_bits.RA4
631 #define RA5 PORTA_bits.RA5
632 #endif /* NO_BIT_DEFINES */
634 // ----- PORTB bits --------------------
647 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
649 #ifndef NO_BIT_DEFINES
650 #define RB0 PORTB_bits.RB0
651 #define RB1 PORTB_bits.RB1
652 #define RB2 PORTB_bits.RB2
653 #define RB3 PORTB_bits.RB3
654 #define RB4 PORTB_bits.RB4
655 #define RB5 PORTB_bits.RB5
656 #define RB6 PORTB_bits.RB6
657 #define RB7 PORTB_bits.RB7
658 #endif /* NO_BIT_DEFINES */
660 // ----- PORTC bits --------------------
673 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
675 #ifndef NO_BIT_DEFINES
676 #define RC0 PORTC_bits.RC0
677 #define RC1 PORTC_bits.RC1
678 #define RC2 PORTC_bits.RC2
679 #define RC3 PORTC_bits.RC3
680 #define RC4 PORTC_bits.RC4
681 #define RC5 PORTC_bits.RC5
682 #define RC6 PORTC_bits.RC6
683 #define RC7 PORTC_bits.RC7
684 #endif /* NO_BIT_DEFINES */
686 // ----- RCSTA bits --------------------
689 unsigned char RX9D:1;
690 unsigned char OERR:1;
691 unsigned char FERR:1;
693 unsigned char CREN:1;
694 unsigned char SREN:1;
696 unsigned char SPEN:1;
699 unsigned char RCD8:1;
715 unsigned char NOT_RC8:1;
725 unsigned char RC8_9:1;
729 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
731 #ifndef NO_BIT_DEFINES
732 #define RX9D RCSTA_bits.RX9D
733 #define RCD8 RCSTA_bits.RCD8
734 #define OERR RCSTA_bits.OERR
735 #define FERR RCSTA_bits.FERR
736 #define CREN RCSTA_bits.CREN
737 #define SREN RCSTA_bits.SREN
738 #define RX9 RCSTA_bits.RX9
739 #define RC9 RCSTA_bits.RC9
740 #define NOT_RC8 RCSTA_bits.NOT_RC8
741 #define RC8_9 RCSTA_bits.RC8_9
742 #define SPEN RCSTA_bits.SPEN
743 #endif /* NO_BIT_DEFINES */
745 // ----- STATUS bits --------------------
751 unsigned char NOT_PD:1;
752 unsigned char NOT_TO:1;
758 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
760 #ifndef NO_BIT_DEFINES
761 #define C STATUS_bits.C
762 #define DC STATUS_bits.DC
763 #define Z STATUS_bits.Z
764 #define NOT_PD STATUS_bits.NOT_PD
765 #define NOT_TO STATUS_bits.NOT_TO
766 #define RP0 STATUS_bits.RP0
767 #define RP1 STATUS_bits.RP1
768 #define IRP STATUS_bits.IRP
769 #endif /* NO_BIT_DEFINES */
771 // ----- T1CON bits --------------------
774 unsigned char TMR1ON:1;
775 unsigned char TMR1CS:1;
776 unsigned char NOT_T1SYNC:1;
777 unsigned char T1OSCEN:1;
778 unsigned char T1CKPS0:1;
779 unsigned char T1CKPS1:1;
786 unsigned char T1INSYNC:1;
794 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
796 #ifndef NO_BIT_DEFINES
797 #define TMR1ON T1CON_bits.TMR1ON
798 #define TMR1CS T1CON_bits.TMR1CS
799 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
800 #define T1INSYNC T1CON_bits.T1INSYNC
801 #define T1OSCEN T1CON_bits.T1OSCEN
802 #define T1CKPS0 T1CON_bits.T1CKPS0
803 #define T1CKPS1 T1CON_bits.T1CKPS1
804 #endif /* NO_BIT_DEFINES */
806 // ----- T2CON bits --------------------
809 unsigned char T2CKPS0:1;
810 unsigned char T2CKPS1:1;
811 unsigned char TMR2ON:1;
812 unsigned char TOUTPS0:1;
813 unsigned char TOUTPS1:1;
814 unsigned char TOUTPS2:1;
815 unsigned char TOUTPS3:1;
819 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
821 #ifndef NO_BIT_DEFINES
822 #define T2CKPS0 T2CON_bits.T2CKPS0
823 #define T2CKPS1 T2CON_bits.T2CKPS1
824 #define TMR2ON T2CON_bits.TMR2ON
825 #define TOUTPS0 T2CON_bits.TOUTPS0
826 #define TOUTPS1 T2CON_bits.TOUTPS1
827 #define TOUTPS2 T2CON_bits.TOUTPS2
828 #define TOUTPS3 T2CON_bits.TOUTPS3
829 #endif /* NO_BIT_DEFINES */
831 // ----- TRISA bits --------------------
834 unsigned char TRISA0:1;
835 unsigned char TRISA1:1;
836 unsigned char TRISA2:1;
837 unsigned char TRISA3:1;
838 unsigned char TRISA4:1;
839 unsigned char TRISA5:1;
844 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
846 #ifndef NO_BIT_DEFINES
847 #define TRISA0 TRISA_bits.TRISA0
848 #define TRISA1 TRISA_bits.TRISA1
849 #define TRISA2 TRISA_bits.TRISA2
850 #define TRISA3 TRISA_bits.TRISA3
851 #define TRISA4 TRISA_bits.TRISA4
852 #define TRISA5 TRISA_bits.TRISA5
853 #endif /* NO_BIT_DEFINES */
855 // ----- TRISB bits --------------------
858 unsigned char TRISB0:1;
859 unsigned char TRISB1:1;
860 unsigned char TRISB2:1;
861 unsigned char TRISB3:1;
862 unsigned char TRISB4:1;
863 unsigned char TRISB5:1;
864 unsigned char TRISB6:1;
865 unsigned char TRISB7:1;
868 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
870 #ifndef NO_BIT_DEFINES
871 #define TRISB0 TRISB_bits.TRISB0
872 #define TRISB1 TRISB_bits.TRISB1
873 #define TRISB2 TRISB_bits.TRISB2
874 #define TRISB3 TRISB_bits.TRISB3
875 #define TRISB4 TRISB_bits.TRISB4
876 #define TRISB5 TRISB_bits.TRISB5
877 #define TRISB6 TRISB_bits.TRISB6
878 #define TRISB7 TRISB_bits.TRISB7
879 #endif /* NO_BIT_DEFINES */
881 // ----- TRISC bits --------------------
884 unsigned char TRISC0:1;
885 unsigned char TRISC1:1;
886 unsigned char TRISC2:1;
887 unsigned char TRISC3:1;
888 unsigned char TRISC4:1;
889 unsigned char TRISC5:1;
890 unsigned char TRISC6:1;
891 unsigned char TRISC7:1;
894 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
896 #ifndef NO_BIT_DEFINES
897 #define TRISC0 TRISC_bits.TRISC0
898 #define TRISC1 TRISC_bits.TRISC1
899 #define TRISC2 TRISC_bits.TRISC2
900 #define TRISC3 TRISC_bits.TRISC3
901 #define TRISC4 TRISC_bits.TRISC4
902 #define TRISC5 TRISC_bits.TRISC5
903 #define TRISC6 TRISC_bits.TRISC6
904 #define TRISC7 TRISC_bits.TRISC7
905 #endif /* NO_BIT_DEFINES */
907 // ----- TXSTA bits --------------------
910 unsigned char TX9D:1;
911 unsigned char TRMT:1;
912 unsigned char BRGH:1;
914 unsigned char SYNC:1;
915 unsigned char TXEN:1;
917 unsigned char CSRC:1;
920 unsigned char TXD8:1;
926 unsigned char NOT_TX8:1;
936 unsigned char TX8_9:1;
940 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
942 #ifndef NO_BIT_DEFINES
943 #define TX9D TXSTA_bits.TX9D
944 #define TXD8 TXSTA_bits.TXD8
945 #define TRMT TXSTA_bits.TRMT
946 #define BRGH TXSTA_bits.BRGH
947 #define SYNC TXSTA_bits.SYNC
948 #define TXEN TXSTA_bits.TXEN
949 #define TX9 TXSTA_bits.TX9
950 #define NOT_TX8 TXSTA_bits.NOT_TX8
951 #define TX8_9 TXSTA_bits.TX8_9
952 #define CSRC TXSTA_bits.CSRC
953 #endif /* NO_BIT_DEFINES */
955 // ----- UCTRL bits --------------------
959 unsigned char SUSPND:1;
960 unsigned char RESUME:1;
961 unsigned char DEV_ATT:1;
962 unsigned char PKT_DIS:1;
968 extern volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits;
970 #ifndef NO_BIT_DEFINES
971 #define SUSPND UCTRL_bits.SUSPND
972 #define RESUME UCTRL_bits.RESUME
973 #define DEV_ATT UCTRL_bits.DEV_ATT
974 #define PKT_DIS UCTRL_bits.PKT_DIS
975 #define SE0 UCTRL_bits.SE0
976 #endif /* NO_BIT_DEFINES */
978 // ----- UEIE bits --------------------
981 unsigned char PID_ERR:1;
982 unsigned char CRC5:1;
983 unsigned char CRC16:1;
984 unsigned char DFN8:1;
985 unsigned char BTO_ERR:1;
986 unsigned char WRT_ERR:1;
987 unsigned char OWN_ERR:1;
988 unsigned char BTS_ERR:1;
991 extern volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits;
993 #ifndef NO_BIT_DEFINES
994 #define PID_ERR UEIE_bits.PID_ERR
995 #define CRC5 UEIE_bits.CRC5
996 #define CRC16 UEIE_bits.CRC16
997 #define DFN8 UEIE_bits.DFN8
998 #define BTO_ERR UEIE_bits.BTO_ERR
999 #define WRT_ERR UEIE_bits.WRT_ERR
1000 #define OWN_ERR UEIE_bits.OWN_ERR
1001 #define BTS_ERR UEIE_bits.BTS_ERR
1002 #endif /* NO_BIT_DEFINES */
1004 // ----- UEP0 bits --------------------
1007 unsigned char EP_STALL:1;
1008 unsigned char EP_IN_EN:1;
1009 unsigned char EP_OUT_EN:1;
1010 unsigned char EP_CTL_DIS:1;
1011 unsigned char PID2:1;
1012 unsigned char PID3:1;
1013 unsigned char DATA01:1;
1014 unsigned char UOWN:1;
1019 unsigned char BSTALL:1;
1020 unsigned char DTS:1;
1024 unsigned char OWN:1;
1029 unsigned char PID0:1;
1030 unsigned char PID1:1;
1037 extern volatile __UEP0_bits_t __at(UEP0_ADDR) UEP0_bits;
1039 #ifndef NO_BIT_DEFINES
1040 #define EP_STALL UEP0_bits.EP_STALL
1041 #define EP_IN_EN UEP0_bits.EP_IN_EN
1042 #define EP_OUT_EN UEP0_bits.EP_OUT_EN
1043 #define BSTALL UEP0_bits.BSTALL
1044 #define PID0 UEP0_bits.PID0
1045 #define EP_CTL_DIS UEP0_bits.EP_CTL_DIS
1046 #define DTS UEP0_bits.DTS
1047 #define PID1 UEP0_bits.PID1
1048 #define PID2 UEP0_bits.PID2
1049 #define PID3 UEP0_bits.PID3
1050 #define DATA01 UEP0_bits.DATA01
1051 #define UOWN UEP0_bits.UOWN
1052 #define OWN UEP0_bits.OWN
1053 #endif /* NO_BIT_DEFINES */
1055 // ----- UIE bits --------------------
1058 unsigned char USB_RST:1;
1059 unsigned char UERR:1;
1060 unsigned char ACTIVITY:1;
1061 unsigned char TOK_DNE:1;
1062 unsigned char UIDLE:1;
1063 unsigned char STALL:1;
1068 extern volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits;
1070 #ifndef NO_BIT_DEFINES
1071 #define USB_RST UIE_bits.USB_RST
1072 #define UERR UIE_bits.UERR
1073 #define ACTIVITY UIE_bits.ACTIVITY
1074 #define TOK_DNE UIE_bits.TOK_DNE
1075 #define UIDLE UIE_bits.UIDLE
1076 #define STALL UIE_bits.STALL
1077 #endif /* NO_BIT_DEFINES */
1079 // ----- USTAT bits --------------------
1085 unsigned char ENDP0:1;
1086 unsigned char ENDP1:1;
1092 extern volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits;
1094 #ifndef NO_BIT_DEFINES
1095 #define IN USTAT_bits.IN
1096 #define ENDP0 USTAT_bits.ENDP0
1097 #define ENDP1 USTAT_bits.ENDP1
1098 #endif /* NO_BIT_DEFINES */