2 // Register Declarations for Microchip 16C745 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define CCPR1L_ADDR 0x0015
46 #define CCPR1H_ADDR 0x0016
47 #define CCP1CON_ADDR 0x0017
48 #define RCSTA_ADDR 0x0018
49 #define TXREG_ADDR 0x0019
50 #define RCREG_ADDR 0x001A
51 #define CCPR2L_ADDR 0x001B
52 #define CCPR2H_ADDR 0x001C
53 #define CCP2CON_ADDR 0x001D
54 #define ADRES_ADDR 0x001E
55 #define ADCON0_ADDR 0x001F
56 #define OPTION_REG_ADDR 0x0081
57 #define TRISA_ADDR 0x0085
58 #define TRISB_ADDR 0x0086
59 #define TRISC_ADDR 0x0087
60 #define PIE1_ADDR 0x008C
61 #define PIE2_ADDR 0x008D
62 #define PCON_ADDR 0x008E
63 #define PR2_ADDR 0x0092
64 #define TXSTA_ADDR 0x0098
65 #define SPBRG_ADDR 0x0099
66 #define ADCON1_ADDR 0x009F
67 #define UIR_ADDR 0x0190
68 #define UIE_ADDR 0x0191
69 #define UEIR_ADDR 0x0192
70 #define UEIE_ADDR 0x0193
71 #define USTAT_ADDR 0x0194
72 #define UCTRL_ADDR 0x0195
73 #define UADDR_ADDR 0x0196
74 #define USWSTAT_ADDR 0x0197
75 #define UEP0_ADDR 0x0198
76 #define UEP1_ADDR 0x0199
77 #define UEP2_ADDR 0x019A
78 #define BD0OST_ADDR 0x01A0
79 #define BD0OBC_ADDR 0x01A1
80 #define BD0OAL_ADDR 0x01A2
81 #define BD0IST_ADDR 0x01A4
82 #define BD0IBC_ADDR 0x01A5
83 #define BD0IAL_ADDR 0x01A6
84 #define BD1OST_ADDR 0x01A8
85 #define BD1OBC_ADDR 0x01A9
86 #define BD1OAL_ADDR 0x01AA
87 #define BD1IST_ADDR 0x01AC
88 #define BD1IBC_ADDR 0x01AD
89 #define BD1IAL_ADDR 0x01AE
90 #define BD2OST_ADDR 0x01B0
91 #define BD2OBC_ADDR 0x01B1
92 #define BD2OAL_ADDR 0x01B2
93 #define BD2IST_ADDR 0x01B4
94 #define BD2IBC_ADDR 0x01B5
95 #define BD2IAL_ADDR 0x01B6
98 // Memory organization.
104 // P16C745.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
107 // This header file defines configurations, registers, and other useful bits of
108 // information for the PIC16C745 microcontroller. These names are taken to match
109 // the data sheets as closely as possible.
111 // Note that the processor must be selected before this file is
112 // included. The processor may be selected the following ways:
114 // 1. Command line switch:
115 // C:\ MPASM MYFILE.ASM /PIC16C745
116 // 2. LIST directive in the source file
118 // 3. Processor Type entry in the MPASM full-screen interface
120 //==========================================================================
124 //==========================================================================
128 //1.00 28 Sep 99 Initial Release
130 //==========================================================================
134 //==========================================================================
137 // MESSG "Processor-header file mismatch. Verify selected processor."
140 //==========================================================================
142 // Register Definitions
144 //==========================================================================
149 //----- Register Files------------------------------------------------------
151 extern __data __at (INDF_ADDR) volatile char INDF;
152 extern __sfr __at (TMR0_ADDR) TMR0;
153 extern __data __at (PCL_ADDR) volatile char PCL;
154 extern __sfr __at (STATUS_ADDR) STATUS;
155 extern __sfr __at (FSR_ADDR) FSR;
156 extern __sfr __at (PORTA_ADDR) PORTA;
157 extern __sfr __at (PORTB_ADDR) PORTB;
158 extern __sfr __at (PORTC_ADDR) PORTC;
159 extern __sfr __at (PCLATH_ADDR) PCLATH;
160 extern __sfr __at (INTCON_ADDR) INTCON;
161 extern __sfr __at (PIR1_ADDR) PIR1;
162 extern __sfr __at (PIR2_ADDR) PIR2;
163 extern __sfr __at (TMR1L_ADDR) TMR1L;
164 extern __sfr __at (TMR1H_ADDR) TMR1H;
165 extern __sfr __at (T1CON_ADDR) T1CON;
166 extern __sfr __at (TMR2_ADDR) TMR2;
167 extern __sfr __at (T2CON_ADDR) T2CON;
168 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
169 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
170 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
171 extern __sfr __at (RCSTA_ADDR) RCSTA;
172 extern __sfr __at (TXREG_ADDR) TXREG;
173 extern __sfr __at (RCREG_ADDR) RCREG;
174 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
175 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
176 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
177 extern __sfr __at (ADRES_ADDR) ADRES;
178 extern __sfr __at (ADCON0_ADDR) ADCON0;
180 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
181 extern __sfr __at (TRISA_ADDR) TRISA;
182 extern __sfr __at (TRISB_ADDR) TRISB;
183 extern __sfr __at (TRISC_ADDR) TRISC;
184 extern __sfr __at (PIE1_ADDR) PIE1;
185 extern __sfr __at (PIE2_ADDR) PIE2;
186 extern __sfr __at (PCON_ADDR) PCON;
187 extern __sfr __at (PR2_ADDR) PR2;
188 extern __sfr __at (TXSTA_ADDR) TXSTA;
189 extern __sfr __at (SPBRG_ADDR) SPBRG;
190 extern __sfr __at (ADCON1_ADDR) ADCON1;
191 extern __sfr __at (UIR_ADDR) UIR;
192 extern __sfr __at (UIE_ADDR) UIE;
193 extern __sfr __at (UEIR_ADDR) UEIR;
194 extern __sfr __at (UEIE_ADDR) UEIE;
195 extern __sfr __at (USTAT_ADDR) USTAT;
196 extern __sfr __at (UCTRL_ADDR) UCTRL;
197 extern __sfr __at (UADDR_ADDR) UADDR;
198 extern __sfr __at (USWSTAT_ADDR) USWSTAT;
199 extern __sfr __at (UEP0_ADDR) UEP0;
200 extern __sfr __at (UEP1_ADDR) UEP1;
201 extern __sfr __at (UEP2_ADDR) UEP2;
203 extern __sfr __at (BD0OST_ADDR) BD0OST;
204 extern __sfr __at (BD0OBC_ADDR) BD0OBC;
205 extern __sfr __at (BD0OAL_ADDR) BD0OAL;
206 extern __sfr __at (BD0IST_ADDR) BD0IST;
207 extern __sfr __at (BD0IBC_ADDR) BD0IBC;
208 extern __sfr __at (BD0IAL_ADDR) BD0IAL;
210 extern __sfr __at (BD1OST_ADDR) BD1OST;
211 extern __sfr __at (BD1OBC_ADDR) BD1OBC;
212 extern __sfr __at (BD1OAL_ADDR) BD1OAL;
213 extern __sfr __at (BD1IST_ADDR) BD1IST;
214 extern __sfr __at (BD1IBC_ADDR) BD1IBC;
215 extern __sfr __at (BD1IAL_ADDR) BD1IAL;
217 extern __sfr __at (BD2OST_ADDR) BD2OST;
218 extern __sfr __at (BD2OBC_ADDR) BD2OBC;
219 extern __sfr __at (BD2OAL_ADDR) BD2OAL;
220 extern __sfr __at (BD2IST_ADDR) BD2IST;
221 extern __sfr __at (BD2IBC_ADDR) BD2IBC;
222 extern __sfr __at (BD2IAL_ADDR) BD2IAL;
225 //----- STATUS Bits --------------------------------------------------------
228 //----- INTCON Bits --------------------------------------------------------
231 //----- PIR1 Bits ----------------------------------------------------------
234 //----- PIR2 Bits ----------------------------------------------------------
237 //----- T1CON Bits ---------------------------------------------------------
240 //----- T2CON Bits ---------------------------------------------------------
243 //----- CCP1CON Bits -------------------------------------------------------
246 //----- RCSTA Bits ---------------------------------------------------------
249 //----- CCP2CON Bits -------------------------------------------------------
252 //----- ADCON0 Bits --------------------------------------------------------
255 //----- OPTION Bits --------------------------------------------------------
259 //----- PIE1 Bits ----------------------------------------------------------
262 //----- PIE2 Bits ----------------------------------------------------------
265 //----- PCON Bits ----------------------------------------------------------
268 //----- TXSTA Bits ---------------------------------------------------------
271 //----- ADCON1 Bits --------------------------------------------------------
274 //----- UIR/UIE Bits -----------------------------------------------------
277 //----- UEIR/UEIE Bits -----------------------------------------------------
280 //----- USTAT Bits ---------------------------------------------------------
283 //----- UCTRL Bits ---------------------------------------------------------
285 //----- UEP0/UEP1/UEP2 Bits ------------------------------------------------
288 //----- Buffer descriptor Bits ---------------------------------------------
290 //==========================================================================
294 //==========================================================================
297 // __BADRAM H'8', H'9', H'13', H'14', H'88', H'89', H'8F'-H'91'
298 // __BADRAM H'93'-H'97', H'9A'-H'9E'
299 // __BADRAM H'105', H'107'-H'109', H'10C'-H'11F'
300 // __BADRAM H'185', H'187'-H'189', H'18C'-H'18F', H'19B'-H'19F'
301 // __BADRAM H'1E0'-H'1EF'
302 //==========================================================================
304 // Configuration Bits
306 //==========================================================================
308 #define _CP_ALL 0x00CF
309 #define _CP_75 0x15DF
310 #define _CP_50 0x2AEF
311 #define _CP_OFF 0x3FFF
312 #define _PWRTE_OFF 0x3FFF
313 #define _PWRTE_ON 0x3FF7
314 #define _WDT_ON 0x3FFF
315 #define _WDT_OFF 0x3FFB
316 #define _HS_OSC 0x3FFC
317 #define _EC_OSC 0x3FFD
318 #define _H4_OSC 0x3FFE
319 #define _E4_OSC 0x3FFF
323 // ----- ADCON0 bits --------------------
326 unsigned char ADON:1;
329 unsigned char CHS0:1;
330 unsigned char CHS1:1;
331 unsigned char CHS2:1;
332 unsigned char ADCS0:1;
333 unsigned char ADCS1:1;
338 unsigned char NOT_DONE:1;
348 unsigned char GO_DONE:1;
356 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
358 #define ADON ADCON0_bits.ADON
359 #define GO ADCON0_bits.GO
360 #define NOT_DONE ADCON0_bits.NOT_DONE
361 #define GO_DONE ADCON0_bits.GO_DONE
362 #define CHS0 ADCON0_bits.CHS0
363 #define CHS1 ADCON0_bits.CHS1
364 #define CHS2 ADCON0_bits.CHS2
365 #define ADCS0 ADCON0_bits.ADCS0
366 #define ADCS1 ADCON0_bits.ADCS1
368 // ----- ADCON1 bits --------------------
371 unsigned char PCFG0:1;
372 unsigned char PCFG1:1;
373 unsigned char PCFG2:1;
381 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
383 #define PCFG0 ADCON1_bits.PCFG0
384 #define PCFG1 ADCON1_bits.PCFG1
385 #define PCFG2 ADCON1_bits.PCFG2
387 // ----- CCP1CON bits --------------------
390 unsigned char CCP1M0:1;
391 unsigned char CCP1M1:1;
392 unsigned char CCP1M2:1;
393 unsigned char CCP1M3:1;
394 unsigned char DC1B0:1;
395 unsigned char DC1B1:1;
400 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
402 #define CCP1M0 CCP1CON_bits.CCP1M0
403 #define CCP1M1 CCP1CON_bits.CCP1M1
404 #define CCP1M2 CCP1CON_bits.CCP1M2
405 #define CCP1M3 CCP1CON_bits.CCP1M3
406 #define DC1B0 CCP1CON_bits.DC1B0
407 #define DC1B1 CCP1CON_bits.DC1B1
409 // ----- CCP2CON bits --------------------
412 unsigned char CCP2M0:1;
413 unsigned char CCP2M1:1;
414 unsigned char CCP2M2:1;
415 unsigned char CCP2M3:1;
416 unsigned char DC2B0:1;
417 unsigned char DC2B1:1;
422 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
424 #define CCP2M0 CCP2CON_bits.CCP2M0
425 #define CCP2M1 CCP2CON_bits.CCP2M1
426 #define CCP2M2 CCP2CON_bits.CCP2M2
427 #define CCP2M3 CCP2CON_bits.CCP2M3
428 #define DC2B0 CCP2CON_bits.DC2B0
429 #define DC2B1 CCP2CON_bits.DC2B1
431 // ----- INTCON bits --------------------
434 unsigned char RBIF:1;
435 unsigned char INTF:1;
436 unsigned char T0IF:1;
437 unsigned char RBIE:1;
438 unsigned char INTE:1;
439 unsigned char T0IE:1;
440 unsigned char PEIE:1;
444 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
446 #define RBIF INTCON_bits.RBIF
447 #define INTF INTCON_bits.INTF
448 #define T0IF INTCON_bits.T0IF
449 #define RBIE INTCON_bits.RBIE
450 #define INTE INTCON_bits.INTE
451 #define T0IE INTCON_bits.T0IE
452 #define PEIE INTCON_bits.PEIE
453 #define GIE INTCON_bits.GIE
455 // ----- OPTION_REG bits --------------------
462 unsigned char T0SE:1;
463 unsigned char T0CS:1;
464 unsigned char INTEDG:1;
465 unsigned char NOT_RBPU:1;
467 } __OPTION_REG_bits_t;
468 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
470 #define PS0 OPTION_REG_bits.PS0
471 #define PS1 OPTION_REG_bits.PS1
472 #define PS2 OPTION_REG_bits.PS2
473 #define PSA OPTION_REG_bits.PSA
474 #define T0SE OPTION_REG_bits.T0SE
475 #define T0CS OPTION_REG_bits.T0CS
476 #define INTEDG OPTION_REG_bits.INTEDG
477 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
479 // ----- PCON bits --------------------
482 unsigned char NOT_BO:1;
483 unsigned char NOT_POR:1;
492 unsigned char NOT_BOR:1;
502 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
504 #define NOT_BO PCON_bits.NOT_BO
505 #define NOT_BOR PCON_bits.NOT_BOR
506 #define NOT_POR PCON_bits.NOT_POR
508 // ----- PIE1 bits --------------------
511 unsigned char TMR1IE:1;
512 unsigned char TMR2IE:1;
513 unsigned char CCP1IE:1;
514 unsigned char USBIE:1;
515 unsigned char TXIE:1;
516 unsigned char RCIE:1;
517 unsigned char ADIE:1;
521 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
523 #define TMR1IE PIE1_bits.TMR1IE
524 #define TMR2IE PIE1_bits.TMR2IE
525 #define CCP1IE PIE1_bits.CCP1IE
526 #define USBIE PIE1_bits.USBIE
527 #define TXIE PIE1_bits.TXIE
528 #define RCIE PIE1_bits.RCIE
529 #define ADIE PIE1_bits.ADIE
531 // ----- PIE2 bits --------------------
534 unsigned char CCP2IE:1;
544 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
546 #define CCP2IE PIE2_bits.CCP2IE
548 // ----- PIR1 bits --------------------
551 unsigned char TMR1IF:1;
552 unsigned char TMR2IF:1;
553 unsigned char CCP1IF:1;
554 unsigned char USBIF:1;
555 unsigned char TXIF:1;
556 unsigned char RCIF:1;
557 unsigned char ADIF:1;
561 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
563 #define TMR1IF PIR1_bits.TMR1IF
564 #define TMR2IF PIR1_bits.TMR2IF
565 #define CCP1IF PIR1_bits.CCP1IF
566 #define USBIF PIR1_bits.USBIF
567 #define TXIF PIR1_bits.TXIF
568 #define RCIF PIR1_bits.RCIF
569 #define ADIF PIR1_bits.ADIF
571 // ----- PIR2 bits --------------------
574 unsigned char CCP2IF:1;
584 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
586 #define CCP2IF PIR2_bits.CCP2IF
588 // ----- RCSTA bits --------------------
591 unsigned char RX9D:1;
592 unsigned char OERR:1;
593 unsigned char FERR:1;
595 unsigned char CREN:1;
596 unsigned char SREN:1;
598 unsigned char SPEN:1;
601 unsigned char RCD8:1;
617 unsigned char NOT_RC8:1;
627 unsigned char RC8_9:1;
631 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
633 #define RX9D RCSTA_bits.RX9D
634 #define RCD8 RCSTA_bits.RCD8
635 #define OERR RCSTA_bits.OERR
636 #define FERR RCSTA_bits.FERR
637 #define CREN RCSTA_bits.CREN
638 #define SREN RCSTA_bits.SREN
639 #define RX9 RCSTA_bits.RX9
640 #define RC9 RCSTA_bits.RC9
641 #define NOT_RC8 RCSTA_bits.NOT_RC8
642 #define RC8_9 RCSTA_bits.RC8_9
643 #define SPEN RCSTA_bits.SPEN
645 // ----- STATUS bits --------------------
651 unsigned char NOT_PD:1;
652 unsigned char NOT_TO:1;
658 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
660 #define C STATUS_bits.C
661 #define DC STATUS_bits.DC
662 #define Z STATUS_bits.Z
663 #define NOT_PD STATUS_bits.NOT_PD
664 #define NOT_TO STATUS_bits.NOT_TO
665 #define RP0 STATUS_bits.RP0
666 #define RP1 STATUS_bits.RP1
667 #define IRP STATUS_bits.IRP
669 // ----- T1CON bits --------------------
672 unsigned char TMR1ON:1;
673 unsigned char TMR1CS:1;
674 unsigned char NOT_T1SYNC:1;
675 unsigned char T1OSCEN:1;
676 unsigned char T1CKPS0:1;
677 unsigned char T1CKPS1:1;
684 unsigned char T1INSYNC:1;
692 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
694 #define TMR1ON T1CON_bits.TMR1ON
695 #define TMR1CS T1CON_bits.TMR1CS
696 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
697 #define T1INSYNC T1CON_bits.T1INSYNC
698 #define T1OSCEN T1CON_bits.T1OSCEN
699 #define T1CKPS0 T1CON_bits.T1CKPS0
700 #define T1CKPS1 T1CON_bits.T1CKPS1
702 // ----- T2CON bits --------------------
705 unsigned char T2CKPS0:1;
706 unsigned char T2CKPS1:1;
707 unsigned char TMR2ON:1;
708 unsigned char TOUTPS0:1;
709 unsigned char TOUTPS1:1;
710 unsigned char TOUTPS2:1;
711 unsigned char TOUTPS3:1;
715 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
717 #define T2CKPS0 T2CON_bits.T2CKPS0
718 #define T2CKPS1 T2CON_bits.T2CKPS1
719 #define TMR2ON T2CON_bits.TMR2ON
720 #define TOUTPS0 T2CON_bits.TOUTPS0
721 #define TOUTPS1 T2CON_bits.TOUTPS1
722 #define TOUTPS2 T2CON_bits.TOUTPS2
723 #define TOUTPS3 T2CON_bits.TOUTPS3
725 // ----- TXSTA bits --------------------
728 unsigned char TX9D:1;
729 unsigned char TRMT:1;
730 unsigned char BRGH:1;
732 unsigned char SYNC:1;
733 unsigned char TXEN:1;
735 unsigned char CSRC:1;
738 unsigned char TXD8:1;
744 unsigned char NOT_TX8:1;
754 unsigned char TX8_9:1;
758 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
760 #define TX9D TXSTA_bits.TX9D
761 #define TXD8 TXSTA_bits.TXD8
762 #define TRMT TXSTA_bits.TRMT
763 #define BRGH TXSTA_bits.BRGH
764 #define SYNC TXSTA_bits.SYNC
765 #define TXEN TXSTA_bits.TXEN
766 #define TX9 TXSTA_bits.TX9
767 #define NOT_TX8 TXSTA_bits.NOT_TX8
768 #define TX8_9 TXSTA_bits.TX8_9
769 #define CSRC TXSTA_bits.CSRC
771 // ----- UCTRL bits --------------------
775 unsigned char SUSPND:1;
776 unsigned char RESUME:1;
777 unsigned char DEV_ATT:1;
778 unsigned char PKT_DIS:1;
784 extern volatile __UCTRL_bits_t __at(UCTRL_ADDR) UCTRL_bits;
786 #define SUSPND UCTRL_bits.SUSPND
787 #define RESUME UCTRL_bits.RESUME
788 #define DEV_ATT UCTRL_bits.DEV_ATT
789 #define PKT_DIS UCTRL_bits.PKT_DIS
790 #define SE0 UCTRL_bits.SE0
792 // ----- UEIE bits --------------------
795 unsigned char PID_ERR:1;
796 unsigned char CRC5:1;
797 unsigned char CRC16:1;
798 unsigned char DFN8:1;
799 unsigned char BTO_ERR:1;
800 unsigned char WRT_ERR:1;
801 unsigned char OWN_ERR:1;
802 unsigned char BTS_ERR:1;
805 extern volatile __UEIE_bits_t __at(UEIE_ADDR) UEIE_bits;
807 #define PID_ERR UEIE_bits.PID_ERR
808 #define CRC5 UEIE_bits.CRC5
809 #define CRC16 UEIE_bits.CRC16
810 #define DFN8 UEIE_bits.DFN8
811 #define BTO_ERR UEIE_bits.BTO_ERR
812 #define WRT_ERR UEIE_bits.WRT_ERR
813 #define OWN_ERR UEIE_bits.OWN_ERR
814 #define BTS_ERR UEIE_bits.BTS_ERR
816 // ----- UEP2 bits --------------------
819 unsigned char EP_STALL:1;
820 unsigned char EP_IN_EN:1;
821 unsigned char EP_OUT_EN:1;
822 unsigned char EP_CTL_DIS:1;
823 unsigned char PID2:1;
824 unsigned char PID3:1;
825 unsigned char DATA01:1;
826 unsigned char UOWN:1;
831 unsigned char BSTALL:1;
841 unsigned char PID0:1;
842 unsigned char PID1:1;
849 extern volatile __UEP2_bits_t __at(UEP2_ADDR) UEP2_bits;
851 #define EP_STALL UEP2_bits.EP_STALL
852 #define EP_IN_EN UEP2_bits.EP_IN_EN
853 #define EP_OUT_EN UEP2_bits.EP_OUT_EN
854 #define BSTALL UEP2_bits.BSTALL
855 #define PID0 UEP2_bits.PID0
856 #define EP_CTL_DIS UEP2_bits.EP_CTL_DIS
857 #define DTS UEP2_bits.DTS
858 #define PID1 UEP2_bits.PID1
859 #define PID2 UEP2_bits.PID2
860 #define PID3 UEP2_bits.PID3
861 #define DATA01 UEP2_bits.DATA01
862 #define UOWN UEP2_bits.UOWN
863 #define OWN UEP2_bits.OWN
865 // ----- UIE bits --------------------
868 unsigned char USB_RST:1;
869 unsigned char UERR:1;
870 unsigned char ACTIVITY:1;
871 unsigned char TOK_DNE:1;
872 unsigned char UIDLE:1;
873 unsigned char STALL:1;
878 extern volatile __UIE_bits_t __at(UIE_ADDR) UIE_bits;
880 #define USB_RST UIE_bits.USB_RST
881 #define UERR UIE_bits.UERR
882 #define ACTIVITY UIE_bits.ACTIVITY
883 #define TOK_DNE UIE_bits.TOK_DNE
884 #define UIDLE UIE_bits.UIDLE
885 #define STALL UIE_bits.STALL
887 // ----- USTAT bits --------------------
893 unsigned char ENDP0:1;
894 unsigned char ENDP1:1;
900 extern volatile __USTAT_bits_t __at(USTAT_ADDR) USTAT_bits;
902 #define IN USTAT_bits.IN
903 #define ENDP0 USTAT_bits.ENDP0
904 #define ENDP1 USTAT_bits.ENDP1