2 // Register Declarations for Microchip 16C73B Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRES_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define PR2_ADDR 0x0092
66 #define SSPADD_ADDR 0x0093
67 #define SSPSTAT_ADDR 0x0094
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define ADCON1_ADDR 0x009F
73 // Memory organization.
76 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
77 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
78 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
79 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
80 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
81 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
82 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
83 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
84 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
85 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
86 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
87 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
88 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
89 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
90 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
91 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
92 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
93 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
94 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
95 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
96 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
97 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
98 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
99 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
100 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
101 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
102 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
103 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
104 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
105 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
106 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
107 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
108 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
109 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
110 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
111 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
112 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
113 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
114 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
115 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
116 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
117 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
118 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
122 // P16C73B.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
125 // This header file defines configurations, registers, and other useful bits of
126 // information for the PIC16C73B microcontroller. These names are taken to match
127 // the data sheets as closely as possible.
129 // Note that the processor must be selected before this file is
130 // included. The processor may be selected the following ways:
132 // 1. Command line switch:
133 // C:\ MPASM MYFILE.ASM /PIC16C73B
134 // 2. LIST directive in the source file
136 // 3. Processor Type entry in the MPASM full-screen interface
138 //==========================================================================
142 //==========================================================================
146 //1.00 17/12/97 Initial Release
148 //==========================================================================
152 //==========================================================================
155 // MESSG "Processor-header file mismatch. Verify selected processor."
158 //==========================================================================
160 // Register Definitions
162 //==========================================================================
167 //----- Register Files------------------------------------------------------
169 extern __data __at (INDF_ADDR) volatile char INDF;
170 extern __sfr __at (TMR0_ADDR) TMR0;
171 extern __data __at (PCL_ADDR) volatile char PCL;
172 extern __sfr __at (STATUS_ADDR) STATUS;
173 extern __sfr __at (FSR_ADDR) FSR;
174 extern __sfr __at (PORTA_ADDR) PORTA;
175 extern __sfr __at (PORTB_ADDR) PORTB;
176 extern __sfr __at (PORTC_ADDR) PORTC;
177 extern __sfr __at (PCLATH_ADDR) PCLATH;
178 extern __sfr __at (INTCON_ADDR) INTCON;
179 extern __sfr __at (PIR1_ADDR) PIR1;
180 extern __sfr __at (PIR2_ADDR) PIR2;
181 extern __sfr __at (TMR1L_ADDR) TMR1L;
182 extern __sfr __at (TMR1H_ADDR) TMR1H;
183 extern __sfr __at (T1CON_ADDR) T1CON;
184 extern __sfr __at (TMR2_ADDR) TMR2;
185 extern __sfr __at (T2CON_ADDR) T2CON;
186 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
187 extern __sfr __at (SSPCON_ADDR) SSPCON;
188 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
189 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
190 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
191 extern __sfr __at (RCSTA_ADDR) RCSTA;
192 extern __sfr __at (TXREG_ADDR) TXREG;
193 extern __sfr __at (RCREG_ADDR) RCREG;
194 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
195 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
196 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
197 extern __sfr __at (ADRES_ADDR) ADRES;
198 extern __sfr __at (ADCON0_ADDR) ADCON0;
200 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
201 extern __sfr __at (TRISA_ADDR) TRISA;
202 extern __sfr __at (TRISB_ADDR) TRISB;
203 extern __sfr __at (TRISC_ADDR) TRISC;
204 extern __sfr __at (PIE1_ADDR) PIE1;
205 extern __sfr __at (PIE2_ADDR) PIE2;
206 extern __sfr __at (PCON_ADDR) PCON;
207 extern __sfr __at (PR2_ADDR) PR2;
208 extern __sfr __at (SSPADD_ADDR) SSPADD;
209 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
210 extern __sfr __at (TXSTA_ADDR) TXSTA;
211 extern __sfr __at (SPBRG_ADDR) SPBRG;
212 extern __sfr __at (ADCON1_ADDR) ADCON1;
214 //----- STATUS Bits --------------------------------------------------------
217 //----- INTCON Bits --------------------------------------------------------
220 //----- PIR1 Bits ----------------------------------------------------------
223 //----- PIR2 Bits ----------------------------------------------------------
226 //----- T1CON Bits ---------------------------------------------------------
229 //----- T2CON Bits ---------------------------------------------------------
232 //----- SSPCON Bits --------------------------------------------------------
235 //----- CCP1CON Bits -------------------------------------------------------
238 //----- RCSTA Bits ---------------------------------------------------------
241 //----- CCP2CON Bits -------------------------------------------------------
244 //----- ADCON0 Bits --------------------------------------------------------
247 //----- OPTION Bits --------------------------------------------------------
250 //----- PIE1 Bits ----------------------------------------------------------
253 //----- PIE2 Bits ----------------------------------------------------------
256 //----- PCON Bits ----------------------------------------------------------
259 //----- SSPSTAT Bits -------------------------------------------------------
262 //----- TXSTA Bits ---------------------------------------------------------
265 //----- ADCON1 Bits --------------------------------------------------------
268 //==========================================================================
272 //==========================================================================
275 // __BADRAM H'08'-H'09'
276 // __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E'
278 //==========================================================================
280 // Configuration Bits
282 //==========================================================================
284 #define _BODEN_ON 0x3FFF
285 #define _BODEN_OFF 0x3FBF
286 #define _CP_ALL 0x00CF
287 #define _CP_75 0x15DF
288 #define _CP_50 0x2AEF
289 #define _CP_OFF 0x3FFF
290 #define _PWRTE_OFF 0x3FFF
291 #define _PWRTE_ON 0x3FF7
292 #define _WDT_ON 0x3FFF
293 #define _WDT_OFF 0x3FFB
294 #define _LP_OSC 0x3FFC
295 #define _XT_OSC 0x3FFD
296 #define _HS_OSC 0x3FFE
297 #define _RC_OSC 0x3FFF
301 // ----- ADCON0 bits --------------------
304 unsigned char ADON:1;
307 unsigned char CHS0:1;
308 unsigned char CHS1:1;
309 unsigned char CHS2:1;
310 unsigned char ADCS0:1;
311 unsigned char ADCS1:1;
316 unsigned char NOT_DONE:1;
326 unsigned char GO_DONE:1;
334 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
336 #define ADON ADCON0_bits.ADON
337 #define GO ADCON0_bits.GO
338 #define NOT_DONE ADCON0_bits.NOT_DONE
339 #define GO_DONE ADCON0_bits.GO_DONE
340 #define CHS0 ADCON0_bits.CHS0
341 #define CHS1 ADCON0_bits.CHS1
342 #define CHS2 ADCON0_bits.CHS2
343 #define ADCS0 ADCON0_bits.ADCS0
344 #define ADCS1 ADCON0_bits.ADCS1
346 // ----- ADCON1 bits --------------------
349 unsigned char PCFG0:1;
350 unsigned char PCFG1:1;
351 unsigned char PCFG2:1;
359 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
361 #define PCFG0 ADCON1_bits.PCFG0
362 #define PCFG1 ADCON1_bits.PCFG1
363 #define PCFG2 ADCON1_bits.PCFG2
365 // ----- CCP1CON bits --------------------
368 unsigned char CCP1M0:1;
369 unsigned char CCP1M1:1;
370 unsigned char CCP1M2:1;
371 unsigned char CCP1M3:1;
372 unsigned char CCP1Y:1;
373 unsigned char CCP1X:1;
378 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
380 #define CCP1M0 CCP1CON_bits.CCP1M0
381 #define CCP1M1 CCP1CON_bits.CCP1M1
382 #define CCP1M2 CCP1CON_bits.CCP1M2
383 #define CCP1M3 CCP1CON_bits.CCP1M3
384 #define CCP1Y CCP1CON_bits.CCP1Y
385 #define CCP1X CCP1CON_bits.CCP1X
387 // ----- CCP2CON bits --------------------
390 unsigned char CCP2M0:1;
391 unsigned char CCP2M1:1;
392 unsigned char CCP2M2:1;
393 unsigned char CCP2M3:1;
394 unsigned char CCP2Y:1;
395 unsigned char CCP2X:1;
400 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
402 #define CCP2M0 CCP2CON_bits.CCP2M0
403 #define CCP2M1 CCP2CON_bits.CCP2M1
404 #define CCP2M2 CCP2CON_bits.CCP2M2
405 #define CCP2M3 CCP2CON_bits.CCP2M3
406 #define CCP2Y CCP2CON_bits.CCP2Y
407 #define CCP2X CCP2CON_bits.CCP2X
409 // ----- INTCON bits --------------------
412 unsigned char RBIF:1;
413 unsigned char INTF:1;
414 unsigned char T0IF:1;
415 unsigned char RBIE:1;
416 unsigned char INTE:1;
417 unsigned char T0IE:1;
418 unsigned char PEIE:1;
422 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
424 #define RBIF INTCON_bits.RBIF
425 #define INTF INTCON_bits.INTF
426 #define T0IF INTCON_bits.T0IF
427 #define RBIE INTCON_bits.RBIE
428 #define INTE INTCON_bits.INTE
429 #define T0IE INTCON_bits.T0IE
430 #define PEIE INTCON_bits.PEIE
431 #define GIE INTCON_bits.GIE
433 // ----- OPTION_REG bits --------------------
440 unsigned char T0SE:1;
441 unsigned char T0CS:1;
442 unsigned char INTEDG:1;
443 unsigned char NOT_RBPU:1;
445 } __OPTION_REG_bits_t;
446 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
448 #define PS0 OPTION_REG_bits.PS0
449 #define PS1 OPTION_REG_bits.PS1
450 #define PS2 OPTION_REG_bits.PS2
451 #define PSA OPTION_REG_bits.PSA
452 #define T0SE OPTION_REG_bits.T0SE
453 #define T0CS OPTION_REG_bits.T0CS
454 #define INTEDG OPTION_REG_bits.INTEDG
455 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
457 // ----- PCON bits --------------------
460 unsigned char NOT_BO:1;
461 unsigned char NOT_POR:1;
470 unsigned char NOT_BOR:1;
480 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
482 #define NOT_BO PCON_bits.NOT_BO
483 #define NOT_BOR PCON_bits.NOT_BOR
484 #define NOT_POR PCON_bits.NOT_POR
486 // ----- PIE1 bits --------------------
489 unsigned char TMR1IE:1;
490 unsigned char TMR2IE:1;
491 unsigned char CCP1IE:1;
492 unsigned char SSPIE:1;
493 unsigned char TXIE:1;
494 unsigned char RCIE:1;
495 unsigned char ADIE:1;
499 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
501 #define TMR1IE PIE1_bits.TMR1IE
502 #define TMR2IE PIE1_bits.TMR2IE
503 #define CCP1IE PIE1_bits.CCP1IE
504 #define SSPIE PIE1_bits.SSPIE
505 #define TXIE PIE1_bits.TXIE
506 #define RCIE PIE1_bits.RCIE
507 #define ADIE PIE1_bits.ADIE
509 // ----- PIE2 bits --------------------
512 unsigned char CCP2IE:1;
522 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
524 #define CCP2IE PIE2_bits.CCP2IE
526 // ----- PIR1 bits --------------------
529 unsigned char TMR1IF:1;
530 unsigned char TMR2IF:1;
531 unsigned char CCP1IF:1;
532 unsigned char SSPIF:1;
533 unsigned char TXIF:1;
534 unsigned char RCIF:1;
535 unsigned char ADIF:1;
539 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
541 #define TMR1IF PIR1_bits.TMR1IF
542 #define TMR2IF PIR1_bits.TMR2IF
543 #define CCP1IF PIR1_bits.CCP1IF
544 #define SSPIF PIR1_bits.SSPIF
545 #define TXIF PIR1_bits.TXIF
546 #define RCIF PIR1_bits.RCIF
547 #define ADIF PIR1_bits.ADIF
549 // ----- PIR2 bits --------------------
552 unsigned char CCP2IF:1;
562 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
564 #define CCP2IF PIR2_bits.CCP2IF
566 // ----- RCSTA bits --------------------
569 unsigned char RX9D:1;
570 unsigned char OERR:1;
571 unsigned char FERR:1;
573 unsigned char CREN:1;
574 unsigned char SREN:1;
576 unsigned char SPEN:1;
579 unsigned char RCD8:1;
595 unsigned char NOT_RC8:1;
605 unsigned char RC8_9:1;
609 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
611 #define RX9D RCSTA_bits.RX9D
612 #define RCD8 RCSTA_bits.RCD8
613 #define OERR RCSTA_bits.OERR
614 #define FERR RCSTA_bits.FERR
615 #define CREN RCSTA_bits.CREN
616 #define SREN RCSTA_bits.SREN
617 #define RX9 RCSTA_bits.RX9
618 #define RC9 RCSTA_bits.RC9
619 #define NOT_RC8 RCSTA_bits.NOT_RC8
620 #define RC8_9 RCSTA_bits.RC8_9
621 #define SPEN RCSTA_bits.SPEN
623 // ----- SSPCON bits --------------------
626 unsigned char SSPM0:1;
627 unsigned char SSPM1:1;
628 unsigned char SSPM2:1;
629 unsigned char SSPM3:1;
631 unsigned char SSPEN:1;
632 unsigned char SSPOV:1;
633 unsigned char WCOL:1;
636 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
638 #define SSPM0 SSPCON_bits.SSPM0
639 #define SSPM1 SSPCON_bits.SSPM1
640 #define SSPM2 SSPCON_bits.SSPM2
641 #define SSPM3 SSPCON_bits.SSPM3
642 #define CKP SSPCON_bits.CKP
643 #define SSPEN SSPCON_bits.SSPEN
644 #define SSPOV SSPCON_bits.SSPOV
645 #define WCOL SSPCON_bits.WCOL
647 // ----- SSPSTAT bits --------------------
662 unsigned char I2C_READ:1;
663 unsigned char I2C_START:1;
664 unsigned char I2C_STOP:1;
665 unsigned char I2C_DATA:1;
672 unsigned char NOT_W:1;
675 unsigned char NOT_A:1;
682 unsigned char NOT_WRITE:1;
685 unsigned char NOT_ADDRESS:1;
702 unsigned char READ_WRITE:1;
705 unsigned char DATA_ADDRESS:1;
710 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
712 #define BF SSPSTAT_bits.BF
713 #define UA SSPSTAT_bits.UA
714 #define R SSPSTAT_bits.R
715 #define I2C_READ SSPSTAT_bits.I2C_READ
716 #define NOT_W SSPSTAT_bits.NOT_W
717 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
718 #define R_W SSPSTAT_bits.R_W
719 #define READ_WRITE SSPSTAT_bits.READ_WRITE
720 #define S SSPSTAT_bits.S
721 #define I2C_START SSPSTAT_bits.I2C_START
722 #define P SSPSTAT_bits.P
723 #define I2C_STOP SSPSTAT_bits.I2C_STOP
724 #define D SSPSTAT_bits.D
725 #define I2C_DATA SSPSTAT_bits.I2C_DATA
726 #define NOT_A SSPSTAT_bits.NOT_A
727 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
728 #define D_A SSPSTAT_bits.D_A
729 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
730 #define CKE SSPSTAT_bits.CKE
731 #define SMP SSPSTAT_bits.SMP
733 // ----- STATUS bits --------------------
739 unsigned char NOT_PD:1;
740 unsigned char NOT_TO:1;
746 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
748 #define C STATUS_bits.C
749 #define DC STATUS_bits.DC
750 #define Z STATUS_bits.Z
751 #define NOT_PD STATUS_bits.NOT_PD
752 #define NOT_TO STATUS_bits.NOT_TO
753 #define RP0 STATUS_bits.RP0
754 #define RP1 STATUS_bits.RP1
755 #define IRP STATUS_bits.IRP
757 // ----- T1CON bits --------------------
760 unsigned char TMR1ON:1;
761 unsigned char TMR1CS:1;
762 unsigned char NOT_T1SYNC:1;
763 unsigned char T1OSCEN:1;
764 unsigned char T1CKPS0:1;
765 unsigned char T1CKPS1:1;
772 unsigned char T1INSYNC:1;
780 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
782 #define TMR1ON T1CON_bits.TMR1ON
783 #define TMR1CS T1CON_bits.TMR1CS
784 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
785 #define T1INSYNC T1CON_bits.T1INSYNC
786 #define T1OSCEN T1CON_bits.T1OSCEN
787 #define T1CKPS0 T1CON_bits.T1CKPS0
788 #define T1CKPS1 T1CON_bits.T1CKPS1
790 // ----- T2CON bits --------------------
793 unsigned char T2CKPS0:1;
794 unsigned char T2CKPS1:1;
795 unsigned char TMR2ON:1;
796 unsigned char TOUTPS0:1;
797 unsigned char TOUTPS1:1;
798 unsigned char TOUTPS2:1;
799 unsigned char TOUTPS3:1;
803 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
805 #define T2CKPS0 T2CON_bits.T2CKPS0
806 #define T2CKPS1 T2CON_bits.T2CKPS1
807 #define TMR2ON T2CON_bits.TMR2ON
808 #define TOUTPS0 T2CON_bits.TOUTPS0
809 #define TOUTPS1 T2CON_bits.TOUTPS1
810 #define TOUTPS2 T2CON_bits.TOUTPS2
811 #define TOUTPS3 T2CON_bits.TOUTPS3
813 // ----- TXSTA bits --------------------
816 unsigned char TX9D:1;
817 unsigned char TRMT:1;
818 unsigned char BRGH:1;
820 unsigned char SYNC:1;
821 unsigned char TXEN:1;
823 unsigned char CSRC:1;
826 unsigned char TXD8:1;
832 unsigned char NOT_TX8:1;
842 unsigned char TX8_9:1;
846 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
848 #define TX9D TXSTA_bits.TX9D
849 #define TXD8 TXSTA_bits.TXD8
850 #define TRMT TXSTA_bits.TRMT
851 #define BRGH TXSTA_bits.BRGH
852 #define SYNC TXSTA_bits.SYNC
853 #define TXEN TXSTA_bits.TXEN
854 #define TX9 TXSTA_bits.TX9
855 #define NOT_TX8 TXSTA_bits.NOT_TX8
856 #define TX8_9 TXSTA_bits.TX8_9
857 #define CSRC TXSTA_bits.CSRC