2 // Register Declarations for Microchip 16C73B Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define ADRES_ADDR 0x001E
57 #define ADCON0_ADDR 0x001F
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define PIE1_ADDR 0x008C
63 #define PIE2_ADDR 0x008D
64 #define PCON_ADDR 0x008E
65 #define PR2_ADDR 0x0092
66 #define SSPADD_ADDR 0x0093
67 #define SSPSTAT_ADDR 0x0094
68 #define TXSTA_ADDR 0x0098
69 #define SPBRG_ADDR 0x0099
70 #define ADCON1_ADDR 0x009F
73 // Memory organization.
79 // P16C73B.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
82 // This header file defines configurations, registers, and other useful bits of
83 // information for the PIC16C73B microcontroller. These names are taken to match
84 // the data sheets as closely as possible.
86 // Note that the processor must be selected before this file is
87 // included. The processor may be selected the following ways:
89 // 1. Command line switch:
90 // C:\ MPASM MYFILE.ASM /PIC16C73B
91 // 2. LIST directive in the source file
93 // 3. Processor Type entry in the MPASM full-screen interface
95 //==========================================================================
99 //==========================================================================
103 //1.00 17/12/97 Initial Release
105 //==========================================================================
109 //==========================================================================
112 // MESSG "Processor-header file mismatch. Verify selected processor."
115 //==========================================================================
117 // Register Definitions
119 //==========================================================================
124 //----- Register Files------------------------------------------------------
126 extern __data __at (INDF_ADDR) volatile char INDF;
127 extern __sfr __at (TMR0_ADDR) TMR0;
128 extern __data __at (PCL_ADDR) volatile char PCL;
129 extern __sfr __at (STATUS_ADDR) STATUS;
130 extern __sfr __at (FSR_ADDR) FSR;
131 extern __sfr __at (PORTA_ADDR) PORTA;
132 extern __sfr __at (PORTB_ADDR) PORTB;
133 extern __sfr __at (PORTC_ADDR) PORTC;
134 extern __sfr __at (PCLATH_ADDR) PCLATH;
135 extern __sfr __at (INTCON_ADDR) INTCON;
136 extern __sfr __at (PIR1_ADDR) PIR1;
137 extern __sfr __at (PIR2_ADDR) PIR2;
138 extern __sfr __at (TMR1L_ADDR) TMR1L;
139 extern __sfr __at (TMR1H_ADDR) TMR1H;
140 extern __sfr __at (T1CON_ADDR) T1CON;
141 extern __sfr __at (TMR2_ADDR) TMR2;
142 extern __sfr __at (T2CON_ADDR) T2CON;
143 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
144 extern __sfr __at (SSPCON_ADDR) SSPCON;
145 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
146 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
147 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
148 extern __sfr __at (RCSTA_ADDR) RCSTA;
149 extern __sfr __at (TXREG_ADDR) TXREG;
150 extern __sfr __at (RCREG_ADDR) RCREG;
151 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
152 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
153 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
154 extern __sfr __at (ADRES_ADDR) ADRES;
155 extern __sfr __at (ADCON0_ADDR) ADCON0;
157 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
158 extern __sfr __at (TRISA_ADDR) TRISA;
159 extern __sfr __at (TRISB_ADDR) TRISB;
160 extern __sfr __at (TRISC_ADDR) TRISC;
161 extern __sfr __at (PIE1_ADDR) PIE1;
162 extern __sfr __at (PIE2_ADDR) PIE2;
163 extern __sfr __at (PCON_ADDR) PCON;
164 extern __sfr __at (PR2_ADDR) PR2;
165 extern __sfr __at (SSPADD_ADDR) SSPADD;
166 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
167 extern __sfr __at (TXSTA_ADDR) TXSTA;
168 extern __sfr __at (SPBRG_ADDR) SPBRG;
169 extern __sfr __at (ADCON1_ADDR) ADCON1;
171 //----- STATUS Bits --------------------------------------------------------
174 //----- INTCON Bits --------------------------------------------------------
177 //----- PIR1 Bits ----------------------------------------------------------
180 //----- PIR2 Bits ----------------------------------------------------------
183 //----- T1CON Bits ---------------------------------------------------------
186 //----- T2CON Bits ---------------------------------------------------------
189 //----- SSPCON Bits --------------------------------------------------------
192 //----- CCP1CON Bits -------------------------------------------------------
195 //----- RCSTA Bits ---------------------------------------------------------
198 //----- CCP2CON Bits -------------------------------------------------------
201 //----- ADCON0 Bits --------------------------------------------------------
204 //----- OPTION Bits --------------------------------------------------------
207 //----- PIE1 Bits ----------------------------------------------------------
210 //----- PIE2 Bits ----------------------------------------------------------
213 //----- PCON Bits ----------------------------------------------------------
216 //----- SSPSTAT Bits -------------------------------------------------------
219 //----- TXSTA Bits ---------------------------------------------------------
222 //----- ADCON1 Bits --------------------------------------------------------
225 //==========================================================================
229 //==========================================================================
232 // __BADRAM H'08'-H'09'
233 // __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9E'
235 //==========================================================================
237 // Configuration Bits
239 //==========================================================================
241 #define _BODEN_ON 0x3FFF
242 #define _BODEN_OFF 0x3FBF
243 #define _CP_ALL 0x00CF
244 #define _CP_75 0x15DF
245 #define _CP_50 0x2AEF
246 #define _CP_OFF 0x3FFF
247 #define _PWRTE_OFF 0x3FFF
248 #define _PWRTE_ON 0x3FF7
249 #define _WDT_ON 0x3FFF
250 #define _WDT_OFF 0x3FFB
251 #define _LP_OSC 0x3FFC
252 #define _XT_OSC 0x3FFD
253 #define _HS_OSC 0x3FFE
254 #define _RC_OSC 0x3FFF
258 // ----- ADCON0 bits --------------------
261 unsigned char ADON:1;
264 unsigned char CHS0:1;
265 unsigned char CHS1:1;
266 unsigned char CHS2:1;
267 unsigned char ADCS0:1;
268 unsigned char ADCS1:1;
273 unsigned char NOT_DONE:1;
283 unsigned char GO_DONE:1;
291 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
293 #define ADON ADCON0_bits.ADON
294 #define GO ADCON0_bits.GO
295 #define NOT_DONE ADCON0_bits.NOT_DONE
296 #define GO_DONE ADCON0_bits.GO_DONE
297 #define CHS0 ADCON0_bits.CHS0
298 #define CHS1 ADCON0_bits.CHS1
299 #define CHS2 ADCON0_bits.CHS2
300 #define ADCS0 ADCON0_bits.ADCS0
301 #define ADCS1 ADCON0_bits.ADCS1
303 // ----- ADCON1 bits --------------------
306 unsigned char PCFG0:1;
307 unsigned char PCFG1:1;
308 unsigned char PCFG2:1;
316 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
318 #define PCFG0 ADCON1_bits.PCFG0
319 #define PCFG1 ADCON1_bits.PCFG1
320 #define PCFG2 ADCON1_bits.PCFG2
322 // ----- CCP1CON bits --------------------
325 unsigned char CCP1M0:1;
326 unsigned char CCP1M1:1;
327 unsigned char CCP1M2:1;
328 unsigned char CCP1M3:1;
329 unsigned char CCP1Y:1;
330 unsigned char CCP1X:1;
335 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
337 #define CCP1M0 CCP1CON_bits.CCP1M0
338 #define CCP1M1 CCP1CON_bits.CCP1M1
339 #define CCP1M2 CCP1CON_bits.CCP1M2
340 #define CCP1M3 CCP1CON_bits.CCP1M3
341 #define CCP1Y CCP1CON_bits.CCP1Y
342 #define CCP1X CCP1CON_bits.CCP1X
344 // ----- CCP2CON bits --------------------
347 unsigned char CCP2M0:1;
348 unsigned char CCP2M1:1;
349 unsigned char CCP2M2:1;
350 unsigned char CCP2M3:1;
351 unsigned char CCP2Y:1;
352 unsigned char CCP2X:1;
357 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
359 #define CCP2M0 CCP2CON_bits.CCP2M0
360 #define CCP2M1 CCP2CON_bits.CCP2M1
361 #define CCP2M2 CCP2CON_bits.CCP2M2
362 #define CCP2M3 CCP2CON_bits.CCP2M3
363 #define CCP2Y CCP2CON_bits.CCP2Y
364 #define CCP2X CCP2CON_bits.CCP2X
366 // ----- INTCON bits --------------------
369 unsigned char RBIF:1;
370 unsigned char INTF:1;
371 unsigned char T0IF:1;
372 unsigned char RBIE:1;
373 unsigned char INTE:1;
374 unsigned char T0IE:1;
375 unsigned char PEIE:1;
379 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
381 #define RBIF INTCON_bits.RBIF
382 #define INTF INTCON_bits.INTF
383 #define T0IF INTCON_bits.T0IF
384 #define RBIE INTCON_bits.RBIE
385 #define INTE INTCON_bits.INTE
386 #define T0IE INTCON_bits.T0IE
387 #define PEIE INTCON_bits.PEIE
388 #define GIE INTCON_bits.GIE
390 // ----- OPTION_REG bits --------------------
397 unsigned char T0SE:1;
398 unsigned char T0CS:1;
399 unsigned char INTEDG:1;
400 unsigned char NOT_RBPU:1;
402 } __OPTION_REG_bits_t;
403 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
405 #define PS0 OPTION_REG_bits.PS0
406 #define PS1 OPTION_REG_bits.PS1
407 #define PS2 OPTION_REG_bits.PS2
408 #define PSA OPTION_REG_bits.PSA
409 #define T0SE OPTION_REG_bits.T0SE
410 #define T0CS OPTION_REG_bits.T0CS
411 #define INTEDG OPTION_REG_bits.INTEDG
412 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
414 // ----- PCON bits --------------------
417 unsigned char NOT_BO:1;
418 unsigned char NOT_POR:1;
427 unsigned char NOT_BOR:1;
437 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
439 #define NOT_BO PCON_bits.NOT_BO
440 #define NOT_BOR PCON_bits.NOT_BOR
441 #define NOT_POR PCON_bits.NOT_POR
443 // ----- PIE1 bits --------------------
446 unsigned char TMR1IE:1;
447 unsigned char TMR2IE:1;
448 unsigned char CCP1IE:1;
449 unsigned char SSPIE:1;
450 unsigned char TXIE:1;
451 unsigned char RCIE:1;
452 unsigned char ADIE:1;
456 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
458 #define TMR1IE PIE1_bits.TMR1IE
459 #define TMR2IE PIE1_bits.TMR2IE
460 #define CCP1IE PIE1_bits.CCP1IE
461 #define SSPIE PIE1_bits.SSPIE
462 #define TXIE PIE1_bits.TXIE
463 #define RCIE PIE1_bits.RCIE
464 #define ADIE PIE1_bits.ADIE
466 // ----- PIE2 bits --------------------
469 unsigned char CCP2IE:1;
479 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
481 #define CCP2IE PIE2_bits.CCP2IE
483 // ----- PIR1 bits --------------------
486 unsigned char TMR1IF:1;
487 unsigned char TMR2IF:1;
488 unsigned char CCP1IF:1;
489 unsigned char SSPIF:1;
490 unsigned char TXIF:1;
491 unsigned char RCIF:1;
492 unsigned char ADIF:1;
496 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
498 #define TMR1IF PIR1_bits.TMR1IF
499 #define TMR2IF PIR1_bits.TMR2IF
500 #define CCP1IF PIR1_bits.CCP1IF
501 #define SSPIF PIR1_bits.SSPIF
502 #define TXIF PIR1_bits.TXIF
503 #define RCIF PIR1_bits.RCIF
504 #define ADIF PIR1_bits.ADIF
506 // ----- PIR2 bits --------------------
509 unsigned char CCP2IF:1;
519 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
521 #define CCP2IF PIR2_bits.CCP2IF
523 // ----- RCSTA bits --------------------
526 unsigned char RX9D:1;
527 unsigned char OERR:1;
528 unsigned char FERR:1;
530 unsigned char CREN:1;
531 unsigned char SREN:1;
533 unsigned char SPEN:1;
536 unsigned char RCD8:1;
552 unsigned char NOT_RC8:1;
562 unsigned char RC8_9:1;
566 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
568 #define RX9D RCSTA_bits.RX9D
569 #define RCD8 RCSTA_bits.RCD8
570 #define OERR RCSTA_bits.OERR
571 #define FERR RCSTA_bits.FERR
572 #define CREN RCSTA_bits.CREN
573 #define SREN RCSTA_bits.SREN
574 #define RX9 RCSTA_bits.RX9
575 #define RC9 RCSTA_bits.RC9
576 #define NOT_RC8 RCSTA_bits.NOT_RC8
577 #define RC8_9 RCSTA_bits.RC8_9
578 #define SPEN RCSTA_bits.SPEN
580 // ----- SSPCON bits --------------------
583 unsigned char SSPM0:1;
584 unsigned char SSPM1:1;
585 unsigned char SSPM2:1;
586 unsigned char SSPM3:1;
588 unsigned char SSPEN:1;
589 unsigned char SSPOV:1;
590 unsigned char WCOL:1;
593 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
595 #define SSPM0 SSPCON_bits.SSPM0
596 #define SSPM1 SSPCON_bits.SSPM1
597 #define SSPM2 SSPCON_bits.SSPM2
598 #define SSPM3 SSPCON_bits.SSPM3
599 #define CKP SSPCON_bits.CKP
600 #define SSPEN SSPCON_bits.SSPEN
601 #define SSPOV SSPCON_bits.SSPOV
602 #define WCOL SSPCON_bits.WCOL
604 // ----- SSPSTAT bits --------------------
619 unsigned char I2C_READ:1;
620 unsigned char I2C_START:1;
621 unsigned char I2C_STOP:1;
622 unsigned char I2C_DATA:1;
629 unsigned char NOT_W:1;
632 unsigned char NOT_A:1;
639 unsigned char NOT_WRITE:1;
642 unsigned char NOT_ADDRESS:1;
659 unsigned char READ_WRITE:1;
662 unsigned char DATA_ADDRESS:1;
667 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
669 #define BF SSPSTAT_bits.BF
670 #define UA SSPSTAT_bits.UA
671 #define R SSPSTAT_bits.R
672 #define I2C_READ SSPSTAT_bits.I2C_READ
673 #define NOT_W SSPSTAT_bits.NOT_W
674 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
675 #define R_W SSPSTAT_bits.R_W
676 #define READ_WRITE SSPSTAT_bits.READ_WRITE
677 #define S SSPSTAT_bits.S
678 #define I2C_START SSPSTAT_bits.I2C_START
679 #define P SSPSTAT_bits.P
680 #define I2C_STOP SSPSTAT_bits.I2C_STOP
681 #define D SSPSTAT_bits.D
682 #define I2C_DATA SSPSTAT_bits.I2C_DATA
683 #define NOT_A SSPSTAT_bits.NOT_A
684 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
685 #define D_A SSPSTAT_bits.D_A
686 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
687 #define CKE SSPSTAT_bits.CKE
688 #define SMP SSPSTAT_bits.SMP
690 // ----- STATUS bits --------------------
696 unsigned char NOT_PD:1;
697 unsigned char NOT_TO:1;
703 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
705 #define C STATUS_bits.C
706 #define DC STATUS_bits.DC
707 #define Z STATUS_bits.Z
708 #define NOT_PD STATUS_bits.NOT_PD
709 #define NOT_TO STATUS_bits.NOT_TO
710 #define RP0 STATUS_bits.RP0
711 #define RP1 STATUS_bits.RP1
712 #define IRP STATUS_bits.IRP
714 // ----- T1CON bits --------------------
717 unsigned char TMR1ON:1;
718 unsigned char TMR1CS:1;
719 unsigned char NOT_T1SYNC:1;
720 unsigned char T1OSCEN:1;
721 unsigned char T1CKPS0:1;
722 unsigned char T1CKPS1:1;
729 unsigned char T1INSYNC:1;
737 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
739 #define TMR1ON T1CON_bits.TMR1ON
740 #define TMR1CS T1CON_bits.TMR1CS
741 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
742 #define T1INSYNC T1CON_bits.T1INSYNC
743 #define T1OSCEN T1CON_bits.T1OSCEN
744 #define T1CKPS0 T1CON_bits.T1CKPS0
745 #define T1CKPS1 T1CON_bits.T1CKPS1
747 // ----- T2CON bits --------------------
750 unsigned char T2CKPS0:1;
751 unsigned char T2CKPS1:1;
752 unsigned char TMR2ON:1;
753 unsigned char TOUTPS0:1;
754 unsigned char TOUTPS1:1;
755 unsigned char TOUTPS2:1;
756 unsigned char TOUTPS3:1;
760 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
762 #define T2CKPS0 T2CON_bits.T2CKPS0
763 #define T2CKPS1 T2CON_bits.T2CKPS1
764 #define TMR2ON T2CON_bits.TMR2ON
765 #define TOUTPS0 T2CON_bits.TOUTPS0
766 #define TOUTPS1 T2CON_bits.TOUTPS1
767 #define TOUTPS2 T2CON_bits.TOUTPS2
768 #define TOUTPS3 T2CON_bits.TOUTPS3
770 // ----- TXSTA bits --------------------
773 unsigned char TX9D:1;
774 unsigned char TRMT:1;
775 unsigned char BRGH:1;
777 unsigned char SYNC:1;
778 unsigned char TXEN:1;
780 unsigned char CSRC:1;
783 unsigned char TXD8:1;
789 unsigned char NOT_TX8:1;
799 unsigned char TX8_9:1;
803 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
805 #define TX9D TXSTA_bits.TX9D
806 #define TXD8 TXSTA_bits.TXD8
807 #define TRMT TXSTA_bits.TRMT
808 #define BRGH TXSTA_bits.BRGH
809 #define SYNC TXSTA_bits.SYNC
810 #define TXEN TXSTA_bits.TXEN
811 #define TX9 TXSTA_bits.TX9
812 #define NOT_TX8 TXSTA_bits.NOT_TX8
813 #define TX8_9 TXSTA_bits.TX8_9
814 #define CSRC TXSTA_bits.CSRC