2 // Register Declarations for Microchip 16C72 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define ADRES_ADDR 0x001E
50 #define ADCON0_ADDR 0x001F
51 #define OPTION_REG_ADDR 0x0081
52 #define TRISA_ADDR 0x0085
53 #define TRISB_ADDR 0x0086
54 #define TRISC_ADDR 0x0087
55 #define PIE1_ADDR 0x008C
56 #define PCON_ADDR 0x008E
57 #define PR2_ADDR 0x0092
58 #define SSPADD_ADDR 0x0093
59 #define SSPSTAT_ADDR 0x0094
60 #define ADCON1_ADDR 0x009F
63 // Memory organization.
66 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
67 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
68 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
69 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
70 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
71 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
72 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
73 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
74 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
75 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
76 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
77 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
78 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
79 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
80 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
81 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
82 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
83 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
84 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
85 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
86 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
87 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
88 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
89 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
90 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
91 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
92 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
93 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
94 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
95 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
96 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
97 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
98 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
102 // P16C72.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
105 // This header file defines configurations, registers, and other useful bits of
106 // information for the PIC16C72 microcontroller. These names are taken to match
107 // the data sheets as closely as possible.
109 // Note that the processor must be selected before this file is
110 // included. The processor may be selected the following ways:
112 // 1. Command line switch:
113 // C:\ MPASM MYFILE.ASM /PIC16C72
114 // 2. LIST directive in the source file
116 // 3. Processor Type entry in the MPASM full-screen interface
118 //==========================================================================
122 //==========================================================================
126 //1.01 11/28/95 Added NOT_BOR to match revised datasheet
127 //1.00 10/31/95 Initial Release
129 //==========================================================================
133 //==========================================================================
136 // MESSG "Processor-header file mismatch. Verify selected processor."
139 //==========================================================================
141 // Register Definitions
143 //==========================================================================
148 //----- Register Files------------------------------------------------------
150 extern __data __at (INDF_ADDR) volatile char INDF;
151 extern __sfr __at (TMR0_ADDR) TMR0;
152 extern __data __at (PCL_ADDR) volatile char PCL;
153 extern __sfr __at (STATUS_ADDR) STATUS;
154 extern __sfr __at (FSR_ADDR) FSR;
155 extern __sfr __at (PORTA_ADDR) PORTA;
156 extern __sfr __at (PORTB_ADDR) PORTB;
157 extern __sfr __at (PORTC_ADDR) PORTC;
158 extern __sfr __at (PCLATH_ADDR) PCLATH;
159 extern __sfr __at (INTCON_ADDR) INTCON;
160 extern __sfr __at (PIR1_ADDR) PIR1;
161 extern __sfr __at (TMR1L_ADDR) TMR1L;
162 extern __sfr __at (TMR1H_ADDR) TMR1H;
163 extern __sfr __at (T1CON_ADDR) T1CON;
164 extern __sfr __at (TMR2_ADDR) TMR2;
165 extern __sfr __at (T2CON_ADDR) T2CON;
166 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
167 extern __sfr __at (SSPCON_ADDR) SSPCON;
168 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
169 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
170 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
171 extern __sfr __at (ADRES_ADDR) ADRES;
172 extern __sfr __at (ADCON0_ADDR) ADCON0;
174 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
175 extern __sfr __at (TRISA_ADDR) TRISA;
176 extern __sfr __at (TRISB_ADDR) TRISB;
177 extern __sfr __at (TRISC_ADDR) TRISC;
178 extern __sfr __at (PIE1_ADDR) PIE1;
179 extern __sfr __at (PCON_ADDR) PCON;
180 extern __sfr __at (PR2_ADDR) PR2;
181 extern __sfr __at (SSPADD_ADDR) SSPADD;
182 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
183 extern __sfr __at (ADCON1_ADDR) ADCON1;
185 //----- STATUS Bits --------------------------------------------------------
188 //----- INTCON Bits --------------------------------------------------------
191 //----- PIR1 Bits ----------------------------------------------------------
194 //----- T1CON Bits ---------------------------------------------------------
197 //----- T2CON Bits ---------------------------------------------------------
200 //----- SSPCON Bits --------------------------------------------------------
203 //----- CCP1CON Bits -------------------------------------------------------
206 //----- ADCON0 Bits --------------------------------------------------------
209 //----- OPTION Bits --------------------------------------------------------
212 //----- PIE1 Bits ----------------------------------------------------------
215 //----- PCON Bits ----------------------------------------------------------
218 //----- SSPSTAT Bits -------------------------------------------------------
221 //----- ADCON1 Bits --------------------------------------------------------
224 //==========================================================================
228 //==========================================================================
231 // __BADRAM H'08'-H'09', H'0D', H'18'-H'1D'
232 // __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E'
234 //==========================================================================
236 // Configuration Bits
238 //==========================================================================
240 #define _BODEN_ON 0x3FFF
241 #define _BODEN_OFF 0x3FBF
242 #define _CP_ALL 0x00CF
243 #define _CP_75 0x15DF
244 #define _CP_50 0x2AEF
245 #define _CP_OFF 0x3FFF
246 #define _PWRTE_OFF 0x3FFF
247 #define _PWRTE_ON 0x3FF7
248 #define _WDT_ON 0x3FFF
249 #define _WDT_OFF 0x3FFB
250 #define _LP_OSC 0x3FFC
251 #define _XT_OSC 0x3FFD
252 #define _HS_OSC 0x3FFE
253 #define _RC_OSC 0x3FFF
257 // ----- ADCON0 bits --------------------
260 unsigned char ADON:1;
263 unsigned char CHS0:1;
264 unsigned char CHS1:1;
265 unsigned char CHS2:1;
266 unsigned char ADCS0:1;
267 unsigned char ADCS1:1;
272 unsigned char NOT_DONE:1;
282 unsigned char GO_DONE:1;
290 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
292 #define ADON ADCON0_bits.ADON
293 #define GO ADCON0_bits.GO
294 #define NOT_DONE ADCON0_bits.NOT_DONE
295 #define GO_DONE ADCON0_bits.GO_DONE
296 #define CHS0 ADCON0_bits.CHS0
297 #define CHS1 ADCON0_bits.CHS1
298 #define CHS2 ADCON0_bits.CHS2
299 #define ADCS0 ADCON0_bits.ADCS0
300 #define ADCS1 ADCON0_bits.ADCS1
302 // ----- ADCON1 bits --------------------
305 unsigned char PCFG0:1;
306 unsigned char PCFG1:1;
307 unsigned char PCFG2:1;
315 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
317 #define PCFG0 ADCON1_bits.PCFG0
318 #define PCFG1 ADCON1_bits.PCFG1
319 #define PCFG2 ADCON1_bits.PCFG2
321 // ----- CCP1CON bits --------------------
324 unsigned char CCP1M0:1;
325 unsigned char CCP1M1:1;
326 unsigned char CCP1M2:1;
327 unsigned char CCP1M3:1;
328 unsigned char CCP1Y:1;
329 unsigned char CCP1X:1;
334 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
336 #define CCP1M0 CCP1CON_bits.CCP1M0
337 #define CCP1M1 CCP1CON_bits.CCP1M1
338 #define CCP1M2 CCP1CON_bits.CCP1M2
339 #define CCP1M3 CCP1CON_bits.CCP1M3
340 #define CCP1Y CCP1CON_bits.CCP1Y
341 #define CCP1X CCP1CON_bits.CCP1X
343 // ----- INTCON bits --------------------
346 unsigned char RBIF:1;
347 unsigned char INTF:1;
348 unsigned char T0IF:1;
349 unsigned char RBIE:1;
350 unsigned char INTE:1;
351 unsigned char T0IE:1;
352 unsigned char PEIE:1;
356 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
358 #define RBIF INTCON_bits.RBIF
359 #define INTF INTCON_bits.INTF
360 #define T0IF INTCON_bits.T0IF
361 #define RBIE INTCON_bits.RBIE
362 #define INTE INTCON_bits.INTE
363 #define T0IE INTCON_bits.T0IE
364 #define PEIE INTCON_bits.PEIE
365 #define GIE INTCON_bits.GIE
367 // ----- OPTION_REG bits --------------------
374 unsigned char T0SE:1;
375 unsigned char T0CS:1;
376 unsigned char INTEDG:1;
377 unsigned char NOT_RBPU:1;
379 } __OPTION_REG_bits_t;
380 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
382 #define PS0 OPTION_REG_bits.PS0
383 #define PS1 OPTION_REG_bits.PS1
384 #define PS2 OPTION_REG_bits.PS2
385 #define PSA OPTION_REG_bits.PSA
386 #define T0SE OPTION_REG_bits.T0SE
387 #define T0CS OPTION_REG_bits.T0CS
388 #define INTEDG OPTION_REG_bits.INTEDG
389 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
391 // ----- PCON bits --------------------
394 unsigned char NOT_BO:1;
395 unsigned char NOT_POR:1;
404 unsigned char NOT_BOR:1;
414 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
416 #define NOT_BO PCON_bits.NOT_BO
417 #define NOT_BOR PCON_bits.NOT_BOR
418 #define NOT_POR PCON_bits.NOT_POR
420 // ----- PIE1 bits --------------------
423 unsigned char TMR1IE:1;
424 unsigned char TMR2IE:1;
425 unsigned char CCP1IE:1;
426 unsigned char SSPIE:1;
429 unsigned char ADIE:1;
433 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
435 #define TMR1IE PIE1_bits.TMR1IE
436 #define TMR2IE PIE1_bits.TMR2IE
437 #define CCP1IE PIE1_bits.CCP1IE
438 #define SSPIE PIE1_bits.SSPIE
439 #define ADIE PIE1_bits.ADIE
441 // ----- PIR1 bits --------------------
444 unsigned char TMR1IF:1;
445 unsigned char TMR2IF:1;
446 unsigned char CCP1IF:1;
447 unsigned char SSPIF:1;
450 unsigned char ADIF:1;
454 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
456 #define TMR1IF PIR1_bits.TMR1IF
457 #define TMR2IF PIR1_bits.TMR2IF
458 #define CCP1IF PIR1_bits.CCP1IF
459 #define SSPIF PIR1_bits.SSPIF
460 #define ADIF PIR1_bits.ADIF
462 // ----- SSPCON bits --------------------
465 unsigned char SSPM0:1;
466 unsigned char SSPM1:1;
467 unsigned char SSPM2:1;
468 unsigned char SSPM3:1;
470 unsigned char SSPEN:1;
471 unsigned char SSPOV:1;
472 unsigned char WCOL:1;
475 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
477 #define SSPM0 SSPCON_bits.SSPM0
478 #define SSPM1 SSPCON_bits.SSPM1
479 #define SSPM2 SSPCON_bits.SSPM2
480 #define SSPM3 SSPCON_bits.SSPM3
481 #define CKP SSPCON_bits.CKP
482 #define SSPEN SSPCON_bits.SSPEN
483 #define SSPOV SSPCON_bits.SSPOV
484 #define WCOL SSPCON_bits.WCOL
486 // ----- SSPSTAT bits --------------------
501 unsigned char I2C_READ:1;
502 unsigned char I2C_START:1;
503 unsigned char I2C_STOP:1;
504 unsigned char I2C_DATA:1;
511 unsigned char NOT_W:1;
514 unsigned char NOT_A:1;
521 unsigned char NOT_WRITE:1;
524 unsigned char NOT_ADDRESS:1;
541 unsigned char READ_WRITE:1;
544 unsigned char DATA_ADDRESS:1;
549 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
551 #define BF SSPSTAT_bits.BF
552 #define UA SSPSTAT_bits.UA
553 #define R SSPSTAT_bits.R
554 #define I2C_READ SSPSTAT_bits.I2C_READ
555 #define NOT_W SSPSTAT_bits.NOT_W
556 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
557 #define R_W SSPSTAT_bits.R_W
558 #define READ_WRITE SSPSTAT_bits.READ_WRITE
559 #define S SSPSTAT_bits.S
560 #define I2C_START SSPSTAT_bits.I2C_START
561 #define P SSPSTAT_bits.P
562 #define I2C_STOP SSPSTAT_bits.I2C_STOP
563 #define D SSPSTAT_bits.D
564 #define I2C_DATA SSPSTAT_bits.I2C_DATA
565 #define NOT_A SSPSTAT_bits.NOT_A
566 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
567 #define D_A SSPSTAT_bits.D_A
568 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
570 // ----- STATUS bits --------------------
576 unsigned char NOT_PD:1;
577 unsigned char NOT_TO:1;
583 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
585 #define C STATUS_bits.C
586 #define DC STATUS_bits.DC
587 #define Z STATUS_bits.Z
588 #define NOT_PD STATUS_bits.NOT_PD
589 #define NOT_TO STATUS_bits.NOT_TO
590 #define RP0 STATUS_bits.RP0
591 #define RP1 STATUS_bits.RP1
592 #define IRP STATUS_bits.IRP
594 // ----- T1CON bits --------------------
597 unsigned char TMR1ON:1;
598 unsigned char TMR1CS:1;
599 unsigned char T1INSYNC:1;
600 unsigned char T1OSCEN:1;
601 unsigned char T1CKPS0:1;
602 unsigned char T1CKPS1:1;
607 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
609 #define TMR1ON T1CON_bits.TMR1ON
610 #define TMR1CS T1CON_bits.TMR1CS
611 #define T1INSYNC T1CON_bits.T1INSYNC
612 #define T1OSCEN T1CON_bits.T1OSCEN
613 #define T1CKPS0 T1CON_bits.T1CKPS0
614 #define T1CKPS1 T1CON_bits.T1CKPS1
616 // ----- T2CON bits --------------------
619 unsigned char T2CKPS0:1;
620 unsigned char T2CKPS1:1;
621 unsigned char TMR2ON:1;
622 unsigned char TOUTPS0:1;
623 unsigned char TOUTPS1:1;
624 unsigned char TOUTPS2:1;
625 unsigned char TOUTPS3:1;
629 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
631 #define T2CKPS0 T2CON_bits.T2CKPS0
632 #define T2CKPS1 T2CON_bits.T2CKPS1
633 #define TMR2ON T2CON_bits.TMR2ON
634 #define TOUTPS0 T2CON_bits.TOUTPS0
635 #define TOUTPS1 T2CON_bits.TOUTPS1
636 #define TOUTPS2 T2CON_bits.TOUTPS2
637 #define TOUTPS3 T2CON_bits.TOUTPS3