2 // Register Declarations for Microchip 16C72 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define TMR1L_ADDR 0x000E
40 #define TMR1H_ADDR 0x000F
41 #define T1CON_ADDR 0x0010
42 #define TMR2_ADDR 0x0011
43 #define T2CON_ADDR 0x0012
44 #define SSPBUF_ADDR 0x0013
45 #define SSPCON_ADDR 0x0014
46 #define CCPR1L_ADDR 0x0015
47 #define CCPR1H_ADDR 0x0016
48 #define CCP1CON_ADDR 0x0017
49 #define ADRES_ADDR 0x001E
50 #define ADCON0_ADDR 0x001F
51 #define OPTION_REG_ADDR 0x0081
52 #define TRISA_ADDR 0x0085
53 #define TRISB_ADDR 0x0086
54 #define TRISC_ADDR 0x0087
55 #define PIE1_ADDR 0x008C
56 #define PCON_ADDR 0x008E
57 #define PR2_ADDR 0x0092
58 #define SSPADD_ADDR 0x0093
59 #define SSPSTAT_ADDR 0x0094
60 #define ADCON1_ADDR 0x009F
63 // Memory organization.
69 // P16C72.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
72 // This header file defines configurations, registers, and other useful bits of
73 // information for the PIC16C72 microcontroller. These names are taken to match
74 // the data sheets as closely as possible.
76 // Note that the processor must be selected before this file is
77 // included. The processor may be selected the following ways:
79 // 1. Command line switch:
80 // C:\ MPASM MYFILE.ASM /PIC16C72
81 // 2. LIST directive in the source file
83 // 3. Processor Type entry in the MPASM full-screen interface
85 //==========================================================================
89 //==========================================================================
93 //1.01 11/28/95 Added NOT_BOR to match revised datasheet
94 //1.00 10/31/95 Initial Release
96 //==========================================================================
100 //==========================================================================
103 // MESSG "Processor-header file mismatch. Verify selected processor."
106 //==========================================================================
108 // Register Definitions
110 //==========================================================================
115 //----- Register Files------------------------------------------------------
117 extern __sfr __at (INDF_ADDR) INDF;
118 extern __sfr __at (TMR0_ADDR) TMR0;
119 extern __sfr __at (PCL_ADDR) PCL;
120 extern __sfr __at (STATUS_ADDR) STATUS;
121 extern __sfr __at (FSR_ADDR) FSR;
122 extern __sfr __at (PORTA_ADDR) PORTA;
123 extern __sfr __at (PORTB_ADDR) PORTB;
124 extern __sfr __at (PORTC_ADDR) PORTC;
125 extern __sfr __at (PCLATH_ADDR) PCLATH;
126 extern __sfr __at (INTCON_ADDR) INTCON;
127 extern __sfr __at (PIR1_ADDR) PIR1;
128 extern __sfr __at (TMR1L_ADDR) TMR1L;
129 extern __sfr __at (TMR1H_ADDR) TMR1H;
130 extern __sfr __at (T1CON_ADDR) T1CON;
131 extern __sfr __at (TMR2_ADDR) TMR2;
132 extern __sfr __at (T2CON_ADDR) T2CON;
133 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
134 extern __sfr __at (SSPCON_ADDR) SSPCON;
135 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
136 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
137 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
138 extern __sfr __at (ADRES_ADDR) ADRES;
139 extern __sfr __at (ADCON0_ADDR) ADCON0;
141 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
142 extern __sfr __at (TRISA_ADDR) TRISA;
143 extern __sfr __at (TRISB_ADDR) TRISB;
144 extern __sfr __at (TRISC_ADDR) TRISC;
145 extern __sfr __at (PIE1_ADDR) PIE1;
146 extern __sfr __at (PCON_ADDR) PCON;
147 extern __sfr __at (PR2_ADDR) PR2;
148 extern __sfr __at (SSPADD_ADDR) SSPADD;
149 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
150 extern __sfr __at (ADCON1_ADDR) ADCON1;
152 //----- STATUS Bits --------------------------------------------------------
155 //----- INTCON Bits --------------------------------------------------------
158 //----- PIR1 Bits ----------------------------------------------------------
161 //----- T1CON Bits ---------------------------------------------------------
164 //----- T2CON Bits ---------------------------------------------------------
167 //----- SSPCON Bits --------------------------------------------------------
170 //----- CCP1CON Bits -------------------------------------------------------
173 //----- ADCON0 Bits --------------------------------------------------------
176 //----- OPTION Bits --------------------------------------------------------
179 //----- PIE1 Bits ----------------------------------------------------------
182 //----- PCON Bits ----------------------------------------------------------
185 //----- SSPSTAT Bits -------------------------------------------------------
188 //----- ADCON1 Bits --------------------------------------------------------
191 //==========================================================================
195 //==========================================================================
198 // __BADRAM H'08'-H'09', H'0D', H'18'-H'1D'
199 // __BADRAM H'88'-H'89', H'8D', H'8F'-H'91', H'95'-H'9E'
201 //==========================================================================
203 // Configuration Bits
205 //==========================================================================
207 #define _BODEN_ON 0x3FFF
208 #define _BODEN_OFF 0x3FBF
209 #define _CP_ALL 0x00CF
210 #define _CP_75 0x15DF
211 #define _CP_50 0x2AEF
212 #define _CP_OFF 0x3FFF
213 #define _PWRTE_OFF 0x3FFF
214 #define _PWRTE_ON 0x3FF7
215 #define _WDT_ON 0x3FFF
216 #define _WDT_OFF 0x3FFB
217 #define _LP_OSC 0x3FFC
218 #define _XT_OSC 0x3FFD
219 #define _HS_OSC 0x3FFE
220 #define _RC_OSC 0x3FFF
224 // ----- ADCON0 bits --------------------
227 unsigned char ADON:1;
230 unsigned char CHS0:1;
231 unsigned char CHS1:1;
232 unsigned char CHS2:1;
233 unsigned char ADCS0:1;
234 unsigned char ADCS1:1;
239 unsigned char NOT_DONE:1;
249 unsigned char GO_DONE:1;
257 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
259 #define ADON ADCON0_bits.ADON
260 #define GO ADCON0_bits.GO
261 #define NOT_DONE ADCON0_bits.NOT_DONE
262 #define GO_DONE ADCON0_bits.GO_DONE
263 #define CHS0 ADCON0_bits.CHS0
264 #define CHS1 ADCON0_bits.CHS1
265 #define CHS2 ADCON0_bits.CHS2
266 #define ADCS0 ADCON0_bits.ADCS0
267 #define ADCS1 ADCON0_bits.ADCS1
269 // ----- ADCON1 bits --------------------
272 unsigned char PCFG0:1;
273 unsigned char PCFG1:1;
274 unsigned char PCFG2:1;
282 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
284 #define PCFG0 ADCON1_bits.PCFG0
285 #define PCFG1 ADCON1_bits.PCFG1
286 #define PCFG2 ADCON1_bits.PCFG2
288 // ----- CCP1CON bits --------------------
291 unsigned char CCP1M0:1;
292 unsigned char CCP1M1:1;
293 unsigned char CCP1M2:1;
294 unsigned char CCP1M3:1;
295 unsigned char CCP1Y:1;
296 unsigned char CCP1X:1;
301 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
303 #define CCP1M0 CCP1CON_bits.CCP1M0
304 #define CCP1M1 CCP1CON_bits.CCP1M1
305 #define CCP1M2 CCP1CON_bits.CCP1M2
306 #define CCP1M3 CCP1CON_bits.CCP1M3
307 #define CCP1Y CCP1CON_bits.CCP1Y
308 #define CCP1X CCP1CON_bits.CCP1X
310 // ----- INTCON bits --------------------
313 unsigned char RBIF:1;
314 unsigned char INTF:1;
315 unsigned char T0IF:1;
316 unsigned char RBIE:1;
317 unsigned char INTE:1;
318 unsigned char T0IE:1;
319 unsigned char PEIE:1;
323 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
325 #define RBIF INTCON_bits.RBIF
326 #define INTF INTCON_bits.INTF
327 #define T0IF INTCON_bits.T0IF
328 #define RBIE INTCON_bits.RBIE
329 #define INTE INTCON_bits.INTE
330 #define T0IE INTCON_bits.T0IE
331 #define PEIE INTCON_bits.PEIE
332 #define GIE INTCON_bits.GIE
334 // ----- OPTION_REG bits --------------------
341 unsigned char T0SE:1;
342 unsigned char T0CS:1;
343 unsigned char INTEDG:1;
344 unsigned char NOT_RBPU:1;
346 } __OPTION_REG_bits_t;
347 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
349 #define PS0 OPTION_REG_bits.PS0
350 #define PS1 OPTION_REG_bits.PS1
351 #define PS2 OPTION_REG_bits.PS2
352 #define PSA OPTION_REG_bits.PSA
353 #define T0SE OPTION_REG_bits.T0SE
354 #define T0CS OPTION_REG_bits.T0CS
355 #define INTEDG OPTION_REG_bits.INTEDG
356 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
358 // ----- PCON bits --------------------
361 unsigned char NOT_BO:1;
362 unsigned char NOT_POR:1;
371 unsigned char NOT_BOR:1;
381 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
383 #define NOT_BO PCON_bits.NOT_BO
384 #define NOT_BOR PCON_bits.NOT_BOR
385 #define NOT_POR PCON_bits.NOT_POR
387 // ----- PIE1 bits --------------------
390 unsigned char TMR1IE:1;
391 unsigned char TMR2IE:1;
392 unsigned char CCP1IE:1;
393 unsigned char SSPIE:1;
396 unsigned char ADIE:1;
400 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
402 #define TMR1IE PIE1_bits.TMR1IE
403 #define TMR2IE PIE1_bits.TMR2IE
404 #define CCP1IE PIE1_bits.CCP1IE
405 #define SSPIE PIE1_bits.SSPIE
406 #define ADIE PIE1_bits.ADIE
408 // ----- PIR1 bits --------------------
411 unsigned char TMR1IF:1;
412 unsigned char TMR2IF:1;
413 unsigned char CCP1IF:1;
414 unsigned char SSPIF:1;
417 unsigned char ADIF:1;
421 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
423 #define TMR1IF PIR1_bits.TMR1IF
424 #define TMR2IF PIR1_bits.TMR2IF
425 #define CCP1IF PIR1_bits.CCP1IF
426 #define SSPIF PIR1_bits.SSPIF
427 #define ADIF PIR1_bits.ADIF
429 // ----- PORTA bits --------------------
442 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
444 #define RA0 PORTA_bits.RA0
445 #define RA1 PORTA_bits.RA1
446 #define RA2 PORTA_bits.RA2
447 #define RA3 PORTA_bits.RA3
448 #define RA4 PORTA_bits.RA4
449 #define RA5 PORTA_bits.RA5
451 // ----- PORTB bits --------------------
464 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
466 #define RB0 PORTB_bits.RB0
467 #define RB1 PORTB_bits.RB1
468 #define RB2 PORTB_bits.RB2
469 #define RB3 PORTB_bits.RB3
470 #define RB4 PORTB_bits.RB4
471 #define RB5 PORTB_bits.RB5
472 #define RB6 PORTB_bits.RB6
473 #define RB7 PORTB_bits.RB7
475 // ----- PORTC bits --------------------
488 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
490 #define RC0 PORTC_bits.RC0
491 #define RC1 PORTC_bits.RC1
492 #define RC2 PORTC_bits.RC2
493 #define RC3 PORTC_bits.RC3
494 #define RC4 PORTC_bits.RC4
495 #define RC5 PORTC_bits.RC5
496 #define RC6 PORTC_bits.RC6
497 #define RC7 PORTC_bits.RC7
499 // ----- SSPCON bits --------------------
502 unsigned char SSPM0:1;
503 unsigned char SSPM1:1;
504 unsigned char SSPM2:1;
505 unsigned char SSPM3:1;
507 unsigned char SSPEN:1;
508 unsigned char SSPOV:1;
509 unsigned char WCOL:1;
512 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
514 #define SSPM0 SSPCON_bits.SSPM0
515 #define SSPM1 SSPCON_bits.SSPM1
516 #define SSPM2 SSPCON_bits.SSPM2
517 #define SSPM3 SSPCON_bits.SSPM3
518 #define CKP SSPCON_bits.CKP
519 #define SSPEN SSPCON_bits.SSPEN
520 #define SSPOV SSPCON_bits.SSPOV
521 #define WCOL SSPCON_bits.WCOL
523 // ----- SSPSTAT bits --------------------
538 unsigned char I2C_READ:1;
539 unsigned char I2C_START:1;
540 unsigned char I2C_STOP:1;
541 unsigned char I2C_DATA:1;
548 unsigned char NOT_W:1;
551 unsigned char NOT_A:1;
558 unsigned char NOT_WRITE:1;
561 unsigned char NOT_ADDRESS:1;
578 unsigned char READ_WRITE:1;
581 unsigned char DATA_ADDRESS:1;
586 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
588 #define BF SSPSTAT_bits.BF
589 #define UA SSPSTAT_bits.UA
590 #define R SSPSTAT_bits.R
591 #define I2C_READ SSPSTAT_bits.I2C_READ
592 #define NOT_W SSPSTAT_bits.NOT_W
593 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
594 #define R_W SSPSTAT_bits.R_W
595 #define READ_WRITE SSPSTAT_bits.READ_WRITE
596 #define S SSPSTAT_bits.S
597 #define I2C_START SSPSTAT_bits.I2C_START
598 #define P SSPSTAT_bits.P
599 #define I2C_STOP SSPSTAT_bits.I2C_STOP
600 #define D SSPSTAT_bits.D
601 #define I2C_DATA SSPSTAT_bits.I2C_DATA
602 #define NOT_A SSPSTAT_bits.NOT_A
603 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
604 #define D_A SSPSTAT_bits.D_A
605 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
607 // ----- STATUS bits --------------------
613 unsigned char NOT_PD:1;
614 unsigned char NOT_TO:1;
620 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
622 #define C STATUS_bits.C
623 #define DC STATUS_bits.DC
624 #define Z STATUS_bits.Z
625 #define NOT_PD STATUS_bits.NOT_PD
626 #define NOT_TO STATUS_bits.NOT_TO
627 #define RP0 STATUS_bits.RP0
628 #define RP1 STATUS_bits.RP1
629 #define IRP STATUS_bits.IRP
631 // ----- T1CON bits --------------------
634 unsigned char TMR1ON:1;
635 unsigned char TMR1CS:1;
636 unsigned char NOT_T1SYNC:1;
637 unsigned char T1OSCEN:1;
638 unsigned char T1CKPS0:1;
639 unsigned char T1CKPS1:1;
646 unsigned char T1INSYNC:1;
654 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
656 #define TMR1ON T1CON_bits.TMR1ON
657 #define TMR1CS T1CON_bits.TMR1CS
658 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
659 #define T1INSYNC T1CON_bits.T1INSYNC
660 #define T1OSCEN T1CON_bits.T1OSCEN
661 #define T1CKPS0 T1CON_bits.T1CKPS0
662 #define T1CKPS1 T1CON_bits.T1CKPS1
664 // ----- T2CON bits --------------------
667 unsigned char T2CKPS0:1;
668 unsigned char T2CKPS1:1;
669 unsigned char TMR2ON:1;
670 unsigned char TOUTPS0:1;
671 unsigned char TOUTPS1:1;
672 unsigned char TOUTPS2:1;
673 unsigned char TOUTPS3:1;
677 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
679 #define T2CKPS0 T2CON_bits.T2CKPS0
680 #define T2CKPS1 T2CON_bits.T2CKPS1
681 #define TMR2ON T2CON_bits.TMR2ON
682 #define TOUTPS0 T2CON_bits.TOUTPS0
683 #define TOUTPS1 T2CON_bits.TOUTPS1
684 #define TOUTPS2 T2CON_bits.TOUTPS2
685 #define TOUTPS3 T2CON_bits.TOUTPS3
687 // ----- TRISA bits --------------------
690 unsigned char TRISA0:1;
691 unsigned char TRISA1:1;
692 unsigned char TRISA2:1;
693 unsigned char TRISA3:1;
694 unsigned char TRISA4:1;
695 unsigned char TRISA5:1;
700 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
702 #define TRISA0 TRISA_bits.TRISA0
703 #define TRISA1 TRISA_bits.TRISA1
704 #define TRISA2 TRISA_bits.TRISA2
705 #define TRISA3 TRISA_bits.TRISA3
706 #define TRISA4 TRISA_bits.TRISA4
707 #define TRISA5 TRISA_bits.TRISA5
709 // ----- TRISB bits --------------------
712 unsigned char TRISB0:1;
713 unsigned char TRISB1:1;
714 unsigned char TRISB2:1;
715 unsigned char TRISB3:1;
716 unsigned char TRISB4:1;
717 unsigned char TRISB5:1;
718 unsigned char TRISB6:1;
719 unsigned char TRISB7:1;
722 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
724 #define TRISB0 TRISB_bits.TRISB0
725 #define TRISB1 TRISB_bits.TRISB1
726 #define TRISB2 TRISB_bits.TRISB2
727 #define TRISB3 TRISB_bits.TRISB3
728 #define TRISB4 TRISB_bits.TRISB4
729 #define TRISB5 TRISB_bits.TRISB5
730 #define TRISB6 TRISB_bits.TRISB6
731 #define TRISB7 TRISB_bits.TRISB7
733 // ----- TRISC bits --------------------
736 unsigned char TRISC0:1;
737 unsigned char TRISC1:1;
738 unsigned char TRISC2:1;
739 unsigned char TRISC3:1;
740 unsigned char TRISC4:1;
741 unsigned char TRISC5:1;
742 unsigned char TRISC6:1;
743 unsigned char TRISC7:1;
746 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
748 #define TRISC0 TRISC_bits.TRISC0
749 #define TRISC1 TRISC_bits.TRISC1
750 #define TRISC2 TRISC_bits.TRISC2
751 #define TRISC3 TRISC_bits.TRISC3
752 #define TRISC4 TRISC_bits.TRISC4
753 #define TRISC5 TRISC_bits.TRISC5
754 #define TRISC6 TRISC_bits.TRISC6
755 #define TRISC7 TRISC_bits.TRISC7