2 // Register Declarations for Microchip 16C715 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PCLATH_ADDR 0x000A
36 #define INTCON_ADDR 0x000B
37 #define PIR1_ADDR 0x000C
38 #define ADRES_ADDR 0x001E
39 #define ADCON0_ADDR 0x001F
40 #define OPTION_REG_ADDR 0x0081
41 #define TRISA_ADDR 0x0085
42 #define TRISB_ADDR 0x0086
43 #define PIE1_ADDR 0x008C
44 #define PCON_ADDR 0x008E
45 #define ADCON1_ADDR 0x009F
48 // Memory organization.
51 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
52 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
53 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
54 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
55 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
56 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
57 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
58 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
59 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
60 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
61 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
62 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
63 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
64 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
65 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
66 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
67 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
68 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
72 // P16C715.INC Standard Header File, Version 1.01 Microchip Technology, Inc.
75 // This header file defines configurations, registers, and other useful bits of
76 // information for the PIC16C715 microcontroller. These names are taken to match
77 // the data sheets as closely as possible.
79 // Note that the processor must be selected before this file is
80 // included. The processor may be selected the following ways:
82 // 1. Command line switch:
83 // C:\ MPASM MYFILE.ASM /PIC16C715
84 // 2. LIST directive in the source file
86 // 3. Processor Type entry in the MPASM full-screen interface
88 //==========================================================================
92 //==========================================================================
96 //1.01 05/12/97 Added values for Parity Enable configuration bits
97 //1.00 04/11/96 Initial Release
99 //==========================================================================
103 //==========================================================================
106 // MESSG "Processor-header file mismatch. Verify selected processor."
109 //==========================================================================
111 // Register Definitions
113 //==========================================================================
118 //----- Register Files------------------------------------------------------
120 extern __data __at (INDF_ADDR) volatile char INDF;
121 extern __sfr __at (TMR0_ADDR) TMR0;
122 extern __data __at (PCL_ADDR) volatile char PCL;
123 extern __sfr __at (STATUS_ADDR) STATUS;
124 extern __sfr __at (FSR_ADDR) FSR;
125 extern __sfr __at (PORTA_ADDR) PORTA;
126 extern __sfr __at (PORTB_ADDR) PORTB;
127 extern __sfr __at (PCLATH_ADDR) PCLATH;
128 extern __sfr __at (INTCON_ADDR) INTCON;
129 extern __sfr __at (PIR1_ADDR) PIR1;
130 extern __sfr __at (ADRES_ADDR) ADRES;
131 extern __sfr __at (ADCON0_ADDR) ADCON0;
133 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
134 extern __sfr __at (TRISA_ADDR) TRISA;
135 extern __sfr __at (TRISB_ADDR) TRISB;
136 extern __sfr __at (PIE1_ADDR) PIE1;
137 extern __sfr __at (PCON_ADDR) PCON;
138 extern __sfr __at (ADCON1_ADDR) ADCON1;
140 //----- STATUS Bits --------------------------------------------------------
143 //----- INTCON Bits --------------------------------------------------------
146 //----- PIR1 Bits ----------------------------------------------------------
149 //----- ADCON0 Bits --------------------------------------------------------
152 //----- OPTION Bits --------------------------------------------------------
155 //----- PIE1 Bits ----------------------------------------------------------
158 //----- PCON Bits ----------------------------------------------------------
161 //----- ADCON1 Bits --------------------------------------------------------
164 //==========================================================================
168 //==========================================================================
171 // __BADRAM H'07'-H'09', H'0D'-H'1D'
172 // __BADRAM H'87'-H'89', H'8D', H'8F'-H'9E', H'C0'-H'EF'
174 //==========================================================================
176 // Configuration Bits
178 //==========================================================================
180 #define _MPEEN_ON 0x3FFF
181 #define _MPEEN_OFF 0x3F7F
182 #define _BODEN_ON 0x3FFF
183 #define _BODEN_OFF 0x3FBF
184 #define _CP_ALL 0x00CF
185 #define _CP_50 0x15DF
186 #define _CP_OFF 0x3FFF
187 #define _PWRTE_OFF 0x3FFF
188 #define _PWRTE_ON 0x3FF7
189 #define _WDT_ON 0x3FFF
190 #define _WDT_OFF 0x3FFB
191 #define _LP_OSC 0x3FFC
192 #define _XT_OSC 0x3FFD
193 #define _HS_OSC 0x3FFE
194 #define _RC_OSC 0x3FFF
198 // ----- ADCON0 bits --------------------
201 unsigned char ADON:1;
204 unsigned char CHS0:1;
205 unsigned char CHS1:1;
206 unsigned char CHS2:1;
207 unsigned char ADCS0:1;
208 unsigned char ADCS1:1;
213 unsigned char NOT_DONE:1;
223 unsigned char GO_DONE:1;
231 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
233 #define ADON ADCON0_bits.ADON
234 #define GO ADCON0_bits.GO
235 #define NOT_DONE ADCON0_bits.NOT_DONE
236 #define GO_DONE ADCON0_bits.GO_DONE
237 #define CHS0 ADCON0_bits.CHS0
238 #define CHS1 ADCON0_bits.CHS1
239 #define CHS2 ADCON0_bits.CHS2
240 #define ADCS0 ADCON0_bits.ADCS0
241 #define ADCS1 ADCON0_bits.ADCS1
243 // ----- ADCON1 bits --------------------
246 unsigned char PCFG0:1;
247 unsigned char PCFG1:1;
256 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
258 #define PCFG0 ADCON1_bits.PCFG0
259 #define PCFG1 ADCON1_bits.PCFG1
261 // ----- INTCON bits --------------------
264 unsigned char RBIF:1;
265 unsigned char INTF:1;
266 unsigned char T0IF:1;
267 unsigned char RBIE:1;
268 unsigned char INTE:1;
269 unsigned char T0IE:1;
270 unsigned char PEIE:1;
274 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
276 #define RBIF INTCON_bits.RBIF
277 #define INTF INTCON_bits.INTF
278 #define T0IF INTCON_bits.T0IF
279 #define RBIE INTCON_bits.RBIE
280 #define INTE INTCON_bits.INTE
281 #define T0IE INTCON_bits.T0IE
282 #define PEIE INTCON_bits.PEIE
283 #define GIE INTCON_bits.GIE
285 // ----- OPTION_REG bits --------------------
292 unsigned char T0SE:1;
293 unsigned char T0CS:1;
294 unsigned char INTEDG:1;
295 unsigned char NOT_RBPU:1;
297 } __OPTION_REG_bits_t;
298 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
300 #define PS0 OPTION_REG_bits.PS0
301 #define PS1 OPTION_REG_bits.PS1
302 #define PS2 OPTION_REG_bits.PS2
303 #define PSA OPTION_REG_bits.PSA
304 #define T0SE OPTION_REG_bits.T0SE
305 #define T0CS OPTION_REG_bits.T0CS
306 #define INTEDG OPTION_REG_bits.INTEDG
307 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
309 // ----- PCON bits --------------------
312 unsigned char NOT_BO:1;
313 unsigned char NOT_POR:1;
314 unsigned char NOT_MPE:1;
322 unsigned char NOT_BOR:1;
332 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
334 #define NOT_BO PCON_bits.NOT_BO
335 #define NOT_BOR PCON_bits.NOT_BOR
336 #define NOT_POR PCON_bits.NOT_POR
337 #define NOT_MPE PCON_bits.NOT_MPE
339 // ----- PIE1 bits --------------------
348 unsigned char ADIE:1;
352 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
354 #define ADIE PIE1_bits.ADIE
356 // ----- PIR1 bits --------------------
365 unsigned char ADIF:1;
369 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
371 #define ADIF PIR1_bits.ADIF
373 // ----- STATUS bits --------------------
379 unsigned char NOT_PD:1;
380 unsigned char NOT_TO:1;
386 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
388 #define C STATUS_bits.C
389 #define DC STATUS_bits.DC
390 #define Z STATUS_bits.Z
391 #define NOT_PD STATUS_bits.NOT_PD
392 #define NOT_TO STATUS_bits.NOT_TO
393 #define RP0 STATUS_bits.RP0
394 #define RP1 STATUS_bits.RP1
395 #define IRP STATUS_bits.IRP