2 // Register Declarations for Microchip 16C711 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define ADCON0_ADDR 0x0008
36 #define ADRES_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define PCON_ADDR 0x0087
43 #define ADCON1_ADDR 0x0088
46 // Memory organization.
49 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
50 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
51 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
52 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
53 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
54 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
55 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
56 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
57 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
58 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
59 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
60 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
61 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
62 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
63 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
64 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
68 // P16C711.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
71 // This header file defines configurations, registers, and other useful bits of
72 // information for the PIC16C711 microcontroller. These names are taken to match
73 // the data sheets as closely as possible.
75 // Note that the processor must be selected before this file is
76 // included. The processor may be selected the following ways:
78 // 1. Command line switch:
79 // C:\ MPASM MYFILE.ASM /PIC16C711
80 // 2. LIST directive in the source file
82 // 3. Processor Type entry in the MPASM full-screen interface
84 //==========================================================================
88 //==========================================================================
92 //1.00 04/10/96 Initial Release
94 //==========================================================================
98 //==========================================================================
101 // MESSG "Processor-header file mismatch. Verify selected processor."
104 //==========================================================================
106 // Register Definitions
108 //==========================================================================
113 //----- Register Files------------------------------------------------------
115 extern data __at (INDF_ADDR) volatile char INDF;
116 extern sfr __at (TMR0_ADDR) TMR0;
117 extern data __at (PCL_ADDR) volatile char PCL;
118 extern sfr __at (STATUS_ADDR) STATUS;
119 extern sfr __at (FSR_ADDR) FSR;
120 extern sfr __at (PORTA_ADDR) PORTA;
121 extern sfr __at (PORTB_ADDR) PORTB;
122 extern sfr __at (ADCON0_ADDR) ADCON0;
123 extern sfr __at (ADRES_ADDR) ADRES;
124 extern sfr __at (PCLATH_ADDR) PCLATH;
125 extern sfr __at (INTCON_ADDR) INTCON;
127 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
128 extern sfr __at (TRISA_ADDR) TRISA;
129 extern sfr __at (TRISB_ADDR) TRISB;
130 extern sfr __at (PCON_ADDR) PCON;
131 extern sfr __at (ADCON1_ADDR) ADCON1;
133 //----- STATUS Bits --------------------------------------------------------
136 //----- ADCON0 Bits --------------------------------------------------------
139 //----- INTCON Bits --------------------------------------------------------
142 //----- OPTION Bits --------------------------------------------------------
145 //----- PCON Bits ----------------------------------------------------------
148 //----- ADCON1 Bits --------------------------------------------------------
151 //==========================================================================
155 //==========================================================================
158 // __BADRAM H'07', H'50'-H'7F'
160 //==========================================================================
162 // Configuration Bits
164 //==========================================================================
166 #define _BODEN_ON 0x3FFF
167 #define _BODEN_OFF 0x3FBF
168 #define _CP_ON 0x004F
169 #define _CP_OFF 0x3FFF
170 #define _PWRTE_OFF 0x3FFF
171 #define _PWRTE_ON 0x3FF7
172 #define _WDT_ON 0x3FFF
173 #define _WDT_OFF 0x3FFB
174 #define _LP_OSC 0x3FFC
175 #define _XT_OSC 0x3FFD
176 #define _HS_OSC 0x3FFE
177 #define _RC_OSC 0x3FFF
181 // ----- ADCON0 bits --------------------
184 unsigned char ADON:1;
185 unsigned char ADIF:1;
187 unsigned char CHS0:1;
188 unsigned char CHS1:1;
190 unsigned char ADCS0:1;
191 unsigned char ADCS1:1;
196 unsigned char NOT_DONE:1;
206 unsigned char GO_DONE:1;
214 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
216 #define ADON ADCON0_bits.ADON
217 #define ADIF ADCON0_bits.ADIF
218 #define GO ADCON0_bits.GO
219 #define NOT_DONE ADCON0_bits.NOT_DONE
220 #define GO_DONE ADCON0_bits.GO_DONE
221 #define CHS0 ADCON0_bits.CHS0
222 #define CHS1 ADCON0_bits.CHS1
223 #define ADCS0 ADCON0_bits.ADCS0
224 #define ADCS1 ADCON0_bits.ADCS1
226 // ----- ADCON1 bits --------------------
229 unsigned char PCFG0:1;
230 unsigned char PCFG1:1;
239 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
241 #define PCFG0 ADCON1_bits.PCFG0
242 #define PCFG1 ADCON1_bits.PCFG1
244 // ----- INTCON bits --------------------
247 unsigned char RBIF:1;
248 unsigned char INTF:1;
249 unsigned char T0IF:1;
250 unsigned char RBIE:1;
251 unsigned char INTE:1;
252 unsigned char T0IE:1;
253 unsigned char ADIE:1;
257 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
259 #define RBIF INTCON_bits.RBIF
260 #define INTF INTCON_bits.INTF
261 #define T0IF INTCON_bits.T0IF
262 #define RBIE INTCON_bits.RBIE
263 #define INTE INTCON_bits.INTE
264 #define T0IE INTCON_bits.T0IE
265 #define ADIE INTCON_bits.ADIE
266 #define GIE INTCON_bits.GIE
268 // ----- OPTION_REG bits --------------------
275 unsigned char T0SE:1;
276 unsigned char T0CS:1;
277 unsigned char INTEDG:1;
278 unsigned char NOT_RBPU:1;
280 } __OPTION_REG_bits_t;
281 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
283 #define PS0 OPTION_REG_bits.PS0
284 #define PS1 OPTION_REG_bits.PS1
285 #define PS2 OPTION_REG_bits.PS2
286 #define PSA OPTION_REG_bits.PSA
287 #define T0SE OPTION_REG_bits.T0SE
288 #define T0CS OPTION_REG_bits.T0CS
289 #define INTEDG OPTION_REG_bits.INTEDG
290 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
292 // ----- PCON bits --------------------
295 unsigned char NOT_BO:1;
296 unsigned char NOT_POR:1;
305 unsigned char NOT_BOR:1;
315 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
317 #define NOT_BO PCON_bits.NOT_BO
318 #define NOT_BOR PCON_bits.NOT_BOR
319 #define NOT_POR PCON_bits.NOT_POR
321 // ----- STATUS bits --------------------
327 unsigned char NOT_PD:1;
328 unsigned char NOT_TO:1;
334 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
336 #define C STATUS_bits.C
337 #define DC STATUS_bits.DC
338 #define Z STATUS_bits.Z
339 #define NOT_PD STATUS_bits.NOT_PD
340 #define NOT_TO STATUS_bits.NOT_TO
341 #define RP0 STATUS_bits.RP0
342 #define RP1 STATUS_bits.RP1
343 #define IRP STATUS_bits.IRP