2 // Register Declarations for Microchip 16C711 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define ADCON0_ADDR 0x0008
36 #define ADRES_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define PCON_ADDR 0x0087
43 #define ADCON1_ADDR 0x0088
46 // Memory organization.
52 // P16C711.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
55 // This header file defines configurations, registers, and other useful bits of
56 // information for the PIC16C711 microcontroller. These names are taken to match
57 // the data sheets as closely as possible.
59 // Note that the processor must be selected before this file is
60 // included. The processor may be selected the following ways:
62 // 1. Command line switch:
63 // C:\ MPASM MYFILE.ASM /PIC16C711
64 // 2. LIST directive in the source file
66 // 3. Processor Type entry in the MPASM full-screen interface
68 //==========================================================================
72 //==========================================================================
76 //1.00 04/10/96 Initial Release
78 //==========================================================================
82 //==========================================================================
85 // MESSG "Processor-header file mismatch. Verify selected processor."
88 //==========================================================================
90 // Register Definitions
92 //==========================================================================
97 //----- Register Files------------------------------------------------------
99 extern __data __at (INDF_ADDR) volatile char INDF;
100 extern __sfr __at (TMR0_ADDR) TMR0;
101 extern __data __at (PCL_ADDR) volatile char PCL;
102 extern __sfr __at (STATUS_ADDR) STATUS;
103 extern __sfr __at (FSR_ADDR) FSR;
104 extern __sfr __at (PORTA_ADDR) PORTA;
105 extern __sfr __at (PORTB_ADDR) PORTB;
106 extern __sfr __at (ADCON0_ADDR) ADCON0;
107 extern __sfr __at (ADRES_ADDR) ADRES;
108 extern __sfr __at (PCLATH_ADDR) PCLATH;
109 extern __sfr __at (INTCON_ADDR) INTCON;
111 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
112 extern __sfr __at (TRISA_ADDR) TRISA;
113 extern __sfr __at (TRISB_ADDR) TRISB;
114 extern __sfr __at (PCON_ADDR) PCON;
115 extern __sfr __at (ADCON1_ADDR) ADCON1;
117 //----- STATUS Bits --------------------------------------------------------
120 //----- ADCON0 Bits --------------------------------------------------------
123 //----- INTCON Bits --------------------------------------------------------
126 //----- OPTION Bits --------------------------------------------------------
129 //----- PCON Bits ----------------------------------------------------------
132 //----- ADCON1 Bits --------------------------------------------------------
135 //==========================================================================
139 //==========================================================================
142 // __BADRAM H'07', H'50'-H'7F'
144 //==========================================================================
146 // Configuration Bits
148 //==========================================================================
150 #define _BODEN_ON 0x3FFF
151 #define _BODEN_OFF 0x3FBF
152 #define _CP_ON 0x004F
153 #define _CP_OFF 0x3FFF
154 #define _PWRTE_OFF 0x3FFF
155 #define _PWRTE_ON 0x3FF7
156 #define _WDT_ON 0x3FFF
157 #define _WDT_OFF 0x3FFB
158 #define _LP_OSC 0x3FFC
159 #define _XT_OSC 0x3FFD
160 #define _HS_OSC 0x3FFE
161 #define _RC_OSC 0x3FFF
165 // ----- ADCON0 bits --------------------
168 unsigned char ADON:1;
169 unsigned char ADIF:1;
171 unsigned char CHS0:1;
172 unsigned char CHS1:1;
174 unsigned char ADCS0:1;
175 unsigned char ADCS1:1;
180 unsigned char NOT_DONE:1;
190 unsigned char GO_DONE:1;
198 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
200 #define ADON ADCON0_bits.ADON
201 #define ADIF ADCON0_bits.ADIF
202 #define GO ADCON0_bits.GO
203 #define NOT_DONE ADCON0_bits.NOT_DONE
204 #define GO_DONE ADCON0_bits.GO_DONE
205 #define CHS0 ADCON0_bits.CHS0
206 #define CHS1 ADCON0_bits.CHS1
207 #define ADCS0 ADCON0_bits.ADCS0
208 #define ADCS1 ADCON0_bits.ADCS1
210 // ----- ADCON1 bits --------------------
213 unsigned char PCFG0:1;
214 unsigned char PCFG1:1;
223 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
225 #define PCFG0 ADCON1_bits.PCFG0
226 #define PCFG1 ADCON1_bits.PCFG1
228 // ----- INTCON bits --------------------
231 unsigned char RBIF:1;
232 unsigned char INTF:1;
233 unsigned char T0IF:1;
234 unsigned char RBIE:1;
235 unsigned char INTE:1;
236 unsigned char T0IE:1;
237 unsigned char ADIE:1;
241 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
243 #define RBIF INTCON_bits.RBIF
244 #define INTF INTCON_bits.INTF
245 #define T0IF INTCON_bits.T0IF
246 #define RBIE INTCON_bits.RBIE
247 #define INTE INTCON_bits.INTE
248 #define T0IE INTCON_bits.T0IE
249 #define ADIE INTCON_bits.ADIE
250 #define GIE INTCON_bits.GIE
252 // ----- OPTION_REG bits --------------------
259 unsigned char T0SE:1;
260 unsigned char T0CS:1;
261 unsigned char INTEDG:1;
262 unsigned char NOT_RBPU:1;
264 } __OPTION_REG_bits_t;
265 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
267 #define PS0 OPTION_REG_bits.PS0
268 #define PS1 OPTION_REG_bits.PS1
269 #define PS2 OPTION_REG_bits.PS2
270 #define PSA OPTION_REG_bits.PSA
271 #define T0SE OPTION_REG_bits.T0SE
272 #define T0CS OPTION_REG_bits.T0CS
273 #define INTEDG OPTION_REG_bits.INTEDG
274 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
276 // ----- PCON bits --------------------
279 unsigned char NOT_BO:1;
280 unsigned char NOT_POR:1;
289 unsigned char NOT_BOR:1;
299 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
301 #define NOT_BO PCON_bits.NOT_BO
302 #define NOT_BOR PCON_bits.NOT_BOR
303 #define NOT_POR PCON_bits.NOT_POR
305 // ----- STATUS bits --------------------
311 unsigned char NOT_PD:1;
312 unsigned char NOT_TO:1;
318 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
320 #define C STATUS_bits.C
321 #define DC STATUS_bits.DC
322 #define Z STATUS_bits.Z
323 #define NOT_PD STATUS_bits.NOT_PD
324 #define NOT_TO STATUS_bits.NOT_TO
325 #define RP0 STATUS_bits.RP0
326 #define RP1 STATUS_bits.RP1
327 #define IRP STATUS_bits.IRP