2 // Register Declarations for Microchip 16C710 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define ADCON0_ADDR 0x0008
36 #define ADRES_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define PCON_ADDR 0x0087
43 #define ADCON1_ADDR 0x0088
46 // Memory organization.
52 // P16C710.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
55 // This header file defines configurations, registers, and other useful bits of
56 // information for the PIC16C710 microcontroller. These names are taken to match
57 // the data sheets as closely as possible.
59 // Note that the processor must be selected before this file is
60 // included. The processor may be selected the following ways:
62 // 1. Command line switch:
63 // C:\ MPASM MYFILE.ASM /PIC16C710
64 // 2. LIST directive in the source file
66 // 3. Processor Type entry in the MPASM full-screen interface
68 //==========================================================================
72 //==========================================================================
76 //1.00 04/10/96 Initial Release
78 //==========================================================================
82 //==========================================================================
85 // MESSG "Processor-header file mismatch. Verify selected processor."
88 //==========================================================================
90 // Register Definitions
92 //==========================================================================
97 //----- Register Files------------------------------------------------------
99 extern __sfr __at (INDF_ADDR) INDF;
100 extern __sfr __at (TMR0_ADDR) TMR0;
101 extern __sfr __at (PCL_ADDR) PCL;
102 extern __sfr __at (STATUS_ADDR) STATUS;
103 extern __sfr __at (FSR_ADDR) FSR;
104 extern __sfr __at (PORTA_ADDR) PORTA;
105 extern __sfr __at (PORTB_ADDR) PORTB;
106 extern __sfr __at (ADCON0_ADDR) ADCON0;
107 extern __sfr __at (ADRES_ADDR) ADRES;
108 extern __sfr __at (PCLATH_ADDR) PCLATH;
109 extern __sfr __at (INTCON_ADDR) INTCON;
111 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
112 extern __sfr __at (TRISA_ADDR) TRISA;
113 extern __sfr __at (TRISB_ADDR) TRISB;
114 extern __sfr __at (PCON_ADDR) PCON;
115 extern __sfr __at (ADCON1_ADDR) ADCON1;
117 //----- STATUS Bits --------------------------------------------------------
120 //----- ADCON0 Bits --------------------------------------------------------
123 //----- INTCON Bits --------------------------------------------------------
126 //----- OPTION Bits --------------------------------------------------------
129 //----- PCON Bits ----------------------------------------------------------
132 //----- ADCON1 Bits --------------------------------------------------------
135 //==========================================================================
139 //==========================================================================
142 // __BADRAM H'07', H'30'-H'7F'
144 //==========================================================================
146 // Configuration Bits
148 //==========================================================================
150 #define _BODEN_ON 0x3FFF
151 #define _BODEN_OFF 0x3FBF
152 #define _CP_ON 0x004F
153 #define _CP_OFF 0x3FFF
154 #define _PWRTE_OFF 0x3FFF
155 #define _PWRTE_ON 0x3FF7
156 #define _WDT_ON 0x3FFF
157 #define _WDT_OFF 0x3FFB
158 #define _LP_OSC 0x3FFC
159 #define _XT_OSC 0x3FFD
160 #define _HS_OSC 0x3FFE
161 #define _RC_OSC 0x3FFF
165 // ----- ADCON0 bits --------------------
168 unsigned char ADON:1;
169 unsigned char ADIF:1;
171 unsigned char CHS0:1;
172 unsigned char CHS1:1;
174 unsigned char ADCS0:1;
175 unsigned char ADCS1:1;
180 unsigned char NOT_DONE:1;
190 unsigned char GO_DONE:1;
198 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
200 #ifndef NO_BIT_DEFINES
201 #define ADON ADCON0_bits.ADON
202 #define ADIF ADCON0_bits.ADIF
203 #define GO ADCON0_bits.GO
204 #define NOT_DONE ADCON0_bits.NOT_DONE
205 #define GO_DONE ADCON0_bits.GO_DONE
206 #define CHS0 ADCON0_bits.CHS0
207 #define CHS1 ADCON0_bits.CHS1
208 #define ADCS0 ADCON0_bits.ADCS0
209 #define ADCS1 ADCON0_bits.ADCS1
210 #endif /* NO_BIT_DEFINES */
212 // ----- ADCON1 bits --------------------
215 unsigned char PCFG0:1;
216 unsigned char PCFG1:1;
225 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
227 #ifndef NO_BIT_DEFINES
228 #define PCFG0 ADCON1_bits.PCFG0
229 #define PCFG1 ADCON1_bits.PCFG1
230 #endif /* NO_BIT_DEFINES */
232 // ----- INTCON bits --------------------
235 unsigned char RBIF:1;
236 unsigned char INTF:1;
237 unsigned char T0IF:1;
238 unsigned char RBIE:1;
239 unsigned char INTE:1;
240 unsigned char T0IE:1;
241 unsigned char ADIE:1;
245 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
247 #ifndef NO_BIT_DEFINES
248 #define RBIF INTCON_bits.RBIF
249 #define INTF INTCON_bits.INTF
250 #define T0IF INTCON_bits.T0IF
251 #define RBIE INTCON_bits.RBIE
252 #define INTE INTCON_bits.INTE
253 #define T0IE INTCON_bits.T0IE
254 #define ADIE INTCON_bits.ADIE
255 #define GIE INTCON_bits.GIE
256 #endif /* NO_BIT_DEFINES */
258 // ----- OPTION_REG bits --------------------
265 unsigned char T0SE:1;
266 unsigned char T0CS:1;
267 unsigned char INTEDG:1;
268 unsigned char NOT_RBPU:1;
270 } __OPTION_REG_bits_t;
271 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
273 #ifndef NO_BIT_DEFINES
274 #define PS0 OPTION_REG_bits.PS0
275 #define PS1 OPTION_REG_bits.PS1
276 #define PS2 OPTION_REG_bits.PS2
277 #define PSA OPTION_REG_bits.PSA
278 #define T0SE OPTION_REG_bits.T0SE
279 #define T0CS OPTION_REG_bits.T0CS
280 #define INTEDG OPTION_REG_bits.INTEDG
281 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
282 #endif /* NO_BIT_DEFINES */
284 // ----- PCON bits --------------------
287 unsigned char NOT_BO:1;
288 unsigned char NOT_POR:1;
297 unsigned char NOT_BOR:1;
307 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
309 #ifndef NO_BIT_DEFINES
310 #define NOT_BO PCON_bits.NOT_BO
311 #define NOT_BOR PCON_bits.NOT_BOR
312 #define NOT_POR PCON_bits.NOT_POR
313 #endif /* NO_BIT_DEFINES */
315 // ----- PORTA bits --------------------
328 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
330 #ifndef NO_BIT_DEFINES
331 #define RA0 PORTA_bits.RA0
332 #define RA1 PORTA_bits.RA1
333 #define RA2 PORTA_bits.RA2
334 #define RA3 PORTA_bits.RA3
335 #define RA4 PORTA_bits.RA4
336 #define RA5 PORTA_bits.RA5
337 #endif /* NO_BIT_DEFINES */
339 // ----- PORTB bits --------------------
352 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
354 #ifndef NO_BIT_DEFINES
355 #define RB0 PORTB_bits.RB0
356 #define RB1 PORTB_bits.RB1
357 #define RB2 PORTB_bits.RB2
358 #define RB3 PORTB_bits.RB3
359 #define RB4 PORTB_bits.RB4
360 #define RB5 PORTB_bits.RB5
361 #define RB6 PORTB_bits.RB6
362 #define RB7 PORTB_bits.RB7
363 #endif /* NO_BIT_DEFINES */
365 // ----- STATUS bits --------------------
371 unsigned char NOT_PD:1;
372 unsigned char NOT_TO:1;
378 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
380 #ifndef NO_BIT_DEFINES
381 #define C STATUS_bits.C
382 #define DC STATUS_bits.DC
383 #define Z STATUS_bits.Z
384 #define NOT_PD STATUS_bits.NOT_PD
385 #define NOT_TO STATUS_bits.NOT_TO
386 #define RP0 STATUS_bits.RP0
387 #define RP1 STATUS_bits.RP1
388 #define IRP STATUS_bits.IRP
389 #endif /* NO_BIT_DEFINES */
391 // ----- TRISA bits --------------------
394 unsigned char TRISA0:1;
395 unsigned char TRISA1:1;
396 unsigned char TRISA2:1;
397 unsigned char TRISA3:1;
398 unsigned char TRISA4:1;
399 unsigned char TRISA5:1;
404 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
406 #ifndef NO_BIT_DEFINES
407 #define TRISA0 TRISA_bits.TRISA0
408 #define TRISA1 TRISA_bits.TRISA1
409 #define TRISA2 TRISA_bits.TRISA2
410 #define TRISA3 TRISA_bits.TRISA3
411 #define TRISA4 TRISA_bits.TRISA4
412 #define TRISA5 TRISA_bits.TRISA5
413 #endif /* NO_BIT_DEFINES */
415 // ----- TRISB bits --------------------
418 unsigned char TRISB0:1;
419 unsigned char TRISB1:1;
420 unsigned char TRISB2:1;
421 unsigned char TRISB3:1;
422 unsigned char TRISB4:1;
423 unsigned char TRISB5:1;
424 unsigned char TRISB6:1;
425 unsigned char TRISB7:1;
428 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
430 #ifndef NO_BIT_DEFINES
431 #define TRISB0 TRISB_bits.TRISB0
432 #define TRISB1 TRISB_bits.TRISB1
433 #define TRISB2 TRISB_bits.TRISB2
434 #define TRISB3 TRISB_bits.TRISB3
435 #define TRISB4 TRISB_bits.TRISB4
436 #define TRISB5 TRISB_bits.TRISB5
437 #define TRISB6 TRISB_bits.TRISB6
438 #define TRISB7 TRISB_bits.TRISB7
439 #endif /* NO_BIT_DEFINES */