2 // Register Declarations for Microchip 16C71 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define ADCON0_ADDR 0x0008
36 #define ADRES_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define ADCON1_ADDR 0x0088
45 // Memory organization.
51 // P16C71.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
54 // This header file defines configurations, registers, and other useful bits of
55 // information for the PIC16C71 microcontroller. These names are taken to match
56 // the data sheets as closely as possible.
58 // Note that the processor must be selected before this file is
59 // included. The processor may be selected the following ways:
61 // 1. Command line switch:
62 // C:\ MPASM MYFILE.ASM /PIC16C71
63 // 2. LIST directive in the source file
65 // 3. Processor Type entry in the MPASM full-screen interface
67 //==========================================================================
71 //==========================================================================
75 //1.00 10/31/95 Initial Release
77 //==========================================================================
81 //==========================================================================
84 // MESSG "Processor-header file mismatch. Verify selected processor."
87 //==========================================================================
89 // Register Definitions
91 //==========================================================================
96 //----- Register Files------------------------------------------------------
98 extern __sfr __at (INDF_ADDR) INDF;
99 extern __sfr __at (TMR0_ADDR) TMR0;
100 extern __sfr __at (PCL_ADDR) PCL;
101 extern __sfr __at (STATUS_ADDR) STATUS;
102 extern __sfr __at (FSR_ADDR) FSR;
103 extern __sfr __at (PORTA_ADDR) PORTA;
104 extern __sfr __at (PORTB_ADDR) PORTB;
105 extern __sfr __at (ADCON0_ADDR) ADCON0;
106 extern __sfr __at (ADRES_ADDR) ADRES;
107 extern __sfr __at (PCLATH_ADDR) PCLATH;
108 extern __sfr __at (INTCON_ADDR) INTCON;
110 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
111 extern __sfr __at (TRISA_ADDR) TRISA;
112 extern __sfr __at (TRISB_ADDR) TRISB;
113 extern __sfr __at (ADCON1_ADDR) ADCON1;
115 //----- STATUS Bits --------------------------------------------------------
118 //----- ADCON0 Bits --------------------------------------------------------
121 //----- INTCON Bits --------------------------------------------------------
124 //----- OPTION Bits --------------------------------------------------------
127 //----- ADCON1 Bits --------------------------------------------------------
130 //==========================================================================
134 //==========================================================================
137 // __BADRAM H'07', H'30'-H'7F', H'87'
139 //==========================================================================
141 // Configuration Bits
143 //==========================================================================
145 #define _CP_ON 0x3FEF
146 #define _CP_OFF 0x3FFF
147 #define _PWRTE_ON 0x3FFF
148 #define _PWRTE_OFF 0x3FF7
149 #define _WDT_ON 0x3FFF
150 #define _WDT_OFF 0x3FFB
151 #define _LP_OSC 0x3FFC
152 #define _XT_OSC 0x3FFD
153 #define _HS_OSC 0x3FFE
154 #define _RC_OSC 0x3FFF
158 // ----- ADCON0 bits --------------------
161 unsigned char ADON:1;
162 unsigned char ADIF:1;
164 unsigned char CHS0:1;
165 unsigned char CHS1:1;
167 unsigned char ADCS0:1;
168 unsigned char ADCS1:1;
173 unsigned char NOT_DONE:1;
183 unsigned char GO_DONE:1;
191 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
193 #ifndef NO_BIT_DEFINES
194 #define ADON ADCON0_bits.ADON
195 #define ADIF ADCON0_bits.ADIF
196 #define GO ADCON0_bits.GO
197 #define NOT_DONE ADCON0_bits.NOT_DONE
198 #define GO_DONE ADCON0_bits.GO_DONE
199 #define CHS0 ADCON0_bits.CHS0
200 #define CHS1 ADCON0_bits.CHS1
201 #define ADCS0 ADCON0_bits.ADCS0
202 #define ADCS1 ADCON0_bits.ADCS1
203 #endif /* NO_BIT_DEFINES */
205 // ----- ADCON1 bits --------------------
208 unsigned char PCFG0:1;
209 unsigned char PCFG1:1;
218 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
220 #ifndef NO_BIT_DEFINES
221 #define PCFG0 ADCON1_bits.PCFG0
222 #define PCFG1 ADCON1_bits.PCFG1
223 #endif /* NO_BIT_DEFINES */
225 // ----- INTCON bits --------------------
228 unsigned char RBIF:1;
229 unsigned char INTF:1;
230 unsigned char T0IF:1;
231 unsigned char RBIE:1;
232 unsigned char INTE:1;
233 unsigned char T0IE:1;
234 unsigned char ADIE:1;
238 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
240 #ifndef NO_BIT_DEFINES
241 #define RBIF INTCON_bits.RBIF
242 #define INTF INTCON_bits.INTF
243 #define T0IF INTCON_bits.T0IF
244 #define RBIE INTCON_bits.RBIE
245 #define INTE INTCON_bits.INTE
246 #define T0IE INTCON_bits.T0IE
247 #define ADIE INTCON_bits.ADIE
248 #define GIE INTCON_bits.GIE
249 #endif /* NO_BIT_DEFINES */
251 // ----- OPTION_REG bits --------------------
258 unsigned char T0SE:1;
259 unsigned char T0CS:1;
260 unsigned char INTEDG:1;
261 unsigned char NOT_RBPU:1;
263 } __OPTION_REG_bits_t;
264 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
266 #ifndef NO_BIT_DEFINES
267 #define PS0 OPTION_REG_bits.PS0
268 #define PS1 OPTION_REG_bits.PS1
269 #define PS2 OPTION_REG_bits.PS2
270 #define PSA OPTION_REG_bits.PSA
271 #define T0SE OPTION_REG_bits.T0SE
272 #define T0CS OPTION_REG_bits.T0CS
273 #define INTEDG OPTION_REG_bits.INTEDG
274 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
275 #endif /* NO_BIT_DEFINES */
277 // ----- PORTA bits --------------------
290 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
292 #ifndef NO_BIT_DEFINES
293 #define RA0 PORTA_bits.RA0
294 #define RA1 PORTA_bits.RA1
295 #define RA2 PORTA_bits.RA2
296 #define RA3 PORTA_bits.RA3
297 #define RA4 PORTA_bits.RA4
298 #define RA5 PORTA_bits.RA5
299 #endif /* NO_BIT_DEFINES */
301 // ----- PORTB bits --------------------
314 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
316 #ifndef NO_BIT_DEFINES
317 #define RB0 PORTB_bits.RB0
318 #define RB1 PORTB_bits.RB1
319 #define RB2 PORTB_bits.RB2
320 #define RB3 PORTB_bits.RB3
321 #define RB4 PORTB_bits.RB4
322 #define RB5 PORTB_bits.RB5
323 #define RB6 PORTB_bits.RB6
324 #define RB7 PORTB_bits.RB7
325 #endif /* NO_BIT_DEFINES */
327 // ----- STATUS bits --------------------
333 unsigned char NOT_PD:1;
334 unsigned char NOT_TO:1;
340 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
342 #ifndef NO_BIT_DEFINES
343 #define C STATUS_bits.C
344 #define DC STATUS_bits.DC
345 #define Z STATUS_bits.Z
346 #define NOT_PD STATUS_bits.NOT_PD
347 #define NOT_TO STATUS_bits.NOT_TO
348 #define RP0 STATUS_bits.RP0
349 #define RP1 STATUS_bits.RP1
350 #define IRP STATUS_bits.IRP
351 #endif /* NO_BIT_DEFINES */
353 // ----- TRISA bits --------------------
356 unsigned char TRISA0:1;
357 unsigned char TRISA1:1;
358 unsigned char TRISA2:1;
359 unsigned char TRISA3:1;
360 unsigned char TRISA4:1;
361 unsigned char TRISA5:1;
366 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
368 #ifndef NO_BIT_DEFINES
369 #define TRISA0 TRISA_bits.TRISA0
370 #define TRISA1 TRISA_bits.TRISA1
371 #define TRISA2 TRISA_bits.TRISA2
372 #define TRISA3 TRISA_bits.TRISA3
373 #define TRISA4 TRISA_bits.TRISA4
374 #define TRISA5 TRISA_bits.TRISA5
375 #endif /* NO_BIT_DEFINES */
377 // ----- TRISB bits --------------------
380 unsigned char TRISB0:1;
381 unsigned char TRISB1:1;
382 unsigned char TRISB2:1;
383 unsigned char TRISB3:1;
384 unsigned char TRISB4:1;
385 unsigned char TRISB5:1;
386 unsigned char TRISB6:1;
387 unsigned char TRISB7:1;
390 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
392 #ifndef NO_BIT_DEFINES
393 #define TRISB0 TRISB_bits.TRISB0
394 #define TRISB1 TRISB_bits.TRISB1
395 #define TRISB2 TRISB_bits.TRISB2
396 #define TRISB3 TRISB_bits.TRISB3
397 #define TRISB4 TRISB_bits.TRISB4
398 #define TRISB5 TRISB_bits.TRISB5
399 #define TRISB6 TRISB_bits.TRISB6
400 #define TRISB7 TRISB_bits.TRISB7
401 #endif /* NO_BIT_DEFINES */