2 // Register Declarations for Microchip 16C71 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define ADCON0_ADDR 0x0008
36 #define ADRES_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define ADCON1_ADDR 0x0088
45 // Memory organization.
51 // P16C71.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
54 // This header file defines configurations, registers, and other useful bits of
55 // information for the PIC16C71 microcontroller. These names are taken to match
56 // the data sheets as closely as possible.
58 // Note that the processor must be selected before this file is
59 // included. The processor may be selected the following ways:
61 // 1. Command line switch:
62 // C:\ MPASM MYFILE.ASM /PIC16C71
63 // 2. LIST directive in the source file
65 // 3. Processor Type entry in the MPASM full-screen interface
67 //==========================================================================
71 //==========================================================================
75 //1.00 10/31/95 Initial Release
77 //==========================================================================
81 //==========================================================================
84 // MESSG "Processor-header file mismatch. Verify selected processor."
87 //==========================================================================
89 // Register Definitions
91 //==========================================================================
96 //----- Register Files------------------------------------------------------
98 extern __data __at (INDF_ADDR) volatile char INDF;
99 extern __sfr __at (TMR0_ADDR) TMR0;
100 extern __data __at (PCL_ADDR) volatile char PCL;
101 extern __sfr __at (STATUS_ADDR) STATUS;
102 extern __sfr __at (FSR_ADDR) FSR;
103 extern __sfr __at (PORTA_ADDR) PORTA;
104 extern __sfr __at (PORTB_ADDR) PORTB;
105 extern __sfr __at (ADCON0_ADDR) ADCON0;
106 extern __sfr __at (ADRES_ADDR) ADRES;
107 extern __sfr __at (PCLATH_ADDR) PCLATH;
108 extern __sfr __at (INTCON_ADDR) INTCON;
110 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
111 extern __sfr __at (TRISA_ADDR) TRISA;
112 extern __sfr __at (TRISB_ADDR) TRISB;
113 extern __sfr __at (ADCON1_ADDR) ADCON1;
115 //----- STATUS Bits --------------------------------------------------------
118 //----- ADCON0 Bits --------------------------------------------------------
121 //----- INTCON Bits --------------------------------------------------------
124 //----- OPTION Bits --------------------------------------------------------
127 //----- ADCON1 Bits --------------------------------------------------------
130 //==========================================================================
134 //==========================================================================
137 // __BADRAM H'07', H'30'-H'7F', H'87'
139 //==========================================================================
141 // Configuration Bits
143 //==========================================================================
145 #define _CP_ON 0x3FEF
146 #define _CP_OFF 0x3FFF
147 #define _PWRTE_ON 0x3FFF
148 #define _PWRTE_OFF 0x3FF7
149 #define _WDT_ON 0x3FFF
150 #define _WDT_OFF 0x3FFB
151 #define _LP_OSC 0x3FFC
152 #define _XT_OSC 0x3FFD
153 #define _HS_OSC 0x3FFE
154 #define _RC_OSC 0x3FFF
158 // ----- ADCON0 bits --------------------
161 unsigned char ADON:1;
162 unsigned char ADIF:1;
164 unsigned char CHS0:1;
165 unsigned char CHS1:1;
167 unsigned char ADCS0:1;
168 unsigned char ADCS1:1;
173 unsigned char NOT_DONE:1;
183 unsigned char GO_DONE:1;
191 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
193 #define ADON ADCON0_bits.ADON
194 #define ADIF ADCON0_bits.ADIF
195 #define GO ADCON0_bits.GO
196 #define NOT_DONE ADCON0_bits.NOT_DONE
197 #define GO_DONE ADCON0_bits.GO_DONE
198 #define CHS0 ADCON0_bits.CHS0
199 #define CHS1 ADCON0_bits.CHS1
200 #define ADCS0 ADCON0_bits.ADCS0
201 #define ADCS1 ADCON0_bits.ADCS1
203 // ----- ADCON1 bits --------------------
206 unsigned char PCFG0:1;
207 unsigned char PCFG1:1;
216 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
218 #define PCFG0 ADCON1_bits.PCFG0
219 #define PCFG1 ADCON1_bits.PCFG1
221 // ----- INTCON bits --------------------
224 unsigned char RBIF:1;
225 unsigned char INTF:1;
226 unsigned char T0IF:1;
227 unsigned char RBIE:1;
228 unsigned char INTE:1;
229 unsigned char T0IE:1;
230 unsigned char ADIE:1;
234 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
236 #define RBIF INTCON_bits.RBIF
237 #define INTF INTCON_bits.INTF
238 #define T0IF INTCON_bits.T0IF
239 #define RBIE INTCON_bits.RBIE
240 #define INTE INTCON_bits.INTE
241 #define T0IE INTCON_bits.T0IE
242 #define ADIE INTCON_bits.ADIE
243 #define GIE INTCON_bits.GIE
245 // ----- OPTION_REG bits --------------------
252 unsigned char T0SE:1;
253 unsigned char T0CS:1;
254 unsigned char INTEDG:1;
255 unsigned char NOT_RBPU:1;
257 } __OPTION_REG_bits_t;
258 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
260 #define PS0 OPTION_REG_bits.PS0
261 #define PS1 OPTION_REG_bits.PS1
262 #define PS2 OPTION_REG_bits.PS2
263 #define PSA OPTION_REG_bits.PSA
264 #define T0SE OPTION_REG_bits.T0SE
265 #define T0CS OPTION_REG_bits.T0CS
266 #define INTEDG OPTION_REG_bits.INTEDG
267 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
269 // ----- STATUS bits --------------------
275 unsigned char NOT_PD:1;
276 unsigned char NOT_TO:1;
282 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
284 #define C STATUS_bits.C
285 #define DC STATUS_bits.DC
286 #define Z STATUS_bits.Z
287 #define NOT_PD STATUS_bits.NOT_PD
288 #define NOT_TO STATUS_bits.NOT_TO
289 #define RP0 STATUS_bits.RP0
290 #define RP1 STATUS_bits.RP1
291 #define IRP STATUS_bits.IRP