2 // Register Declarations for Microchip 16C71 Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define ADCON0_ADDR 0x0008
36 #define ADRES_ADDR 0x0009
37 #define PCLATH_ADDR 0x000A
38 #define INTCON_ADDR 0x000B
39 #define OPTION_REG_ADDR 0x0081
40 #define TRISA_ADDR 0x0085
41 #define TRISB_ADDR 0x0086
42 #define ADCON1_ADDR 0x0088
45 // Memory organization.
48 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
49 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
50 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
51 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
52 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
53 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
54 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
55 #pragma memmap ADCON0_ADDR ADCON0_ADDR SFR 0x000 // ADCON0
56 #pragma memmap ADRES_ADDR ADRES_ADDR SFR 0x000 // ADRES
57 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
58 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
59 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
60 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
61 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
62 #pragma memmap ADCON1_ADDR ADCON1_ADDR SFR 0x000 // ADCON1
66 // P16C71.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
69 // This header file defines configurations, registers, and other useful bits of
70 // information for the PIC16C71 microcontroller. These names are taken to match
71 // the data sheets as closely as possible.
73 // Note that the processor must be selected before this file is
74 // included. The processor may be selected the following ways:
76 // 1. Command line switch:
77 // C:\ MPASM MYFILE.ASM /PIC16C71
78 // 2. LIST directive in the source file
80 // 3. Processor Type entry in the MPASM full-screen interface
82 //==========================================================================
86 //==========================================================================
90 //1.00 10/31/95 Initial Release
92 //==========================================================================
96 //==========================================================================
99 // MESSG "Processor-header file mismatch. Verify selected processor."
102 //==========================================================================
104 // Register Definitions
106 //==========================================================================
111 //----- Register Files------------------------------------------------------
113 extern data __at (INDF_ADDR) volatile char INDF;
114 extern sfr __at (TMR0_ADDR) TMR0;
115 extern data __at (PCL_ADDR) volatile char PCL;
116 extern sfr __at (STATUS_ADDR) STATUS;
117 extern sfr __at (FSR_ADDR) FSR;
118 extern sfr __at (PORTA_ADDR) PORTA;
119 extern sfr __at (PORTB_ADDR) PORTB;
120 extern sfr __at (ADCON0_ADDR) ADCON0;
121 extern sfr __at (ADRES_ADDR) ADRES;
122 extern sfr __at (PCLATH_ADDR) PCLATH;
123 extern sfr __at (INTCON_ADDR) INTCON;
125 extern sfr __at (OPTION_REG_ADDR) OPTION_REG;
126 extern sfr __at (TRISA_ADDR) TRISA;
127 extern sfr __at (TRISB_ADDR) TRISB;
128 extern sfr __at (ADCON1_ADDR) ADCON1;
130 //----- STATUS Bits --------------------------------------------------------
133 //----- ADCON0 Bits --------------------------------------------------------
136 //----- INTCON Bits --------------------------------------------------------
139 //----- OPTION Bits --------------------------------------------------------
142 //----- ADCON1 Bits --------------------------------------------------------
145 //==========================================================================
149 //==========================================================================
152 // __BADRAM H'07', H'30'-H'7F', H'87'
154 //==========================================================================
156 // Configuration Bits
158 //==========================================================================
160 #define _CP_ON 0x3FEF
161 #define _CP_OFF 0x3FFF
162 #define _PWRTE_ON 0x3FFF
163 #define _PWRTE_OFF 0x3FF7
164 #define _WDT_ON 0x3FFF
165 #define _WDT_OFF 0x3FFB
166 #define _LP_OSC 0x3FFC
167 #define _XT_OSC 0x3FFD
168 #define _HS_OSC 0x3FFE
169 #define _RC_OSC 0x3FFF
173 // ----- ADCON0 bits --------------------
176 unsigned char ADON:1;
177 unsigned char ADIF:1;
179 unsigned char CHS0:1;
180 unsigned char CHS1:1;
182 unsigned char ADCS0:1;
183 unsigned char ADCS1:1;
188 unsigned char NOT_DONE:1;
198 unsigned char GO_DONE:1;
206 extern volatile __ADCON0_bits_t __at(ADCON0_ADDR) ADCON0_bits;
208 #define ADON ADCON0_bits.ADON
209 #define ADIF ADCON0_bits.ADIF
210 #define GO ADCON0_bits.GO
211 #define NOT_DONE ADCON0_bits.NOT_DONE
212 #define GO_DONE ADCON0_bits.GO_DONE
213 #define CHS0 ADCON0_bits.CHS0
214 #define CHS1 ADCON0_bits.CHS1
215 #define ADCS0 ADCON0_bits.ADCS0
216 #define ADCS1 ADCON0_bits.ADCS1
218 // ----- ADCON1 bits --------------------
221 unsigned char PCFG0:1;
222 unsigned char PCFG1:1;
231 extern volatile __ADCON1_bits_t __at(ADCON1_ADDR) ADCON1_bits;
233 #define PCFG0 ADCON1_bits.PCFG0
234 #define PCFG1 ADCON1_bits.PCFG1
236 // ----- INTCON bits --------------------
239 unsigned char RBIF:1;
240 unsigned char INTF:1;
241 unsigned char T0IF:1;
242 unsigned char RBIE:1;
243 unsigned char INTE:1;
244 unsigned char T0IE:1;
245 unsigned char ADIE:1;
249 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
251 #define RBIF INTCON_bits.RBIF
252 #define INTF INTCON_bits.INTF
253 #define T0IF INTCON_bits.T0IF
254 #define RBIE INTCON_bits.RBIE
255 #define INTE INTCON_bits.INTE
256 #define T0IE INTCON_bits.T0IE
257 #define ADIE INTCON_bits.ADIE
258 #define GIE INTCON_bits.GIE
260 // ----- OPTION_REG bits --------------------
267 unsigned char T0SE:1;
268 unsigned char T0CS:1;
269 unsigned char INTEDG:1;
270 unsigned char NOT_RBPU:1;
272 } __OPTION_REG_bits_t;
273 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
275 #define PS0 OPTION_REG_bits.PS0
276 #define PS1 OPTION_REG_bits.PS1
277 #define PS2 OPTION_REG_bits.PS2
278 #define PSA OPTION_REG_bits.PSA
279 #define T0SE OPTION_REG_bits.T0SE
280 #define T0CS OPTION_REG_bits.T0CS
281 #define INTEDG OPTION_REG_bits.INTEDG
282 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
284 // ----- STATUS bits --------------------
290 unsigned char NOT_PD:1;
291 unsigned char NOT_TO:1;
297 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
299 #define C STATUS_bits.C
300 #define DC STATUS_bits.DC
301 #define Z STATUS_bits.Z
302 #define NOT_PD STATUS_bits.NOT_PD
303 #define NOT_TO STATUS_bits.NOT_TO
304 #define RP0 STATUS_bits.RP0
305 #define RP1 STATUS_bits.RP1
306 #define IRP STATUS_bits.IRP