2 // Register Declarations for Microchip 16C65B Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define TRISD_ADDR 0x0088
63 #define TRISE_ADDR 0x0089
64 #define PIE1_ADDR 0x008C
65 #define PIE2_ADDR 0x008D
66 #define PCON_ADDR 0x008E
67 #define PR2_ADDR 0x0092
68 #define SSPADD_ADDR 0x0093
69 #define SSPSTAT_ADDR 0x0094
70 #define TXSTA_ADDR 0x0098
71 #define SPBRG_ADDR 0x0099
74 // Memory organization.
77 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
78 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
79 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
80 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
81 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
82 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
83 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
84 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
85 #pragma memmap PORTD_ADDR PORTD_ADDR SFR 0x000 // PORTD
86 #pragma memmap PORTE_ADDR PORTE_ADDR SFR 0x000 // PORTE
87 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
88 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
89 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
90 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
91 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
92 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
93 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
94 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
95 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
96 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
97 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
98 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
99 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
100 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
101 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
102 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
103 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
104 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
105 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
106 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
107 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
108 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
109 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
110 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
111 #pragma memmap TRISD_ADDR TRISD_ADDR SFR 0x000 // TRISD
112 #pragma memmap TRISE_ADDR TRISE_ADDR SFR 0x000 // TRISE
113 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
114 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
115 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
116 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
117 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
118 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
119 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
120 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
124 // P16C65B.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
127 // This header file defines configurations, registers, and other useful bits of
128 // information for the PIC16C65B microcontroller. These names are taken to match
129 // the data sheets as closely as possible.
131 // Note that the processor must be selected before this file is
132 // included. The processor may be selected the following ways:
134 // 1. Command line switch:
135 // C:\ MPASM MYFILE.ASM /PIC16C65B
136 // 2. LIST directive in the source file
138 // 3. Processor Type entry in the MPASM full-screen interface
140 //==========================================================================
144 //==========================================================================
148 //1.00 12/17/97 Initial Release
150 //==========================================================================
154 //==========================================================================
157 // MESSG "Processor-header file mismatch. Verify selected processor."
160 //==========================================================================
162 // Register Definitions
164 //==========================================================================
169 //----- Register Files------------------------------------------------------
171 extern __data __at (INDF_ADDR) volatile char INDF;
172 extern __sfr __at (TMR0_ADDR) TMR0;
173 extern __data __at (PCL_ADDR) volatile char PCL;
174 extern __sfr __at (STATUS_ADDR) STATUS;
175 extern __sfr __at (FSR_ADDR) FSR;
176 extern __sfr __at (PORTA_ADDR) PORTA;
177 extern __sfr __at (PORTB_ADDR) PORTB;
178 extern __sfr __at (PORTC_ADDR) PORTC;
179 extern __sfr __at (PORTD_ADDR) PORTD;
180 extern __sfr __at (PORTE_ADDR) PORTE;
181 extern __sfr __at (PCLATH_ADDR) PCLATH;
182 extern __sfr __at (INTCON_ADDR) INTCON;
183 extern __sfr __at (PIR1_ADDR) PIR1;
184 extern __sfr __at (PIR2_ADDR) PIR2;
185 extern __sfr __at (TMR1L_ADDR) TMR1L;
186 extern __sfr __at (TMR1H_ADDR) TMR1H;
187 extern __sfr __at (T1CON_ADDR) T1CON;
188 extern __sfr __at (TMR2_ADDR) TMR2;
189 extern __sfr __at (T2CON_ADDR) T2CON;
190 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
191 extern __sfr __at (SSPCON_ADDR) SSPCON;
192 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
193 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
194 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
195 extern __sfr __at (RCSTA_ADDR) RCSTA;
196 extern __sfr __at (TXREG_ADDR) TXREG;
197 extern __sfr __at (RCREG_ADDR) RCREG;
198 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
199 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
200 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
202 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
203 extern __sfr __at (TRISA_ADDR) TRISA;
204 extern __sfr __at (TRISB_ADDR) TRISB;
205 extern __sfr __at (TRISC_ADDR) TRISC;
206 extern __sfr __at (TRISD_ADDR) TRISD;
207 extern __sfr __at (TRISE_ADDR) TRISE;
208 extern __sfr __at (PIE1_ADDR) PIE1;
209 extern __sfr __at (PIE2_ADDR) PIE2;
210 extern __sfr __at (PCON_ADDR) PCON;
211 extern __sfr __at (PR2_ADDR) PR2;
212 extern __sfr __at (SSPADD_ADDR) SSPADD;
213 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
214 extern __sfr __at (TXSTA_ADDR) TXSTA;
215 extern __sfr __at (SPBRG_ADDR) SPBRG;
217 //----- STATUS Bits --------------------------------------------------------
220 //----- INTCON Bits --------------------------------------------------------
223 //----- PIR1 Bits ----------------------------------------------------------
226 //----- PIR2 Bits ----------------------------------------------------------
229 //----- T1CON Bits ---------------------------------------------------------
232 //----- T2CON Bits ---------------------------------------------------------
235 //----- SSPCON Bits --------------------------------------------------------
238 //----- CCP1CON Bits -------------------------------------------------------
241 //----- RCSTA Bits ---------------------------------------------------------
244 //----- CCP2CON Bits -------------------------------------------------------
247 //----- OPTION Bits --------------------------------------------------------
250 //----- TRISE Bits ---------------------------------------------------------
253 //----- PIE1 Bits ----------------------------------------------------------
256 //----- PIE2 Bits ----------------------------------------------------------
259 //----- PCON Bits ----------------------------------------------------------
262 //----- SSPSTAT Bits -------------------------------------------------------
265 //----- TXSTA Bits ---------------------------------------------------------
268 //==========================================================================
272 //==========================================================================
275 // __BADRAM H'1E'-H'1F',H'8F'-H'91', H'95'-H'97', H'9A'-H'9F'
277 //==========================================================================
279 // Configuration Bits
281 //==========================================================================
283 #define _BODEN_ON 0x3FFF
284 #define _BODEN_OFF 0x3FBF
285 #define _CP_ALL 0x00CF
286 #define _CP_75 0x15DF
287 #define _CP_50 0x2AEF
288 #define _CP_OFF 0x3FFF
289 #define _PWRTE_OFF 0x3FFF
290 #define _PWRTE_ON 0x3FF7
291 #define _WDT_ON 0x3FFF
292 #define _WDT_OFF 0x3FFB
293 #define _LP_OSC 0x3FFC
294 #define _XT_OSC 0x3FFD
295 #define _HS_OSC 0x3FFE
296 #define _RC_OSC 0x3FFF
300 // ----- CCP1CON bits --------------------
303 unsigned char CCP1M0:1;
304 unsigned char CCP1M1:1;
305 unsigned char CCP1M2:1;
306 unsigned char CCP1M3:1;
307 unsigned char CCP1Y:1;
308 unsigned char CCP1X:1;
313 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
315 #define CCP1M0 CCP1CON_bits.CCP1M0
316 #define CCP1M1 CCP1CON_bits.CCP1M1
317 #define CCP1M2 CCP1CON_bits.CCP1M2
318 #define CCP1M3 CCP1CON_bits.CCP1M3
319 #define CCP1Y CCP1CON_bits.CCP1Y
320 #define CCP1X CCP1CON_bits.CCP1X
322 // ----- CCP2CON bits --------------------
325 unsigned char CCP2M0:1;
326 unsigned char CCP2M1:1;
327 unsigned char CCP2M2:1;
328 unsigned char CCP2M3:1;
329 unsigned char CCP2Y:1;
330 unsigned char CCP2X:1;
335 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
337 #define CCP2M0 CCP2CON_bits.CCP2M0
338 #define CCP2M1 CCP2CON_bits.CCP2M1
339 #define CCP2M2 CCP2CON_bits.CCP2M2
340 #define CCP2M3 CCP2CON_bits.CCP2M3
341 #define CCP2Y CCP2CON_bits.CCP2Y
342 #define CCP2X CCP2CON_bits.CCP2X
344 // ----- INTCON bits --------------------
347 unsigned char RBIF:1;
348 unsigned char INTF:1;
349 unsigned char T0IF:1;
350 unsigned char RBIE:1;
351 unsigned char INTE:1;
352 unsigned char T0IE:1;
353 unsigned char PEIE:1;
357 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
359 #define RBIF INTCON_bits.RBIF
360 #define INTF INTCON_bits.INTF
361 #define T0IF INTCON_bits.T0IF
362 #define RBIE INTCON_bits.RBIE
363 #define INTE INTCON_bits.INTE
364 #define T0IE INTCON_bits.T0IE
365 #define PEIE INTCON_bits.PEIE
366 #define GIE INTCON_bits.GIE
368 // ----- OPTION_REG bits --------------------
375 unsigned char T0SE:1;
376 unsigned char T0CS:1;
377 unsigned char INTEDG:1;
378 unsigned char NOT_RBPU:1;
380 } __OPTION_REG_bits_t;
381 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
383 #define PS0 OPTION_REG_bits.PS0
384 #define PS1 OPTION_REG_bits.PS1
385 #define PS2 OPTION_REG_bits.PS2
386 #define PSA OPTION_REG_bits.PSA
387 #define T0SE OPTION_REG_bits.T0SE
388 #define T0CS OPTION_REG_bits.T0CS
389 #define INTEDG OPTION_REG_bits.INTEDG
390 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
392 // ----- PCON bits --------------------
395 unsigned char NOT_BO:1;
396 unsigned char NOT_POR:1;
405 unsigned char NOT_BOR:1;
415 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
417 #define NOT_BO PCON_bits.NOT_BO
418 #define NOT_BOR PCON_bits.NOT_BOR
419 #define NOT_POR PCON_bits.NOT_POR
421 // ----- PIE1 bits --------------------
424 unsigned char TMR1IE:1;
425 unsigned char TMR2IE:1;
426 unsigned char CCP1IE:1;
427 unsigned char SSPIE:1;
428 unsigned char TXIE:1;
429 unsigned char RCIE:1;
431 unsigned char PSPIE:1;
434 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
436 #define TMR1IE PIE1_bits.TMR1IE
437 #define TMR2IE PIE1_bits.TMR2IE
438 #define CCP1IE PIE1_bits.CCP1IE
439 #define SSPIE PIE1_bits.SSPIE
440 #define TXIE PIE1_bits.TXIE
441 #define RCIE PIE1_bits.RCIE
442 #define PSPIE PIE1_bits.PSPIE
444 // ----- PIE2 bits --------------------
447 unsigned char CCP2IE:1;
457 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
459 #define CCP2IE PIE2_bits.CCP2IE
461 // ----- PIR1 bits --------------------
464 unsigned char TMR1IF:1;
465 unsigned char TMR2IF:1;
466 unsigned char CCP1IF:1;
467 unsigned char SSPIF:1;
468 unsigned char TXIF:1;
469 unsigned char RCIF:1;
471 unsigned char PSPIF:1;
474 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
476 #define TMR1IF PIR1_bits.TMR1IF
477 #define TMR2IF PIR1_bits.TMR2IF
478 #define CCP1IF PIR1_bits.CCP1IF
479 #define SSPIF PIR1_bits.SSPIF
480 #define TXIF PIR1_bits.TXIF
481 #define RCIF PIR1_bits.RCIF
482 #define PSPIF PIR1_bits.PSPIF
484 // ----- PIR2 bits --------------------
487 unsigned char CCP2IF:1;
497 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
499 #define CCP2IF PIR2_bits.CCP2IF
501 // ----- RCSTA bits --------------------
504 unsigned char RX9D:1;
505 unsigned char OERR:1;
506 unsigned char FERR:1;
508 unsigned char CREN:1;
509 unsigned char SREN:1;
511 unsigned char SPEN:1;
514 unsigned char RCD8:1;
530 unsigned char NOT_RC8:1;
540 unsigned char RC8_9:1;
544 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
546 #define RX9D RCSTA_bits.RX9D
547 #define RCD8 RCSTA_bits.RCD8
548 #define OERR RCSTA_bits.OERR
549 #define FERR RCSTA_bits.FERR
550 #define CREN RCSTA_bits.CREN
551 #define SREN RCSTA_bits.SREN
552 #define RX9 RCSTA_bits.RX9
553 #define RC9 RCSTA_bits.RC9
554 #define NOT_RC8 RCSTA_bits.NOT_RC8
555 #define RC8_9 RCSTA_bits.RC8_9
556 #define SPEN RCSTA_bits.SPEN
558 // ----- SSPCON bits --------------------
561 unsigned char SSPM0:1;
562 unsigned char SSPM1:1;
563 unsigned char SSPM2:1;
564 unsigned char SSPM3:1;
566 unsigned char SSPEN:1;
567 unsigned char SSPOV:1;
568 unsigned char WCOL:1;
571 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
573 #define SSPM0 SSPCON_bits.SSPM0
574 #define SSPM1 SSPCON_bits.SSPM1
575 #define SSPM2 SSPCON_bits.SSPM2
576 #define SSPM3 SSPCON_bits.SSPM3
577 #define CKP SSPCON_bits.CKP
578 #define SSPEN SSPCON_bits.SSPEN
579 #define SSPOV SSPCON_bits.SSPOV
580 #define WCOL SSPCON_bits.WCOL
582 // ----- SSPSTAT bits --------------------
597 unsigned char I2C_READ:1;
598 unsigned char I2C_START:1;
599 unsigned char I2C_STOP:1;
600 unsigned char I2C_DATA:1;
607 unsigned char NOT_W:1;
610 unsigned char NOT_A:1;
617 unsigned char NOT_WRITE:1;
620 unsigned char NOT_ADDRESS:1;
637 unsigned char READ_WRITE:1;
640 unsigned char DATA_ADDRESS:1;
645 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
647 #define BF SSPSTAT_bits.BF
648 #define UA SSPSTAT_bits.UA
649 #define R SSPSTAT_bits.R
650 #define I2C_READ SSPSTAT_bits.I2C_READ
651 #define NOT_W SSPSTAT_bits.NOT_W
652 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
653 #define R_W SSPSTAT_bits.R_W
654 #define READ_WRITE SSPSTAT_bits.READ_WRITE
655 #define S SSPSTAT_bits.S
656 #define I2C_START SSPSTAT_bits.I2C_START
657 #define P SSPSTAT_bits.P
658 #define I2C_STOP SSPSTAT_bits.I2C_STOP
659 #define D SSPSTAT_bits.D
660 #define I2C_DATA SSPSTAT_bits.I2C_DATA
661 #define NOT_A SSPSTAT_bits.NOT_A
662 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
663 #define D_A SSPSTAT_bits.D_A
664 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
665 #define CKE SSPSTAT_bits.CKE
666 #define SMP SSPSTAT_bits.SMP
668 // ----- STATUS bits --------------------
674 unsigned char NOT_PD:1;
675 unsigned char NOT_TO:1;
681 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
683 #define C STATUS_bits.C
684 #define DC STATUS_bits.DC
685 #define Z STATUS_bits.Z
686 #define NOT_PD STATUS_bits.NOT_PD
687 #define NOT_TO STATUS_bits.NOT_TO
688 #define RP0 STATUS_bits.RP0
689 #define RP1 STATUS_bits.RP1
690 #define IRP STATUS_bits.IRP
692 // ----- T1CON bits --------------------
695 unsigned char TMR1ON:1;
696 unsigned char TMR1CS:1;
697 unsigned char NOT_T1SYNC:1;
698 unsigned char T1OSCEN:1;
699 unsigned char T1CKPS0:1;
700 unsigned char T1CKPS1:1;
707 unsigned char T1INSYNC:1;
715 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
717 #define TMR1ON T1CON_bits.TMR1ON
718 #define TMR1CS T1CON_bits.TMR1CS
719 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
720 #define T1INSYNC T1CON_bits.T1INSYNC
721 #define T1OSCEN T1CON_bits.T1OSCEN
722 #define T1CKPS0 T1CON_bits.T1CKPS0
723 #define T1CKPS1 T1CON_bits.T1CKPS1
725 // ----- T2CON bits --------------------
728 unsigned char T2CKPS0:1;
729 unsigned char T2CKPS1:1;
730 unsigned char TMR2ON:1;
731 unsigned char TOUTPS0:1;
732 unsigned char TOUTPS1:1;
733 unsigned char TOUTPS2:1;
734 unsigned char TOUTPS3:1;
738 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
740 #define T2CKPS0 T2CON_bits.T2CKPS0
741 #define T2CKPS1 T2CON_bits.T2CKPS1
742 #define TMR2ON T2CON_bits.TMR2ON
743 #define TOUTPS0 T2CON_bits.TOUTPS0
744 #define TOUTPS1 T2CON_bits.TOUTPS1
745 #define TOUTPS2 T2CON_bits.TOUTPS2
746 #define TOUTPS3 T2CON_bits.TOUTPS3
748 // ----- TRISE bits --------------------
751 unsigned char TRISE0:1;
752 unsigned char TRISE1:1;
753 unsigned char TRISE2:1;
755 unsigned char PSPMODE:1;
756 unsigned char IBOV:1;
761 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
763 #define TRISE0 TRISE_bits.TRISE0
764 #define TRISE1 TRISE_bits.TRISE1
765 #define TRISE2 TRISE_bits.TRISE2
766 #define PSPMODE TRISE_bits.PSPMODE
767 #define IBOV TRISE_bits.IBOV
768 #define OBF TRISE_bits.OBF
769 #define IBF TRISE_bits.IBF
771 // ----- TXSTA bits --------------------
774 unsigned char TX9D:1;
775 unsigned char TRMT:1;
776 unsigned char BRGH:1;
778 unsigned char SYNC:1;
779 unsigned char TXEN:1;
781 unsigned char CSRC:1;
784 unsigned char TXD8:1;
790 unsigned char NOT_TX8:1;
800 unsigned char TX8_9:1;
804 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
806 #define TX9D TXSTA_bits.TX9D
807 #define TXD8 TXSTA_bits.TXD8
808 #define TRMT TXSTA_bits.TRMT
809 #define BRGH TXSTA_bits.BRGH
810 #define SYNC TXSTA_bits.SYNC
811 #define TXEN TXSTA_bits.TXEN
812 #define TX9 TXSTA_bits.TX9
813 #define NOT_TX8 TXSTA_bits.NOT_TX8
814 #define TX8_9 TXSTA_bits.TX8_9
815 #define CSRC TXSTA_bits.CSRC