2 // Register Declarations for Microchip 16C65B Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PORTD_ADDR 0x0008
37 #define PORTE_ADDR 0x0009
38 #define PCLATH_ADDR 0x000A
39 #define INTCON_ADDR 0x000B
40 #define PIR1_ADDR 0x000C
41 #define PIR2_ADDR 0x000D
42 #define TMR1L_ADDR 0x000E
43 #define TMR1H_ADDR 0x000F
44 #define T1CON_ADDR 0x0010
45 #define TMR2_ADDR 0x0011
46 #define T2CON_ADDR 0x0012
47 #define SSPBUF_ADDR 0x0013
48 #define SSPCON_ADDR 0x0014
49 #define CCPR1L_ADDR 0x0015
50 #define CCPR1H_ADDR 0x0016
51 #define CCP1CON_ADDR 0x0017
52 #define RCSTA_ADDR 0x0018
53 #define TXREG_ADDR 0x0019
54 #define RCREG_ADDR 0x001A
55 #define CCPR2L_ADDR 0x001B
56 #define CCPR2H_ADDR 0x001C
57 #define CCP2CON_ADDR 0x001D
58 #define OPTION_REG_ADDR 0x0081
59 #define TRISA_ADDR 0x0085
60 #define TRISB_ADDR 0x0086
61 #define TRISC_ADDR 0x0087
62 #define TRISD_ADDR 0x0088
63 #define TRISE_ADDR 0x0089
64 #define PIE1_ADDR 0x008C
65 #define PIE2_ADDR 0x008D
66 #define PCON_ADDR 0x008E
67 #define PR2_ADDR 0x0092
68 #define SSPADD_ADDR 0x0093
69 #define SSPSTAT_ADDR 0x0094
70 #define TXSTA_ADDR 0x0098
71 #define SPBRG_ADDR 0x0099
74 // Memory organization.
80 // P16C65B.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
83 // This header file defines configurations, registers, and other useful bits of
84 // information for the PIC16C65B microcontroller. These names are taken to match
85 // the data sheets as closely as possible.
87 // Note that the processor must be selected before this file is
88 // included. The processor may be selected the following ways:
90 // 1. Command line switch:
91 // C:\ MPASM MYFILE.ASM /PIC16C65B
92 // 2. LIST directive in the source file
94 // 3. Processor Type entry in the MPASM full-screen interface
96 //==========================================================================
100 //==========================================================================
104 //1.00 12/17/97 Initial Release
106 //==========================================================================
110 //==========================================================================
113 // MESSG "Processor-header file mismatch. Verify selected processor."
116 //==========================================================================
118 // Register Definitions
120 //==========================================================================
125 //----- Register Files------------------------------------------------------
127 extern __sfr __at (INDF_ADDR) INDF;
128 extern __sfr __at (TMR0_ADDR) TMR0;
129 extern __sfr __at (PCL_ADDR) PCL;
130 extern __sfr __at (STATUS_ADDR) STATUS;
131 extern __sfr __at (FSR_ADDR) FSR;
132 extern __sfr __at (PORTA_ADDR) PORTA;
133 extern __sfr __at (PORTB_ADDR) PORTB;
134 extern __sfr __at (PORTC_ADDR) PORTC;
135 extern __sfr __at (PORTD_ADDR) PORTD;
136 extern __sfr __at (PORTE_ADDR) PORTE;
137 extern __sfr __at (PCLATH_ADDR) PCLATH;
138 extern __sfr __at (INTCON_ADDR) INTCON;
139 extern __sfr __at (PIR1_ADDR) PIR1;
140 extern __sfr __at (PIR2_ADDR) PIR2;
141 extern __sfr __at (TMR1L_ADDR) TMR1L;
142 extern __sfr __at (TMR1H_ADDR) TMR1H;
143 extern __sfr __at (T1CON_ADDR) T1CON;
144 extern __sfr __at (TMR2_ADDR) TMR2;
145 extern __sfr __at (T2CON_ADDR) T2CON;
146 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
147 extern __sfr __at (SSPCON_ADDR) SSPCON;
148 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
149 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
150 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
151 extern __sfr __at (RCSTA_ADDR) RCSTA;
152 extern __sfr __at (TXREG_ADDR) TXREG;
153 extern __sfr __at (RCREG_ADDR) RCREG;
154 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
155 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
156 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
158 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
159 extern __sfr __at (TRISA_ADDR) TRISA;
160 extern __sfr __at (TRISB_ADDR) TRISB;
161 extern __sfr __at (TRISC_ADDR) TRISC;
162 extern __sfr __at (TRISD_ADDR) TRISD;
163 extern __sfr __at (TRISE_ADDR) TRISE;
164 extern __sfr __at (PIE1_ADDR) PIE1;
165 extern __sfr __at (PIE2_ADDR) PIE2;
166 extern __sfr __at (PCON_ADDR) PCON;
167 extern __sfr __at (PR2_ADDR) PR2;
168 extern __sfr __at (SSPADD_ADDR) SSPADD;
169 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
170 extern __sfr __at (TXSTA_ADDR) TXSTA;
171 extern __sfr __at (SPBRG_ADDR) SPBRG;
173 //----- STATUS Bits --------------------------------------------------------
176 //----- INTCON Bits --------------------------------------------------------
179 //----- PIR1 Bits ----------------------------------------------------------
182 //----- PIR2 Bits ----------------------------------------------------------
185 //----- T1CON Bits ---------------------------------------------------------
188 //----- T2CON Bits ---------------------------------------------------------
191 //----- SSPCON Bits --------------------------------------------------------
194 //----- CCP1CON Bits -------------------------------------------------------
197 //----- RCSTA Bits ---------------------------------------------------------
200 //----- CCP2CON Bits -------------------------------------------------------
203 //----- OPTION Bits --------------------------------------------------------
206 //----- TRISE Bits ---------------------------------------------------------
209 //----- PIE1 Bits ----------------------------------------------------------
212 //----- PIE2 Bits ----------------------------------------------------------
215 //----- PCON Bits ----------------------------------------------------------
218 //----- SSPSTAT Bits -------------------------------------------------------
221 //----- TXSTA Bits ---------------------------------------------------------
224 //==========================================================================
228 //==========================================================================
231 // __BADRAM H'1E'-H'1F',H'8F'-H'91', H'95'-H'97', H'9A'-H'9F'
233 //==========================================================================
235 // Configuration Bits
237 //==========================================================================
239 #define _BODEN_ON 0x3FFF
240 #define _BODEN_OFF 0x3FBF
241 #define _CP_ALL 0x00CF
242 #define _CP_75 0x15DF
243 #define _CP_50 0x2AEF
244 #define _CP_OFF 0x3FFF
245 #define _PWRTE_OFF 0x3FFF
246 #define _PWRTE_ON 0x3FF7
247 #define _WDT_ON 0x3FFF
248 #define _WDT_OFF 0x3FFB
249 #define _LP_OSC 0x3FFC
250 #define _XT_OSC 0x3FFD
251 #define _HS_OSC 0x3FFE
252 #define _RC_OSC 0x3FFF
256 // ----- CCP1CON bits --------------------
259 unsigned char CCP1M0:1;
260 unsigned char CCP1M1:1;
261 unsigned char CCP1M2:1;
262 unsigned char CCP1M3:1;
263 unsigned char CCP1Y:1;
264 unsigned char CCP1X:1;
269 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
271 #define CCP1M0 CCP1CON_bits.CCP1M0
272 #define CCP1M1 CCP1CON_bits.CCP1M1
273 #define CCP1M2 CCP1CON_bits.CCP1M2
274 #define CCP1M3 CCP1CON_bits.CCP1M3
275 #define CCP1Y CCP1CON_bits.CCP1Y
276 #define CCP1X CCP1CON_bits.CCP1X
278 // ----- CCP2CON bits --------------------
281 unsigned char CCP2M0:1;
282 unsigned char CCP2M1:1;
283 unsigned char CCP2M2:1;
284 unsigned char CCP2M3:1;
285 unsigned char CCP2Y:1;
286 unsigned char CCP2X:1;
291 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
293 #define CCP2M0 CCP2CON_bits.CCP2M0
294 #define CCP2M1 CCP2CON_bits.CCP2M1
295 #define CCP2M2 CCP2CON_bits.CCP2M2
296 #define CCP2M3 CCP2CON_bits.CCP2M3
297 #define CCP2Y CCP2CON_bits.CCP2Y
298 #define CCP2X CCP2CON_bits.CCP2X
300 // ----- INTCON bits --------------------
303 unsigned char RBIF:1;
304 unsigned char INTF:1;
305 unsigned char T0IF:1;
306 unsigned char RBIE:1;
307 unsigned char INTE:1;
308 unsigned char T0IE:1;
309 unsigned char PEIE:1;
313 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
315 #define RBIF INTCON_bits.RBIF
316 #define INTF INTCON_bits.INTF
317 #define T0IF INTCON_bits.T0IF
318 #define RBIE INTCON_bits.RBIE
319 #define INTE INTCON_bits.INTE
320 #define T0IE INTCON_bits.T0IE
321 #define PEIE INTCON_bits.PEIE
322 #define GIE INTCON_bits.GIE
324 // ----- OPTION_REG bits --------------------
331 unsigned char T0SE:1;
332 unsigned char T0CS:1;
333 unsigned char INTEDG:1;
334 unsigned char NOT_RBPU:1;
336 } __OPTION_REG_bits_t;
337 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
339 #define PS0 OPTION_REG_bits.PS0
340 #define PS1 OPTION_REG_bits.PS1
341 #define PS2 OPTION_REG_bits.PS2
342 #define PSA OPTION_REG_bits.PSA
343 #define T0SE OPTION_REG_bits.T0SE
344 #define T0CS OPTION_REG_bits.T0CS
345 #define INTEDG OPTION_REG_bits.INTEDG
346 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
348 // ----- PCON bits --------------------
351 unsigned char NOT_BO:1;
352 unsigned char NOT_POR:1;
361 unsigned char NOT_BOR:1;
371 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
373 #define NOT_BO PCON_bits.NOT_BO
374 #define NOT_BOR PCON_bits.NOT_BOR
375 #define NOT_POR PCON_bits.NOT_POR
377 // ----- PIE1 bits --------------------
380 unsigned char TMR1IE:1;
381 unsigned char TMR2IE:1;
382 unsigned char CCP1IE:1;
383 unsigned char SSPIE:1;
384 unsigned char TXIE:1;
385 unsigned char RCIE:1;
387 unsigned char PSPIE:1;
390 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
392 #define TMR1IE PIE1_bits.TMR1IE
393 #define TMR2IE PIE1_bits.TMR2IE
394 #define CCP1IE PIE1_bits.CCP1IE
395 #define SSPIE PIE1_bits.SSPIE
396 #define TXIE PIE1_bits.TXIE
397 #define RCIE PIE1_bits.RCIE
398 #define PSPIE PIE1_bits.PSPIE
400 // ----- PIE2 bits --------------------
403 unsigned char CCP2IE:1;
413 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
415 #define CCP2IE PIE2_bits.CCP2IE
417 // ----- PIR1 bits --------------------
420 unsigned char TMR1IF:1;
421 unsigned char TMR2IF:1;
422 unsigned char CCP1IF:1;
423 unsigned char SSPIF:1;
424 unsigned char TXIF:1;
425 unsigned char RCIF:1;
427 unsigned char PSPIF:1;
430 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
432 #define TMR1IF PIR1_bits.TMR1IF
433 #define TMR2IF PIR1_bits.TMR2IF
434 #define CCP1IF PIR1_bits.CCP1IF
435 #define SSPIF PIR1_bits.SSPIF
436 #define TXIF PIR1_bits.TXIF
437 #define RCIF PIR1_bits.RCIF
438 #define PSPIF PIR1_bits.PSPIF
440 // ----- PIR2 bits --------------------
443 unsigned char CCP2IF:1;
453 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
455 #define CCP2IF PIR2_bits.CCP2IF
457 // ----- PORTA bits --------------------
470 extern volatile __PORTA_bits_t __at(PORTA_ADDR) PORTA_bits;
472 #define RA0 PORTA_bits.RA0
473 #define RA1 PORTA_bits.RA1
474 #define RA2 PORTA_bits.RA2
475 #define RA3 PORTA_bits.RA3
476 #define RA4 PORTA_bits.RA4
477 #define RA5 PORTA_bits.RA5
479 // ----- PORTB bits --------------------
492 extern volatile __PORTB_bits_t __at(PORTB_ADDR) PORTB_bits;
494 #define RB0 PORTB_bits.RB0
495 #define RB1 PORTB_bits.RB1
496 #define RB2 PORTB_bits.RB2
497 #define RB3 PORTB_bits.RB3
498 #define RB4 PORTB_bits.RB4
499 #define RB5 PORTB_bits.RB5
500 #define RB6 PORTB_bits.RB6
501 #define RB7 PORTB_bits.RB7
503 // ----- PORTC bits --------------------
516 extern volatile __PORTC_bits_t __at(PORTC_ADDR) PORTC_bits;
518 #define RC0 PORTC_bits.RC0
519 #define RC1 PORTC_bits.RC1
520 #define RC2 PORTC_bits.RC2
521 #define RC3 PORTC_bits.RC3
522 #define RC4 PORTC_bits.RC4
523 #define RC5 PORTC_bits.RC5
524 #define RC6 PORTC_bits.RC6
525 #define RC7 PORTC_bits.RC7
527 // ----- PORTD bits --------------------
540 extern volatile __PORTD_bits_t __at(PORTD_ADDR) PORTD_bits;
542 #define RD0 PORTD_bits.RD0
543 #define RD1 PORTD_bits.RD1
544 #define RD2 PORTD_bits.RD2
545 #define RD3 PORTD_bits.RD3
546 #define RD4 PORTD_bits.RD4
547 #define RD5 PORTD_bits.RD5
548 #define RD6 PORTD_bits.RD6
549 #define RD7 PORTD_bits.RD7
551 // ----- PORTE bits --------------------
564 extern volatile __PORTE_bits_t __at(PORTE_ADDR) PORTE_bits;
566 #define RE0 PORTE_bits.RE0
567 #define RE1 PORTE_bits.RE1
568 #define RE2 PORTE_bits.RE2
570 // ----- RCSTA bits --------------------
573 unsigned char RX9D:1;
574 unsigned char OERR:1;
575 unsigned char FERR:1;
577 unsigned char CREN:1;
578 unsigned char SREN:1;
580 unsigned char SPEN:1;
583 unsigned char RCD8:1;
599 unsigned char NOT_RC8:1;
609 unsigned char RC8_9:1;
613 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
615 #define RX9D RCSTA_bits.RX9D
616 #define RCD8 RCSTA_bits.RCD8
617 #define OERR RCSTA_bits.OERR
618 #define FERR RCSTA_bits.FERR
619 #define CREN RCSTA_bits.CREN
620 #define SREN RCSTA_bits.SREN
621 #define RX9 RCSTA_bits.RX9
622 #define RC9 RCSTA_bits.RC9
623 #define NOT_RC8 RCSTA_bits.NOT_RC8
624 #define RC8_9 RCSTA_bits.RC8_9
625 #define SPEN RCSTA_bits.SPEN
627 // ----- SSPCON bits --------------------
630 unsigned char SSPM0:1;
631 unsigned char SSPM1:1;
632 unsigned char SSPM2:1;
633 unsigned char SSPM3:1;
635 unsigned char SSPEN:1;
636 unsigned char SSPOV:1;
637 unsigned char WCOL:1;
640 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
642 #define SSPM0 SSPCON_bits.SSPM0
643 #define SSPM1 SSPCON_bits.SSPM1
644 #define SSPM2 SSPCON_bits.SSPM2
645 #define SSPM3 SSPCON_bits.SSPM3
646 #define CKP SSPCON_bits.CKP
647 #define SSPEN SSPCON_bits.SSPEN
648 #define SSPOV SSPCON_bits.SSPOV
649 #define WCOL SSPCON_bits.WCOL
651 // ----- SSPSTAT bits --------------------
666 unsigned char I2C_READ:1;
667 unsigned char I2C_START:1;
668 unsigned char I2C_STOP:1;
669 unsigned char I2C_DATA:1;
676 unsigned char NOT_W:1;
679 unsigned char NOT_A:1;
686 unsigned char NOT_WRITE:1;
689 unsigned char NOT_ADDRESS:1;
706 unsigned char READ_WRITE:1;
709 unsigned char DATA_ADDRESS:1;
714 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
716 #define BF SSPSTAT_bits.BF
717 #define UA SSPSTAT_bits.UA
718 #define R SSPSTAT_bits.R
719 #define I2C_READ SSPSTAT_bits.I2C_READ
720 #define NOT_W SSPSTAT_bits.NOT_W
721 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
722 #define R_W SSPSTAT_bits.R_W
723 #define READ_WRITE SSPSTAT_bits.READ_WRITE
724 #define S SSPSTAT_bits.S
725 #define I2C_START SSPSTAT_bits.I2C_START
726 #define P SSPSTAT_bits.P
727 #define I2C_STOP SSPSTAT_bits.I2C_STOP
728 #define D SSPSTAT_bits.D
729 #define I2C_DATA SSPSTAT_bits.I2C_DATA
730 #define NOT_A SSPSTAT_bits.NOT_A
731 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
732 #define D_A SSPSTAT_bits.D_A
733 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
734 #define CKE SSPSTAT_bits.CKE
735 #define SMP SSPSTAT_bits.SMP
737 // ----- STATUS bits --------------------
743 unsigned char NOT_PD:1;
744 unsigned char NOT_TO:1;
750 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
752 #define C STATUS_bits.C
753 #define DC STATUS_bits.DC
754 #define Z STATUS_bits.Z
755 #define NOT_PD STATUS_bits.NOT_PD
756 #define NOT_TO STATUS_bits.NOT_TO
757 #define RP0 STATUS_bits.RP0
758 #define RP1 STATUS_bits.RP1
759 #define IRP STATUS_bits.IRP
761 // ----- T1CON bits --------------------
764 unsigned char TMR1ON:1;
765 unsigned char TMR1CS:1;
766 unsigned char NOT_T1SYNC:1;
767 unsigned char T1OSCEN:1;
768 unsigned char T1CKPS0:1;
769 unsigned char T1CKPS1:1;
776 unsigned char T1INSYNC:1;
784 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
786 #define TMR1ON T1CON_bits.TMR1ON
787 #define TMR1CS T1CON_bits.TMR1CS
788 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
789 #define T1INSYNC T1CON_bits.T1INSYNC
790 #define T1OSCEN T1CON_bits.T1OSCEN
791 #define T1CKPS0 T1CON_bits.T1CKPS0
792 #define T1CKPS1 T1CON_bits.T1CKPS1
794 // ----- T2CON bits --------------------
797 unsigned char T2CKPS0:1;
798 unsigned char T2CKPS1:1;
799 unsigned char TMR2ON:1;
800 unsigned char TOUTPS0:1;
801 unsigned char TOUTPS1:1;
802 unsigned char TOUTPS2:1;
803 unsigned char TOUTPS3:1;
807 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
809 #define T2CKPS0 T2CON_bits.T2CKPS0
810 #define T2CKPS1 T2CON_bits.T2CKPS1
811 #define TMR2ON T2CON_bits.TMR2ON
812 #define TOUTPS0 T2CON_bits.TOUTPS0
813 #define TOUTPS1 T2CON_bits.TOUTPS1
814 #define TOUTPS2 T2CON_bits.TOUTPS2
815 #define TOUTPS3 T2CON_bits.TOUTPS3
817 // ----- TRISA bits --------------------
820 unsigned char TRISA0:1;
821 unsigned char TRISA1:1;
822 unsigned char TRISA2:1;
823 unsigned char TRISA3:1;
824 unsigned char TRISA4:1;
825 unsigned char TRISA5:1;
830 extern volatile __TRISA_bits_t __at(TRISA_ADDR) TRISA_bits;
832 #define TRISA0 TRISA_bits.TRISA0
833 #define TRISA1 TRISA_bits.TRISA1
834 #define TRISA2 TRISA_bits.TRISA2
835 #define TRISA3 TRISA_bits.TRISA3
836 #define TRISA4 TRISA_bits.TRISA4
837 #define TRISA5 TRISA_bits.TRISA5
839 // ----- TRISB bits --------------------
842 unsigned char TRISB0:1;
843 unsigned char TRISB1:1;
844 unsigned char TRISB2:1;
845 unsigned char TRISB3:1;
846 unsigned char TRISB4:1;
847 unsigned char TRISB5:1;
848 unsigned char TRISB6:1;
849 unsigned char TRISB7:1;
852 extern volatile __TRISB_bits_t __at(TRISB_ADDR) TRISB_bits;
854 #define TRISB0 TRISB_bits.TRISB0
855 #define TRISB1 TRISB_bits.TRISB1
856 #define TRISB2 TRISB_bits.TRISB2
857 #define TRISB3 TRISB_bits.TRISB3
858 #define TRISB4 TRISB_bits.TRISB4
859 #define TRISB5 TRISB_bits.TRISB5
860 #define TRISB6 TRISB_bits.TRISB6
861 #define TRISB7 TRISB_bits.TRISB7
863 // ----- TRISC bits --------------------
866 unsigned char TRISC0:1;
867 unsigned char TRISC1:1;
868 unsigned char TRISC2:1;
869 unsigned char TRISC3:1;
870 unsigned char TRISC4:1;
871 unsigned char TRISC5:1;
872 unsigned char TRISC6:1;
873 unsigned char TRISC7:1;
876 extern volatile __TRISC_bits_t __at(TRISC_ADDR) TRISC_bits;
878 #define TRISC0 TRISC_bits.TRISC0
879 #define TRISC1 TRISC_bits.TRISC1
880 #define TRISC2 TRISC_bits.TRISC2
881 #define TRISC3 TRISC_bits.TRISC3
882 #define TRISC4 TRISC_bits.TRISC4
883 #define TRISC5 TRISC_bits.TRISC5
884 #define TRISC6 TRISC_bits.TRISC6
885 #define TRISC7 TRISC_bits.TRISC7
887 // ----- TRISD bits --------------------
890 unsigned char TRISD0:1;
891 unsigned char TRISD1:1;
892 unsigned char TRISD2:1;
893 unsigned char TRISD3:1;
894 unsigned char TRISD4:1;
895 unsigned char TRISD5:1;
896 unsigned char TRISD6:1;
897 unsigned char TRISD7:1;
900 extern volatile __TRISD_bits_t __at(TRISD_ADDR) TRISD_bits;
902 #define TRISD0 TRISD_bits.TRISD0
903 #define TRISD1 TRISD_bits.TRISD1
904 #define TRISD2 TRISD_bits.TRISD2
905 #define TRISD3 TRISD_bits.TRISD3
906 #define TRISD4 TRISD_bits.TRISD4
907 #define TRISD5 TRISD_bits.TRISD5
908 #define TRISD6 TRISD_bits.TRISD6
909 #define TRISD7 TRISD_bits.TRISD7
911 // ----- TRISE bits --------------------
914 unsigned char TRISE0:1;
915 unsigned char TRISE1:1;
916 unsigned char TRISE2:1;
918 unsigned char PSPMODE:1;
919 unsigned char IBOV:1;
924 extern volatile __TRISE_bits_t __at(TRISE_ADDR) TRISE_bits;
926 #define TRISE0 TRISE_bits.TRISE0
927 #define TRISE1 TRISE_bits.TRISE1
928 #define TRISE2 TRISE_bits.TRISE2
929 #define PSPMODE TRISE_bits.PSPMODE
930 #define IBOV TRISE_bits.IBOV
931 #define OBF TRISE_bits.OBF
932 #define IBF TRISE_bits.IBF
934 // ----- TXSTA bits --------------------
937 unsigned char TX9D:1;
938 unsigned char TRMT:1;
939 unsigned char BRGH:1;
941 unsigned char SYNC:1;
942 unsigned char TXEN:1;
944 unsigned char CSRC:1;
947 unsigned char TXD8:1;
953 unsigned char NOT_TX8:1;
963 unsigned char TX8_9:1;
967 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
969 #define TX9D TXSTA_bits.TX9D
970 #define TXD8 TXSTA_bits.TXD8
971 #define TRMT TXSTA_bits.TRMT
972 #define BRGH TXSTA_bits.BRGH
973 #define SYNC TXSTA_bits.SYNC
974 #define TXEN TXSTA_bits.TXEN
975 #define TX9 TXSTA_bits.TX9
976 #define NOT_TX8 TXSTA_bits.NOT_TX8
977 #define TX8_9 TXSTA_bits.TX8_9
978 #define CSRC TXSTA_bits.CSRC