2 // Register Declarations for Microchip 16C63A Processor
5 // This header file was automatically generated by:
9 // Copyright (c) 2002, Kevin L. Pauba, All Rights Reserved
11 // SDCC is licensed under the GNU Public license (GPL) v2. Note that
12 // this license covers the code to the compiler and other executables,
13 // but explicitly does not cover any code or objects generated by sdcc.
14 // We have not yet decided on a license for the run time libraries, but
15 // it will not put any requirements on code linked against it. See:
17 // http://www.gnu.org/copyleft/gpl/html
19 // See http://sdcc.sourceforge.net/ for the latest information on sdcc.
26 // Register addresses.
28 #define INDF_ADDR 0x0000
29 #define TMR0_ADDR 0x0001
30 #define PCL_ADDR 0x0002
31 #define STATUS_ADDR 0x0003
32 #define FSR_ADDR 0x0004
33 #define PORTA_ADDR 0x0005
34 #define PORTB_ADDR 0x0006
35 #define PORTC_ADDR 0x0007
36 #define PCLATH_ADDR 0x000A
37 #define INTCON_ADDR 0x000B
38 #define PIR1_ADDR 0x000C
39 #define PIR2_ADDR 0x000D
40 #define TMR1L_ADDR 0x000E
41 #define TMR1H_ADDR 0x000F
42 #define T1CON_ADDR 0x0010
43 #define TMR2_ADDR 0x0011
44 #define T2CON_ADDR 0x0012
45 #define SSPBUF_ADDR 0x0013
46 #define SSPCON_ADDR 0x0014
47 #define CCPR1L_ADDR 0x0015
48 #define CCPR1H_ADDR 0x0016
49 #define CCP1CON_ADDR 0x0017
50 #define RCSTA_ADDR 0x0018
51 #define TXREG_ADDR 0x0019
52 #define RCREG_ADDR 0x001A
53 #define CCPR2L_ADDR 0x001B
54 #define CCPR2H_ADDR 0x001C
55 #define CCP2CON_ADDR 0x001D
56 #define OPTION_REG_ADDR 0x0081
57 #define TRISA_ADDR 0x0085
58 #define TRISB_ADDR 0x0086
59 #define TRISC_ADDR 0x0087
60 #define PIE1_ADDR 0x008C
61 #define PIE2_ADDR 0x008D
62 #define PCON_ADDR 0x008E
63 #define PR2_ADDR 0x0092
64 #define SSPADD_ADDR 0x0093
65 #define SSPSTAT_ADDR 0x0094
66 #define TXSTA_ADDR 0x0098
67 #define SPBRG_ADDR 0x0099
70 // Memory organization.
73 #pragma memmap INDF_ADDR INDF_ADDR SFR 0x000 // INDF
74 #pragma memmap TMR0_ADDR TMR0_ADDR SFR 0x000 // TMR0
75 #pragma memmap PCL_ADDR PCL_ADDR SFR 0x000 // PCL
76 #pragma memmap STATUS_ADDR STATUS_ADDR SFR 0x000 // STATUS
77 #pragma memmap FSR_ADDR FSR_ADDR SFR 0x000 // FSR
78 #pragma memmap PORTA_ADDR PORTA_ADDR SFR 0x000 // PORTA
79 #pragma memmap PORTB_ADDR PORTB_ADDR SFR 0x000 // PORTB
80 #pragma memmap PORTC_ADDR PORTC_ADDR SFR 0x000 // PORTC
81 #pragma memmap PCLATH_ADDR PCLATH_ADDR SFR 0x000 // PCLATH
82 #pragma memmap INTCON_ADDR INTCON_ADDR SFR 0x000 // INTCON
83 #pragma memmap PIR1_ADDR PIR1_ADDR SFR 0x000 // PIR1
84 #pragma memmap PIR2_ADDR PIR2_ADDR SFR 0x000 // PIR2
85 #pragma memmap TMR1L_ADDR TMR1L_ADDR SFR 0x000 // TMR1L
86 #pragma memmap TMR1H_ADDR TMR1H_ADDR SFR 0x000 // TMR1H
87 #pragma memmap T1CON_ADDR T1CON_ADDR SFR 0x000 // T1CON
88 #pragma memmap TMR2_ADDR TMR2_ADDR SFR 0x000 // TMR2
89 #pragma memmap T2CON_ADDR T2CON_ADDR SFR 0x000 // T2CON
90 #pragma memmap SSPBUF_ADDR SSPBUF_ADDR SFR 0x000 // SSPBUF
91 #pragma memmap SSPCON_ADDR SSPCON_ADDR SFR 0x000 // SSPCON
92 #pragma memmap CCPR1L_ADDR CCPR1L_ADDR SFR 0x000 // CCPR1L
93 #pragma memmap CCPR1H_ADDR CCPR1H_ADDR SFR 0x000 // CCPR1H
94 #pragma memmap CCP1CON_ADDR CCP1CON_ADDR SFR 0x000 // CCP1CON
95 #pragma memmap RCSTA_ADDR RCSTA_ADDR SFR 0x000 // RCSTA
96 #pragma memmap TXREG_ADDR TXREG_ADDR SFR 0x000 // TXREG
97 #pragma memmap RCREG_ADDR RCREG_ADDR SFR 0x000 // RCREG
98 #pragma memmap CCPR2L_ADDR CCPR2L_ADDR SFR 0x000 // CCPR2L
99 #pragma memmap CCPR2H_ADDR CCPR2H_ADDR SFR 0x000 // CCPR2H
100 #pragma memmap CCP2CON_ADDR CCP2CON_ADDR SFR 0x000 // CCP2CON
101 #pragma memmap OPTION_REG_ADDR OPTION_REG_ADDR SFR 0x000 // OPTION_REG
102 #pragma memmap TRISA_ADDR TRISA_ADDR SFR 0x000 // TRISA
103 #pragma memmap TRISB_ADDR TRISB_ADDR SFR 0x000 // TRISB
104 #pragma memmap TRISC_ADDR TRISC_ADDR SFR 0x000 // TRISC
105 #pragma memmap PIE1_ADDR PIE1_ADDR SFR 0x000 // PIE1
106 #pragma memmap PIE2_ADDR PIE2_ADDR SFR 0x000 // PIE2
107 #pragma memmap PCON_ADDR PCON_ADDR SFR 0x000 // PCON
108 #pragma memmap PR2_ADDR PR2_ADDR SFR 0x000 // PR2
109 #pragma memmap SSPADD_ADDR SSPADD_ADDR SFR 0x000 // SSPADD
110 #pragma memmap SSPSTAT_ADDR SSPSTAT_ADDR SFR 0x000 // SSPSTAT
111 #pragma memmap TXSTA_ADDR TXSTA_ADDR SFR 0x000 // TXSTA
112 #pragma memmap SPBRG_ADDR SPBRG_ADDR SFR 0x000 // SPBRG
116 // P16C63A.INC Standard Header File, Version 1.00 Microchip Technology, Inc.
119 // This header file defines configurations, registers, and other useful bits of
120 // information for the PIC16C63A microcontroller. These names are taken to match
121 // the data sheets as closely as possible.
123 // Note that the processor must be selected before this file is
124 // included. The processor may be selected the following ways:
126 // 1. Command line switch:
127 // C:\ MPASM MYFILE.ASM /PIC16C63A
128 // 2. LIST directive in the source file
130 // 3. Processor Type entry in the MPASM full-screen interface
132 //==========================================================================
136 //==========================================================================
140 //1.00 12/17/97 Initial Release
142 //==========================================================================
146 //==========================================================================
149 // MESSG "Processor-header file mismatch. Verify selected processor."
152 //==========================================================================
154 // Register Definitions
156 //==========================================================================
161 //----- Register Files------------------------------------------------------
163 extern __data __at (INDF_ADDR) volatile char INDF;
164 extern __sfr __at (TMR0_ADDR) TMR0;
165 extern __data __at (PCL_ADDR) volatile char PCL;
166 extern __sfr __at (STATUS_ADDR) STATUS;
167 extern __sfr __at (FSR_ADDR) FSR;
168 extern __sfr __at (PORTA_ADDR) PORTA;
169 extern __sfr __at (PORTB_ADDR) PORTB;
170 extern __sfr __at (PORTC_ADDR) PORTC;
171 extern __sfr __at (PCLATH_ADDR) PCLATH;
172 extern __sfr __at (INTCON_ADDR) INTCON;
173 extern __sfr __at (PIR1_ADDR) PIR1;
174 extern __sfr __at (PIR2_ADDR) PIR2;
175 extern __sfr __at (TMR1L_ADDR) TMR1L;
176 extern __sfr __at (TMR1H_ADDR) TMR1H;
177 extern __sfr __at (T1CON_ADDR) T1CON;
178 extern __sfr __at (TMR2_ADDR) TMR2;
179 extern __sfr __at (T2CON_ADDR) T2CON;
180 extern __sfr __at (SSPBUF_ADDR) SSPBUF;
181 extern __sfr __at (SSPCON_ADDR) SSPCON;
182 extern __sfr __at (CCPR1L_ADDR) CCPR1L;
183 extern __sfr __at (CCPR1H_ADDR) CCPR1H;
184 extern __sfr __at (CCP1CON_ADDR) CCP1CON;
185 extern __sfr __at (RCSTA_ADDR) RCSTA;
186 extern __sfr __at (TXREG_ADDR) TXREG;
187 extern __sfr __at (RCREG_ADDR) RCREG;
188 extern __sfr __at (CCPR2L_ADDR) CCPR2L;
189 extern __sfr __at (CCPR2H_ADDR) CCPR2H;
190 extern __sfr __at (CCP2CON_ADDR) CCP2CON;
192 extern __sfr __at (OPTION_REG_ADDR) OPTION_REG;
193 extern __sfr __at (TRISA_ADDR) TRISA;
194 extern __sfr __at (TRISB_ADDR) TRISB;
195 extern __sfr __at (TRISC_ADDR) TRISC;
196 extern __sfr __at (PIE1_ADDR) PIE1;
197 extern __sfr __at (PIE2_ADDR) PIE2;
198 extern __sfr __at (PCON_ADDR) PCON;
199 extern __sfr __at (PR2_ADDR) PR2;
200 extern __sfr __at (SSPADD_ADDR) SSPADD;
201 extern __sfr __at (SSPSTAT_ADDR) SSPSTAT;
202 extern __sfr __at (TXSTA_ADDR) TXSTA;
203 extern __sfr __at (SPBRG_ADDR) SPBRG;
205 //----- STATUS Bits --------------------------------------------------------
208 //----- INTCON Bits --------------------------------------------------------
211 //----- PIR1 Bits ----------------------------------------------------------
214 //----- PIR2 Bits ----------------------------------------------------------
217 //----- T1CON Bits ---------------------------------------------------------
220 //----- T2CON Bits ---------------------------------------------------------
223 //----- SSPCON Bits --------------------------------------------------------
226 //----- CCP1CON Bits -------------------------------------------------------
229 //----- RCSTA Bits ---------------------------------------------------------
232 //----- CCP2CON Bits -------------------------------------------------------
235 //----- OPTION Bits --------------------------------------------------------
238 //----- PIE1 Bits ----------------------------------------------------------
241 //----- PIE2 Bits ----------------------------------------------------------
244 //----- PCON Bits ----------------------------------------------------------
247 //----- SSPSTAT Bits -------------------------------------------------------
250 //----- TXSTA Bits ---------------------------------------------------------
253 //==========================================================================
257 //==========================================================================
260 // __BADRAM H'08'-H'09', H'1E'-H'1F'
261 // __BADRAM H'88'-H'89', H'8F'-H'91', H'95'-H'97', H'9A'-H'9F'
263 //==========================================================================
265 // Configuration Bits
267 //==========================================================================
269 #define _BODEN_ON 0x3FFF
270 #define _BODEN_OFF 0x3FBF
271 #define _CP_ALL 0x00CF
272 #define _CP_75 0x15DF
273 #define _CP_50 0x2AEF
274 #define _CP_OFF 0x3FFF
275 #define _PWRTE_OFF 0x3FFF
276 #define _PWRTE_ON 0x3FF7
277 #define _WDT_ON 0x3FFF
278 #define _WDT_OFF 0x3FFB
279 #define _LP_OSC 0x3FFC
280 #define _XT_OSC 0x3FFD
281 #define _HS_OSC 0x3FFE
282 #define _RC_OSC 0x3FFF
286 // ----- CCP1CON bits --------------------
289 unsigned char CCP1M0:1;
290 unsigned char CCP1M1:1;
291 unsigned char CCP1M2:1;
292 unsigned char CCP1M3:1;
293 unsigned char CCP1Y:1;
294 unsigned char CCP1X:1;
299 extern volatile __CCP1CON_bits_t __at(CCP1CON_ADDR) CCP1CON_bits;
301 #define CCP1M0 CCP1CON_bits.CCP1M0
302 #define CCP1M1 CCP1CON_bits.CCP1M1
303 #define CCP1M2 CCP1CON_bits.CCP1M2
304 #define CCP1M3 CCP1CON_bits.CCP1M3
305 #define CCP1Y CCP1CON_bits.CCP1Y
306 #define CCP1X CCP1CON_bits.CCP1X
308 // ----- CCP2CON bits --------------------
311 unsigned char CCP2M0:1;
312 unsigned char CCP2M1:1;
313 unsigned char CCP2M2:1;
314 unsigned char CCP2M3:1;
315 unsigned char CCP2Y:1;
316 unsigned char CCP2X:1;
321 extern volatile __CCP2CON_bits_t __at(CCP2CON_ADDR) CCP2CON_bits;
323 #define CCP2M0 CCP2CON_bits.CCP2M0
324 #define CCP2M1 CCP2CON_bits.CCP2M1
325 #define CCP2M2 CCP2CON_bits.CCP2M2
326 #define CCP2M3 CCP2CON_bits.CCP2M3
327 #define CCP2Y CCP2CON_bits.CCP2Y
328 #define CCP2X CCP2CON_bits.CCP2X
330 // ----- INTCON bits --------------------
333 unsigned char RBIF:1;
334 unsigned char INTF:1;
335 unsigned char T0IF:1;
336 unsigned char RBIE:1;
337 unsigned char INTE:1;
338 unsigned char T0IE:1;
339 unsigned char PEIE:1;
343 extern volatile __INTCON_bits_t __at(INTCON_ADDR) INTCON_bits;
345 #define RBIF INTCON_bits.RBIF
346 #define INTF INTCON_bits.INTF
347 #define T0IF INTCON_bits.T0IF
348 #define RBIE INTCON_bits.RBIE
349 #define INTE INTCON_bits.INTE
350 #define T0IE INTCON_bits.T0IE
351 #define PEIE INTCON_bits.PEIE
352 #define GIE INTCON_bits.GIE
354 // ----- OPTION_REG bits --------------------
361 unsigned char T0SE:1;
362 unsigned char T0CS:1;
363 unsigned char INTEDG:1;
364 unsigned char NOT_RBPU:1;
366 } __OPTION_REG_bits_t;
367 extern volatile __OPTION_REG_bits_t __at(OPTION_REG_ADDR) OPTION_REG_bits;
369 #define PS0 OPTION_REG_bits.PS0
370 #define PS1 OPTION_REG_bits.PS1
371 #define PS2 OPTION_REG_bits.PS2
372 #define PSA OPTION_REG_bits.PSA
373 #define T0SE OPTION_REG_bits.T0SE
374 #define T0CS OPTION_REG_bits.T0CS
375 #define INTEDG OPTION_REG_bits.INTEDG
376 #define NOT_RBPU OPTION_REG_bits.NOT_RBPU
378 // ----- PCON bits --------------------
381 unsigned char NOT_BO:1;
382 unsigned char NOT_POR:1;
391 unsigned char NOT_BOR:1;
401 extern volatile __PCON_bits_t __at(PCON_ADDR) PCON_bits;
403 #define NOT_BO PCON_bits.NOT_BO
404 #define NOT_BOR PCON_bits.NOT_BOR
405 #define NOT_POR PCON_bits.NOT_POR
407 // ----- PIE1 bits --------------------
410 unsigned char TMR1IE:1;
411 unsigned char TMR2IE:1;
412 unsigned char CCP1IE:1;
413 unsigned char SSPIE:1;
414 unsigned char TXIE:1;
415 unsigned char RCIE:1;
420 extern volatile __PIE1_bits_t __at(PIE1_ADDR) PIE1_bits;
422 #define TMR1IE PIE1_bits.TMR1IE
423 #define TMR2IE PIE1_bits.TMR2IE
424 #define CCP1IE PIE1_bits.CCP1IE
425 #define SSPIE PIE1_bits.SSPIE
426 #define TXIE PIE1_bits.TXIE
427 #define RCIE PIE1_bits.RCIE
429 // ----- PIE2 bits --------------------
432 unsigned char CCP2IE:1;
442 extern volatile __PIE2_bits_t __at(PIE2_ADDR) PIE2_bits;
444 #define CCP2IE PIE2_bits.CCP2IE
446 // ----- PIR1 bits --------------------
449 unsigned char TMR1IF:1;
450 unsigned char TMR2IF:1;
451 unsigned char CCP1IF:1;
452 unsigned char SSPIF:1;
453 unsigned char TXIF:1;
454 unsigned char RCIF:1;
459 extern volatile __PIR1_bits_t __at(PIR1_ADDR) PIR1_bits;
461 #define TMR1IF PIR1_bits.TMR1IF
462 #define TMR2IF PIR1_bits.TMR2IF
463 #define CCP1IF PIR1_bits.CCP1IF
464 #define SSPIF PIR1_bits.SSPIF
465 #define TXIF PIR1_bits.TXIF
466 #define RCIF PIR1_bits.RCIF
468 // ----- PIR2 bits --------------------
471 unsigned char CCP2IF:1;
481 extern volatile __PIR2_bits_t __at(PIR2_ADDR) PIR2_bits;
483 #define CCP2IF PIR2_bits.CCP2IF
485 // ----- RCSTA bits --------------------
488 unsigned char RX9D:1;
489 unsigned char OERR:1;
490 unsigned char FERR:1;
492 unsigned char CREN:1;
493 unsigned char SREN:1;
495 unsigned char SPEN:1;
498 unsigned char RCD8:1;
514 unsigned char NOT_RC8:1;
524 unsigned char RC8_9:1;
528 extern volatile __RCSTA_bits_t __at(RCSTA_ADDR) RCSTA_bits;
530 #define RX9D RCSTA_bits.RX9D
531 #define RCD8 RCSTA_bits.RCD8
532 #define OERR RCSTA_bits.OERR
533 #define FERR RCSTA_bits.FERR
534 #define CREN RCSTA_bits.CREN
535 #define SREN RCSTA_bits.SREN
536 #define RX9 RCSTA_bits.RX9
537 #define RC9 RCSTA_bits.RC9
538 #define NOT_RC8 RCSTA_bits.NOT_RC8
539 #define RC8_9 RCSTA_bits.RC8_9
540 #define SPEN RCSTA_bits.SPEN
542 // ----- SSPCON bits --------------------
545 unsigned char SSPM0:1;
546 unsigned char SSPM1:1;
547 unsigned char SSPM2:1;
548 unsigned char SSPM3:1;
550 unsigned char SSPEN:1;
551 unsigned char SSPOV:1;
552 unsigned char WCOL:1;
555 extern volatile __SSPCON_bits_t __at(SSPCON_ADDR) SSPCON_bits;
557 #define SSPM0 SSPCON_bits.SSPM0
558 #define SSPM1 SSPCON_bits.SSPM1
559 #define SSPM2 SSPCON_bits.SSPM2
560 #define SSPM3 SSPCON_bits.SSPM3
561 #define CKP SSPCON_bits.CKP
562 #define SSPEN SSPCON_bits.SSPEN
563 #define SSPOV SSPCON_bits.SSPOV
564 #define WCOL SSPCON_bits.WCOL
566 // ----- SSPSTAT bits --------------------
581 unsigned char I2C_READ:1;
582 unsigned char I2C_START:1;
583 unsigned char I2C_STOP:1;
584 unsigned char I2C_DATA:1;
591 unsigned char NOT_W:1;
594 unsigned char NOT_A:1;
601 unsigned char NOT_WRITE:1;
604 unsigned char NOT_ADDRESS:1;
621 unsigned char READ_WRITE:1;
624 unsigned char DATA_ADDRESS:1;
629 extern volatile __SSPSTAT_bits_t __at(SSPSTAT_ADDR) SSPSTAT_bits;
631 #define BF SSPSTAT_bits.BF
632 #define UA SSPSTAT_bits.UA
633 #define R SSPSTAT_bits.R
634 #define I2C_READ SSPSTAT_bits.I2C_READ
635 #define NOT_W SSPSTAT_bits.NOT_W
636 #define NOT_WRITE SSPSTAT_bits.NOT_WRITE
637 #define R_W SSPSTAT_bits.R_W
638 #define READ_WRITE SSPSTAT_bits.READ_WRITE
639 #define S SSPSTAT_bits.S
640 #define I2C_START SSPSTAT_bits.I2C_START
641 #define P SSPSTAT_bits.P
642 #define I2C_STOP SSPSTAT_bits.I2C_STOP
643 #define D SSPSTAT_bits.D
644 #define I2C_DATA SSPSTAT_bits.I2C_DATA
645 #define NOT_A SSPSTAT_bits.NOT_A
646 #define NOT_ADDRESS SSPSTAT_bits.NOT_ADDRESS
647 #define D_A SSPSTAT_bits.D_A
648 #define DATA_ADDRESS SSPSTAT_bits.DATA_ADDRESS
649 #define CKE SSPSTAT_bits.CKE
650 #define SMP SSPSTAT_bits.SMP
652 // ----- STATUS bits --------------------
658 unsigned char NOT_PD:1;
659 unsigned char NOT_TO:1;
665 extern volatile __STATUS_bits_t __at(STATUS_ADDR) STATUS_bits;
667 #define C STATUS_bits.C
668 #define DC STATUS_bits.DC
669 #define Z STATUS_bits.Z
670 #define NOT_PD STATUS_bits.NOT_PD
671 #define NOT_TO STATUS_bits.NOT_TO
672 #define RP0 STATUS_bits.RP0
673 #define RP1 STATUS_bits.RP1
674 #define IRP STATUS_bits.IRP
676 // ----- T1CON bits --------------------
679 unsigned char TMR1ON:1;
680 unsigned char TMR1CS:1;
681 unsigned char NOT_T1SYNC:1;
682 unsigned char T1OSCEN:1;
683 unsigned char T1CKPS0:1;
684 unsigned char T1CKPS1:1;
691 unsigned char T1INSYNC:1;
699 extern volatile __T1CON_bits_t __at(T1CON_ADDR) T1CON_bits;
701 #define TMR1ON T1CON_bits.TMR1ON
702 #define TMR1CS T1CON_bits.TMR1CS
703 #define NOT_T1SYNC T1CON_bits.NOT_T1SYNC
704 #define T1INSYNC T1CON_bits.T1INSYNC
705 #define T1OSCEN T1CON_bits.T1OSCEN
706 #define T1CKPS0 T1CON_bits.T1CKPS0
707 #define T1CKPS1 T1CON_bits.T1CKPS1
709 // ----- T2CON bits --------------------
712 unsigned char T2CKPS0:1;
713 unsigned char T2CKPS1:1;
714 unsigned char TMR2ON:1;
715 unsigned char TOUTPS0:1;
716 unsigned char TOUTPS1:1;
717 unsigned char TOUTPS2:1;
718 unsigned char TOUTPS3:1;
722 extern volatile __T2CON_bits_t __at(T2CON_ADDR) T2CON_bits;
724 #define T2CKPS0 T2CON_bits.T2CKPS0
725 #define T2CKPS1 T2CON_bits.T2CKPS1
726 #define TMR2ON T2CON_bits.TMR2ON
727 #define TOUTPS0 T2CON_bits.TOUTPS0
728 #define TOUTPS1 T2CON_bits.TOUTPS1
729 #define TOUTPS2 T2CON_bits.TOUTPS2
730 #define TOUTPS3 T2CON_bits.TOUTPS3
732 // ----- TXSTA bits --------------------
735 unsigned char TX9D:1;
736 unsigned char TRMT:1;
737 unsigned char BRGH:1;
739 unsigned char SYNC:1;
740 unsigned char TXEN:1;
742 unsigned char CSRC:1;
745 unsigned char TXD8:1;
751 unsigned char NOT_TX8:1;
761 unsigned char TX8_9:1;
765 extern volatile __TXSTA_bits_t __at(TXSTA_ADDR) TXSTA_bits;
767 #define TX9D TXSTA_bits.TX9D
768 #define TXD8 TXSTA_bits.TXD8
769 #define TRMT TXSTA_bits.TRMT
770 #define BRGH TXSTA_bits.BRGH
771 #define SYNC TXSTA_bits.SYNC
772 #define TXEN TXSTA_bits.TXEN
773 #define TX9 TXSTA_bits.TX9
774 #define NOT_TX8 TXSTA_bits.NOT_TX8
775 #define TX8_9 TXSTA_bits.TX8_9
776 #define CSRC TXSTA_bits.CSRC